JPS62104052A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an insulating film from cracking by disposing the sides of wirings of upper and lower layers superposed in parallel on a plane layout separately at least 2mum or more widthwise. CONSTITUTION:The sides of both first and second metal wirings 3, 5 are laterally displaced at the positions where the first and second metal wirings 3, 5 are arranged in parallel in a plane layout at the side separately so that they do not coincide elevationally. The distance delta to be laterally separated is sufficient at least approx. 2mum, and the steps of the interlayer insulating film 4 and a protecting film 6 become smooth. Thus, the insulating films 4, 6 are not abrupt in the sectional shape, nor are reduced in lateral thickness. Accordingly, even if thermal expansion of the films 4 and 6 and stress of metal grains of the wirings 3, 5 are acted on the films 4, 6, it prevents the films 4, 6 from cracking to improve the reliability of a semiconductor device to moisture resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a multilayer wiring structure.

[Conventional technology]

As semiconductor devices, especially semiconductor integrated circuit devices, have become highly integrated in recent years, multilayer wiring structures have been used to interconnect circuit elements configured on a semiconductor substrate or to connect circuit elements to external circuits. . Normally, in this type of multilayer wiring structure, insulation between the upper and lower wiring layers is maintained by forming the lower layer wiring, forming an insulating film between the eyebrows to cover it, and applying the upper layer wiring on top of this. . For this reason,
Each of the upper and lower layer wirings can be extended in any planar pattern without fear of short-circuiting.

[Problem that the invention seeks to solve]

In the above-mentioned multilayer wiring structure, the patterns of the upper and lower wiring can be set freely, so in some cases, the patterns shown in Figure 2 (a)
), the lower layer wiring 13 formed on the insulating film 12 on the surface of the semiconductor substrate 11 and the upper layer wiring 15 formed thereon may extend in parallel, and furthermore, the rewiring 13.15
One side of the two may overlap each other in the vertical direction and the planar direction, or may be disposed very close to each other.

For this reason, the interlayer insulating film 14 provided between the lower layer wiring 13 and the upper layer wiring 15 and the protective film 16 provided on the upper layer wiring 15
overlap at this location on one side, resulting in a steep step, reducing the thickness of the insulating film in the lateral direction at this location, and reducing the mechanical strength of the film. Furthermore, if the upper and lower layer interconnections 13 and 15 are made of metal, each metal grain will affect the interlayer insulating film 14 and the protective film 16, making them vulnerable to thermal shock, which may cause the crank to deteriorate. It becomes more likely to occur.

Such racks cause a significant deterioration in the reliability of semiconductor devices, especially the moisture resistance of plastic-sealed semiconductor devices.

Means for Solving Problem c] The semiconductor device of the present invention solves the above-mentioned problem by preventing the occurrence of steep steps in the insulating film at the sides of the interconnects in the lower layer, which overlap in parallel in a planar layout. In addition, the reliability of the semiconductor device is improved by improving the strength of the insulating film against thermal shock.In addition to overlapping in parallel in a planar layout, the sides of each lower layer wiring are at least 2μ in the width direction.
They are arranged at a distance of at least m.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a plan layout diagram showing a planar pattern shape in one embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line BB.

In the figure, on the insulating film 2 on the surface of the semiconductor substrate 1 is a first metal wiring 3 made of metal such as aluminum as a lower layer wiring.
is formed in a desired planar pattern and covered with a glabella insulating film 4 such as a silicon oxide film. On this interlayer insulating film 4, a second metal wiring 5 made of aluminum or the like is similarly formed in a desired planar pattern as an upper layer wiring, and a protective film 6 is formed on this. In the locations where the sides of the first and second metal wires 3.5 are arranged parallel to each other on the planar layout, the sides of both metal wires 3 and 5 are shifted in the width direction, so that the sides of the first and second metal wires 3. They are placed apart so that they do not match. In order to configure the two metal interconnections 3.5 such that the sides do not match vertically, the second metal interconnection 5 may be configured to overlap more than the first metal interconnection 3 as shown in the figure, or Alternatively, it is conceivable to adopt a method such as configuring the line width of the first metal interconnect 3 to be larger than the line width of the second metal interconnect 5.

The amount δ separating the sides of the upper and lower metal wirings 3.5 from each other in the width direction is determined by the first. each second metal wiring 3,
5 and the thickness of each insulating film 4, 6,
According to various experiments conducted by the present inventors, it has been found that a thickness of at least 2 μm is sufficient, and at the same time, a thickness of more than this is preferable.

According to this configuration, even in locations where the sides of the first metal wiring 3 and the second metal wiring 5 overlap in parallel in a planar pattern, the sides of the both-in lines 3 and 5 are separated from each other by the amount δ in the width direction. Therefore, as shown in FIG. 1(b), the level difference between the interlayer '4fA edge film 4 and the protective film 6 at this location becomes gentle. As a result, these insulating films 4.6 do not have a steep cross-sectional shape, and the lateral thickness of the film 3.5 is not reduced. Therefore, the interlayer insulating film 4 and the protective film 6
Even if stress related to thermal expansion in the metal lines 3, 5 and metal grains of the metal wirings 3, 5 acts on these films 4.6, the films 4.
It is possible to prevent cracks from occurring in the semiconductor device 6, and it is possible to improve reliability of the semiconductor device such as moisture resistance.

In addition, as described above, it is sufficient for the distance δ between each side of the lines 3 and 5 below to be 2 μm in terms of design, even considering the overlay accuracy and patterning accuracy of each wiring pattern.

Further, in the above embodiment, the first. Although an example of a two-layer wiring structure consisting of the second metal wirings 3.5 is shown, a multilayer wiring structure in which three or more layers of wiring are stacked can be similarly implemented. Furthermore, the wiring in each layer is not limited to metal wiring, but can be similarly applied to wiring made of polycrystalline silicon or wiring made of metal silicide.

[Effects of the Invention] As explained above, in the present invention, each side is spaced apart by at least 2 μm in the width direction at a location where the upper and lower layer wirings overlap in parallel on a planar layout, so that the overlapping of these sides is avoided. It is possible to reduce the slope of insulating films such as interlayer insulating films and protective films at certain points, preventing reductions in film thickness and strength, and thereby preventing cracks in insulating films caused by metal grains and thermal expansion. This makes it possible to improve reliability such as moisture resistance of a semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan layout diagram and a BIJI cross-sectional view of one embodiment of the present invention, and FIG. 2(a),
(b) is a plan layout diagram of a conventional structure and its sectional view taken along the line BB. 1.11... Semiconductor substrate, 2.12... Insulating film, 3
゜13...The following line (first metal wiring), 4.14...
Interlayer insulating film, 5, 15... the above line (second metal wiring),
6.16...Protective film, δ...Amount of separation. 1℃1Fi-Figure 1 (a) Figure 1 (b)

Claims (1)

[Scope of Claims] 1. In a semiconductor device having a multilayer wiring structure in which at least two or more layers of wiring are stacked one on top of the other, in locations where the wirings in the upper layer and the lower layer overlap in parallel on a planar layout, At least 2 μm in the width direction of the overlapping sides of
A semiconductor device characterized by being arranged separately. 2. The semiconductor device according to claim 1, wherein each of the upper and lower layer wirings is made of metal wiring such as aluminum.