JPH02184043A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02184043A JPH02184043A JP1004332A JP433289A JPH02184043A JP H02184043 A JPH02184043 A JP H02184043A JP 1004332 A JP1004332 A JP 1004332A JP 433289 A JP433289 A JP 433289A JP H02184043 A JPH02184043 A JP H02184043A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- pads
- chip
- electrical inspection
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000007689 inspection Methods 0.000 claims abstract description 22
- 239000000523 sample Substances 0.000 claims abstract description 10
- 238000012360 testing method Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 6
- 238000000638 solvent extraction Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 2
- 239000011159 matrix material Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Element Separation (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にウェーハ状
態における検査工程を含む半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including an inspection step in a wafer state.
従来、半導体装置の製造においては、半導体ウェーハに
チップ領域を形成した後、良品か不良かを検査してから
チップに切断する。この検査においては、半導体ウェー
ハに形成されている外部リード接続用パッドに探針を立
てて電気的測定を行うのが普通である。即ち、外部接続
用パッドと検査パッドとは共用されている。Conventionally, in the manufacture of semiconductor devices, after chip regions are formed on a semiconductor wafer, the wafer is inspected to determine whether it is good or defective before being cut into chips. In this inspection, electrical measurements are usually made by placing a probe on an external lead connection pad formed on a semiconductor wafer. That is, the external connection pad and the test pad are shared.
この電気的測定における探針の針圧によってパッドに凹
みや傷が発生してしまい、結果的にリード剥れやパッド
剥れが発生し易くなり、十分な接続の信頼性が得られな
いという欠点がある。The disadvantage of this electrical measurement is that the pressure of the probe causes dents and scratches on the pad, resulting in easy lead peeling and pad peeling, making it impossible to obtain sufficient connection reliability. There is.
また、ウェーハ状態での検査時には、ウェーハに形成さ
れている多数のチップ領域の各パッドに探針を接触させ
て測定を行うので、一つのチップ領域に対して時間をか
けて位置合せを行うことは出来ないので、位置合せに時
間がかがらないように、パッドの大きさを５０μｍ口よ
り大きくしていた。即ち、電気的検査用パッドは５０μ
ｍ口より小さくは出来ず、このためチップ占有面積を小
さく出来ないという欠点がある。In addition, when inspecting a wafer, the probe is brought into contact with each pad of a large number of chip areas formed on the wafer to make measurements, so it takes time to align each chip area. Since this is not possible, the size of the pad was made larger than the opening by 50 μm so that alignment would not take much time. That is, the electrical test pad is 50μ
It cannot be made smaller than m openings, and therefore has the disadvantage that the area occupied by the chip cannot be reduced.
しかし、外部リード接続用パッドと検査用パッドとを共
用しないという考え方をとると、外部リード接続は良品
となったチップのみに対して行えば良いので、位置合せ
に時間をかけることができるから、パッドを小さくする
ことができる。ホトリソグラフィ技術を用いて外部接続
用配線を形成することにより外部リード接続用パッドを
小さくする方法が、日経マイクロデバイス、１９８６年
、４月号、４５〜４６頁に発表されている。これについ
て説明しよう。However, if we adopt the idea of not sharing the external lead connection pads and the test pads, we can connect the external leads only to chips that are good, which saves time for alignment. The pad can be made smaller. A method of reducing the size of external lead connection pads by forming external connection wiring using photolithography technology is published in Nikkei Micro Devices, April issue, 1986, pages 45-46. Let me explain this.
第２図は従来の半導体装置の外部接続用配線の形成方法
を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining a conventional method of forming external connection wiring of a semiconductor device.
シリコン基板１１に形成した穴に半導体チップ１２を入
れ、半導体チップ１２とシリコン基板１１との間にエポ
キシ樹脂７を満たす、その後ポリイミド８を表面に塗布
し、ホトリソグラフィ技術を用いてパターニングし、半
導体チップ１２の外部リード接続用パッド３及びシリコ
ン基板１１の上の配線４の部分を開孔し、接続用配線材
料をスパッタ法で堆積し再度ホトリソグラフィ技術を用
いて接続用配線９を形成し、外部リード接続用パッド３
と配線４とを接続する。このように、ホトリソグラフィ
を用いて外部接続が行えると、半導体チップ１２の表面
上の接続用パッド３は、ホトリソグラフィ技術で形成で
きる限界まで小さくすることが可能であり、数μｍ口に
小さくできる。A semiconductor chip 12 is placed in a hole formed in a silicon substrate 11, and an epoxy resin 7 is filled between the semiconductor chip 12 and the silicon substrate 11. Polyimide 8 is then applied to the surface and patterned using photolithography technology to form a semiconductor. Holes are opened in the external lead connection pads 3 of the chip 12 and the wiring 4 on the silicon substrate 11, a connection wiring material is deposited by sputtering, and the connection wiring 9 is formed again using photolithography technology. External lead connection pad 3
and wiring 4 are connected. In this way, if external connections can be made using photolithography, the connection pads 3 on the surface of the semiconductor chip 12 can be made as small as the limit that can be formed using photolithography technology, and can be made as small as several μm. .
以上説明したように、外部リード接続用パッドが縮小で
きる方向であるのに対し、電気的検査用パッドは縮小で
きず、両パッドが共用化されていると、電気検査用パッ
ドの大きさが障害となり、パッドの縮小化ができず、パ
ッドピッチが増大し、チップ周囲に置くパッドの数が大
きく制限されるという欠点がある。As explained above, while external lead connection pads can be reduced in size, electrical testing pads cannot be reduced in size, and if both pads are shared, the size of the electrical testing pads becomes a problem. Therefore, there are disadvantages in that the pads cannot be reduced in size, the pad pitch increases, and the number of pads placed around the chip is greatly limited.
本発明の半導体装置の製造方法は、半導体つ工−ハを格
子状スクライブ領域で仕切って後でチップに切離される
チップ領域を区画し、該チップ領域内に集積回路を形成
する工程と、前記チップ領域の周縁部に外部リード接続
用パッドを設け前記スクライブ領域に電気検査用パッド
を設け前記二つのパッドを配線で接続する工程と、前記
電気検査用パッドに電気検査用探針を立てて前記チップ
領域内に形成された集積回路の良否を検査する工程と、
検査後に前記スクライブ領域で前記半導体ウェーハを切
断して個別のチップに分割する工程とを含んで構成され
る。The method for manufacturing a semiconductor device of the present invention includes the steps of partitioning a semiconductor workpiece with lattice-like scribe areas to define a chip area that will be later separated into chips, and forming an integrated circuit in the chip area; a step of providing an external lead connection pad on the periphery of the chip area, providing an electrical inspection pad on the scribe area and connecting the two pads with wiring, and setting an electrical inspection probe on the electrical inspection pad and performing the A step of inspecting the quality of the integrated circuit formed in the chip area;
The method includes the step of cutting the semiconductor wafer in the scribe area after inspection to divide it into individual chips.
第１図（ａ）、（ｂ）は本発明の一実施例を説明するた
めの平面図及びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' for explaining an embodiment of the present invention.
シリコンウェーハ１には後で半導体チップに分割される
チップ領域２が行列状に多数配置され、スクライブ領域
６で仕切られる。チップ領域２に外部リード接続用パッ
ド３を設ける。スクライブ領域６に電気検査用パッド５
を設け、配線４で接続する。外部接続用パッド３と配線
４と電気検査用パッド５は、例えば厚さ１．０Ｊｉｍの
Ａｔ７で一体化形成される。その上にプラズマＣＶＤ法
等により窒化膜等の保護膜１０を、例えば０．２μｍの
厚さに堆積し、各パッド部を窓あけする。そして、電気
検査用パッド５に探針を立てて電気検査を行う。検査後
、スクライブ領域６の所を切断してチップにする。この
切断により電気検査用パッド５は切り落されることにな
り、最終的にパッケージに組立てたときに、電気検査用
パッド５が半導体チップの入出力端子に容量として付く
ことがない。A large number of chip regions 2, which will later be divided into semiconductor chips, are arranged in rows and columns on a silicon wafer 1, and are partitioned by scribe regions 6. External lead connection pads 3 are provided in the chip area 2. Electrical inspection pad 5 in scribe area 6
and connect it with wiring 4. The external connection pad 3, the wiring 4, and the electrical inspection pad 5 are integrally formed of At7 with a thickness of 1.0 Jim, for example. A protective film 10 such as a nitride film is deposited thereon to a thickness of, for example, 0.2 μm by plasma CVD or the like, and each pad portion is opened. Then, an electrical test is performed by setting a probe on the electrical test pad 5. After inspection, the scribe area 6 is cut into chips. This cutting causes the electrical testing pads 5 to be cut off, so that the electrical testing pads 5 will not be attached as capacitors to the input/output terminals of the semiconductor chip when the package is finally assembled.
このように、電気検査用パッド５と外部リード接続用パ
ッド３とを独立させることにより、電気検査時の探針の
針圧による凹みゃ傷は電気検査用パッド５につくが、外
部リード接続用パッド３にはつかないので、外部リード
接続に支障がなくなリ、また、外部リード接続用パッド
３の面積を縮小することができる。尚、スクライブ前に
、外部リード接続用パッド３と電気検査用パッド５との
間に過電流を流して配線４を溶断しておくと、スクライ
ブ時のぼりが出なくなるので短絡の心配がなくなるので
更に好結果となる。In this way, by making the electrical testing pad 5 and the external lead connection pad 3 independent, the electrical testing pad 5 will be damaged by dents and scratches caused by the pressure of the probe during electrical testing, but the pad 3 for external lead connection will not be damaged. Since it does not touch the pad 3, there is no problem with external lead connection, and the area of the external lead connection pad 3 can be reduced. Furthermore, if you melt the wiring 4 by passing an overcurrent between the external lead connection pad 3 and the electrical inspection pad 5 before scribing, there will be no curling during scribing, so there is no need to worry about short circuits. Good results.
以上説明したように、本発明は、外部リード接続用パッ
ドと電気検査用パッドを別々に形成することにより、電
気検査時の探針の針圧による凹みや傷が外部リード接続
用パッドには全く影響を及ぼさないのでリード接続の信
頼性を上げる効果が有る。As explained above, in the present invention, by forming the external lead connection pad and the electrical inspection pad separately, the external lead connection pad is free from dents and scratches caused by the pressure of the probe during electrical inspection. This has the effect of increasing the reliability of lead connections since it does not have any adverse effects.
部リード接続用パッド、４・・・配線、５・・・電気検
査用パッド、６・・・スクライブ領域、７・・・エポキ
シ樹脂、８・・・ポリイミド、９・・・接続配線、１０
・・・保護膜、１１・・・シリコン基板、１２・・・半
導体チップ。Lead connection pad, 4... Wiring, 5... Electrical inspection pad, 6... Scribe area, 7... Epoxy resin, 8... Polyimide, 9... Connection wiring, 10
. . . Protective film, 11 . . . Silicon substrate, 12 . . . Semiconductor chip.
Claims (1)
チップに切離されるチップ領域を区画し、該チップ領域
内に集積回路を形成する工程と、前記チップ領域の周縁
部に外部リード接続用パッドを設け前記スクライブ領域
に電気検査用パッドを設け前記二つのパッドを配線で接
続する工程と、前記電気検査用パッドに電気検査用探針
を立てて前記チップ領域内に形成された集積回路の良否
を検査する工程と、検査後に前記スクライブ領域で前記
半導体ウェーハを切断して個別のチップに分割する工程
とを含むことを特徴とする半導体装置の製造方法。A process of partitioning a semiconductor wafer with lattice-like scribe areas to define chip areas to be later separated into chips, forming integrated circuits in the chip areas, and providing external lead connection pads on the periphery of the chip areas. A step of providing an electrical testing pad in the scribe area and connecting the two pads with wiring, and testing the quality of the integrated circuit formed in the chip area by setting an electrical testing probe on the electrical testing pad. and a step of cutting the semiconductor wafer in the scribe area to divide it into individual chips after inspection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1004332A JPH02184043A (en) | 1989-01-10 | 1989-01-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1004332A JPH02184043A (en) | 1989-01-10 | 1989-01-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02184043A true JPH02184043A (en) | 1990-07-18 |
Family
ID=11581497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1004332A Pending JPH02184043A (en) | 1989-01-10 | 1989-01-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02184043A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997012395A1 (en) * | 1995-09-27 | 1997-04-03 | Micrel, Inc. | Circuit having trim pads formed in scribe channel |
| US5962926A (en) * | 1997-09-30 | 1999-10-05 | Motorola, Inc. | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
| US5982042A (en) * | 1996-03-18 | 1999-11-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor wafer including semiconductor device |
| US6445001B2 (en) * | 1996-06-12 | 2002-09-03 | Kabushiki Kaisha Toshiba | Semiconductor device with flip-chip structure and method of manufacturing the same |
| JP2006269592A (en) * | 2005-03-23 | 2006-10-05 | Fuji Photo Film Co Ltd | Solid-state image sensor and manufacturing method thereof |
| CN110444485A (en) * | 2018-05-03 | 2019-11-12 | 紫光同芯微电子有限公司 | A kind of chip electrode parallel construction with packaging and testing effect |
-
1989
- 1989-01-10 JP JP1004332A patent/JPH02184043A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997012395A1 (en) * | 1995-09-27 | 1997-04-03 | Micrel, Inc. | Circuit having trim pads formed in scribe channel |
| US5710538A (en) * | 1995-09-27 | 1998-01-20 | Micrel, Inc. | Circuit having trim pads formed in scribe channel |
| US5982042A (en) * | 1996-03-18 | 1999-11-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor wafer including semiconductor device |
| US6445001B2 (en) * | 1996-06-12 | 2002-09-03 | Kabushiki Kaisha Toshiba | Semiconductor device with flip-chip structure and method of manufacturing the same |
| US5962926A (en) * | 1997-09-30 | 1999-10-05 | Motorola, Inc. | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
| KR100369913B1 (en) * | 1997-09-30 | 2003-06-19 | 모토로라 인코포레이티드 | Semiconductor device consisting of multiple overlapping rows of coupling pads with conductive interconnects |
| JP2006269592A (en) * | 2005-03-23 | 2006-10-05 | Fuji Photo Film Co Ltd | Solid-state image sensor and manufacturing method thereof |
| JP4677260B2 (en) * | 2005-03-23 | 2011-04-27 | 富士フイルム株式会社 | Manufacturing method of solid-state imaging device |
| CN110444485A (en) * | 2018-05-03 | 2019-11-12 | 紫光同芯微电子有限公司 | A kind of chip electrode parallel construction with packaging and testing effect |
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