JPH0221622A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0221622A JPH0221622A JP63170623A JP17062388A JPH0221622A JP H0221622 A JPH0221622 A JP H0221622A JP 63170623 A JP63170623 A JP 63170623A JP 17062388 A JP17062388 A JP 17062388A JP H0221622 A JPH0221622 A JP H0221622A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- film formed
- pad
- cvd method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 238000004528 spin coating Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 9
- 238000002161 passivation Methods 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- QGVYLCICHZYPJA-UHFFFAOYSA-N [Cr].[Cu].[Au] Chemical compound [Cr].[Cu].[Au] QGVYLCICHZYPJA-UHFFFAOYSA-N 0.000 description 1
- QPTXTHGOGURUON-UHFFFAOYSA-N copper gold titanium Chemical compound [Ti][Cu][Au] QPTXTHGOGURUON-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にギヤングボンディング
用の突起電極を有する半導体装置の保護用絶縁膜の構造
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a protective insulating film of a semiconductor device having a protruding electrode for gigantic bonding.
従来、この種の半導体装置は、第２図に示すような構造
を有していた。Conventionally, this type of semiconductor device has had a structure as shown in FIG.
第２図において、１は半導体基板、２は層間絶縁膜、３
は外部引き出し用のＡｆｆｌパッド、４Ａ。In FIG. 2, 1 is a semiconductor substrate, 2 is an interlayer insulating film, and 3 is a semiconductor substrate.
Affl pad for external drawer, 4A.
４Ｂは最小間隔で形成された内部のＡｆｆｌ配線である
。そして、これらＡ、Ｒ配線４Ａ、４Ｂ上およびＡρパ
ット３の周辺上に形成される保護用絶縁膜（以下パッシ
ベーション膜という）は、常圧もしくは低圧のＣＶＤ法
による厚さ０．５〜１．０μｍの酸化シリコン膜１０と
ピンホールの少ないプラズマＣＶＤ法による厚さ０．２
〜１．０μｍの窒化膜１１の２層構造となっていた。4B is an internal Affl wiring formed at minimum intervals. A protective insulating film (hereinafter referred to as a passivation film) formed on these A and R wirings 4A and 4B and on the periphery of the Aρ pad 3 has a thickness of 0.5 to 1.5 cm by normal pressure or low pressure CVD method. Silicon oxide film 10 of 0 μm and thickness 0.2 by plasma CVD method with few pinholes
It had a two-layer structure of a nitride film 11 of ~1.0 μm.
そして、ＡＩパッド中央部にはバリアメタル８を介して
突起電極（以下バンプという）９が形成されている。こ
の時バリアメタル８はチタン−パラジウム、チタン−白
金、チタン−銅−金、クロム−銅−金などの２層以上の
膜で形成され、バンプは金、銅、半田などの材料で形成
される。A protruding electrode (hereinafter referred to as a bump) 9 is formed at the center of the AI pad with a barrier metal 8 interposed therebetween. At this time, the barrier metal 8 is formed of two or more layers of films such as titanium-palladium, titanium-platinum, titanium-copper-gold, and chromium-copper-gold, and the bumps are formed of materials such as gold, copper, and solder. .
しかしながら、上述した従来の半導体装置におけるパッ
シベーション膜は、Ａ！２配線４Ａ、４Ｂ間に凹部１２
や空洞部１３が形成されやすく、後工程でバンブ９の形
成を行ない、バリアメタル８をエツチングによって除去
する場合、これら凹部１２や空洞部１３の形成された領
域がエツチングに対して弱く、下のＡ１配線４Ａ、４Ｂ
までエツチングされるという欠点があった。また、ＡＩ
配線がエツチングされない場合でもピンホールのため耐
湿性が劣化し、信頼性が低下するという問題点があった
。However, the passivation film in the conventional semiconductor device described above is A! Recess 12 between 2 wirings 4A and 4B
When bumps 9 are formed in a later process and barrier metal 8 is removed by etching, the regions where these recesses 12 and cavities 13 are formed are vulnerable to etching, and the underlying A1 wiring 4A, 4B
The disadvantage was that it was etched up to the point. Also, AI
Even when the wiring is not etched, there is a problem in that the moisture resistance deteriorates due to the pinholes, resulting in a decrease in reliability.
本発明の目的は、耐エツチング性および耐湿性の向上し
たパッシベーション膜を有する信頼性の高い半導体装置
を提供することにある。An object of the present invention is to provide a highly reliable semiconductor device having a passivation film with improved etching resistance and moisture resistance.
本発明の半導体装置は、半導体基板上に層間絶縁膜を介
して形成された金属パッドと金属配線と、前記金属パッ
ドの周辺部上および前記金属配線上に形成された保護用
絶縁膜と、前記金属パッド上にバリア用の金属層を介し
て形成された突起電極を有する半導体装置において、前
記保護用絶縁膜は順次形成されたＣＶＤ法による第１の
絶縁膜と回転塗布法による第２の絶縁膜とＣＶＤ法に゛
よる第３の絶縁膜とから構成されているものである。The semiconductor device of the present invention includes: a metal pad and a metal wiring formed on a semiconductor substrate via an interlayer insulating film; a protective insulating film formed on a peripheral portion of the metal pad and on the metal wiring; In a semiconductor device having a protruding electrode formed on a metal pad via a barrier metal layer, the protective insulating film includes a first insulating film formed by a CVD method and a second insulating film formed by a spin coating method. It is composed of a film and a third insulating film formed by CVD.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第１図において、半導体基板１上には、酸化シリコン膜
等からなる層間絶縁膜２を介してＡηバッド３及びＡ、
＆配線４Ａ、４Ｂが形成されている。そして、Ａｊ２バ
ッド３の周辺部上及びＡｆｆｌ配線４Ａ、４Ｂ上には、
３層の絶縁膜からなるパッシベーション膜が形成されて
いる。In FIG. 1, Aη pads 3 and A,
& Wirings 4A and 4B are formed. Then, on the peripheral part of Aj2 bad 3 and on Affl wiring 4A, 4B,
A passivation film consisting of three layers of insulating films is formed.
すなわち、パッシベーション膜は、常圧または低圧ＣＶ
Ｄ法による厚さ０．１〜０．３μｍの酸化シリコン膜か
らなる第１の絶縁Ｍ５と、回転塗布法による厚さ０．３
〜０，５μｍの酸化シリコン膜からなる第２の絶縁膜６
と、ピンホールの少ないプラズマＣＶＤ法による厚さ約
０，５μｍの窒化シリコン膜からなる第３の絶縁膜７と
から構成されている。そして、Ａ、＆パッド３の中央部
には、厚さ０．１〜０．５μｍのチタン−銅、チタン−
金等からなるバリアメタル８を介して金や銅等からなる
バンブ９が形成されている。That is, the passivation film can be used at normal pressure or low pressure CV.
A first insulation M5 made of a silicon oxide film with a thickness of 0.1 to 0.3 μm by the D method and a thickness of 0.3 μm by the spin coating method.
A second insulating film 6 made of silicon oxide film with a thickness of ~0.5 μm
and a third insulating film 7 made of a silicon nitride film with a thickness of about 0.5 μm formed by the plasma CVD method with few pinholes. Then, in the center part of A, & pad 3, titanium-copper and titanium-copper with a thickness of 0.1 to 0.5 μm
A bump 9 made of gold, copper, etc. is formed through a barrier metal 8 made of gold or the like.
このように構成された本実施例においては、パッシベー
ション膜が３層の絶縁膜で形成されているため、特に第
２の絶縁膜６が回転塗布法により形成されていることに
より、Ａ、Ｒ配線４Ａ、４Ｂ間に空洞部や四部が形成さ
れることはなくなる。In this embodiment configured as described above, since the passivation film is formed of three layers of insulating films, the second insulating film 6 is formed by a spin coating method, so that the A and R wirings are No cavity or four parts are formed between 4A and 4B.
従って、後工程においてバリアメタル８をエツチングし
た場合でも、Ａρ配線４Ａ、４Ｂがエツチングされるこ
とはなくなり、耐湿性ら向上したものとなる。Therefore, even if the barrier metal 8 is etched in a later step, the Aρ wirings 4A and 4B will not be etched, resulting in improved moisture resistance.
以上説明したように本発明は、金属パッドの周辺部上お
よび金属配線上に形成される保護用絶縁膜を、ＣＶＤ法
による第１の絶縁膜と回転塗布法による第２の絶縁膜と
ＣＶＤ法による第３の絶縁膜とで構成することにより、
耐エツチング性および耐湿性が向上するため、信頼性の
高い半導体装置が得られる。As explained above, in the present invention, a protective insulating film formed on the peripheral portion of a metal pad and on a metal wiring is formed using a first insulating film formed by a CVD method, a second insulating film formed by a spin coating method, and a second insulating film formed by a CVD method. By configuring with the third insulating film,
Since etching resistance and moisture resistance are improved, a highly reliable semiconductor device can be obtained.
第１図は本発明の一実施例の断面図、第２図は従来の半
導体装置の断面図である。
１・・・半導体基板、２・・・層間絶縁膜、３・・・Ａ
ρパッド、４Ａ、４Ｂ・・・Ａη配線、５・・・第１の
絶縁膜、６・・・第２の絶縁膜、７・・・第３絶縁膜、
８・・・バリアメタル、９・・・バンブ、１０・・・酸
化シリコン膜、１１・・・窒化膜、１２・・・凹部、１
３・・・空洞部。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Interlayer insulating film, 3... A
ρ pad, 4A, 4B... Aη wiring, 5... first insulating film, 6... second insulating film, 7... third insulating film,
8... Barrier metal, 9... Bump, 10... Silicon oxide film, 11... Nitride film, 12... Concave portion, 1
3...Cavity part.
Claims (1)
ドと金属配線と、前記金属パッドの周辺部上および前記
金属配線上に形成された保護用絶縁膜と、前記金属パッ
ド上にバリア用の金属層を介して形成された突起電極を
有する半導体装置において、前記保護用絶縁膜は順次形
成されたＣＶＤ法による第１の絶縁膜と回転塗布法によ
る第２の絶縁膜とＣＶＤ法による第３の絶縁膜とから構
成されていることを特徴とする半導体装置。A metal pad and a metal wiring formed on a semiconductor substrate via an interlayer insulating film, a protective insulating film formed on a peripheral portion of the metal pad and on the metal wiring, and a barrier film formed on the metal pad. In a semiconductor device having a protruding electrode formed through a metal layer, the protective insulating film includes a first insulating film formed by CVD, a second insulating film formed by spin coating, and a third insulating film formed by CVD. A semiconductor device comprising an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63170623A JPH0221622A (en) | 1988-07-08 | 1988-07-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63170623A JPH0221622A (en) | 1988-07-08 | 1988-07-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221622A true JPH0221622A (en) | 1990-01-24 |
Family
ID=15908307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63170623A Pending JPH0221622A (en) | 1988-07-08 | 1988-07-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221622A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6387794B2 (en) | 1995-07-14 | 2002-05-14 | Matsushita Electric Industrial Co., Ltd. | Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device |
| US6818539B1 (en) | 1999-06-30 | 2004-11-16 | Seiko Epson Corporation | Semiconductor devices and methods of fabricating the same |
| JP2006179663A (en) * | 2004-12-22 | 2006-07-06 | Seiko Epson Corp | Semiconductor device and its manufacturing method, and semiconductor package |
-
1988
- 1988-07-08 JP JP63170623A patent/JPH0221622A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6387794B2 (en) | 1995-07-14 | 2002-05-14 | Matsushita Electric Industrial Co., Ltd. | Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device |
| US6603207B2 (en) | 1995-07-14 | 2003-08-05 | Matsushita Electric Industrial Co., Ltd. | Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device |
| US6818539B1 (en) | 1999-06-30 | 2004-11-16 | Seiko Epson Corporation | Semiconductor devices and methods of fabricating the same |
| US7285863B2 (en) | 1999-06-30 | 2007-10-23 | Seiko Epson Corporation | Pad structures including insulating layers having a tapered surface |
| JP2006179663A (en) * | 2004-12-22 | 2006-07-06 | Seiko Epson Corp | Semiconductor device and its manufacturing method, and semiconductor package |
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