JPS62252174A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET having high integration and high performance by grounding an insular source electrode through a front surface penetrating hole and a back surface penetrating hole to a back surface electrode. CONSTITUTION:An FET 1 is formed of a semi-insulating substrate 2, an operating layer 3 formed by ion implanting to the substrate 2, a source electrode 4, a drain electrode 5, a gate electrode 6, and leads 7, 8. The insular electrode 4 is electrically connected through a front surface penetrating hole 11 penetrating the substrate 2 and the layer 3 and a back surface penetrating hole 12 with a back surface electrode 10. Thus, when the thicknesses of the substrates are the same, a viahole can be formed in the hole area of l/2 of that of the conventional one, thereby effectively integrating it.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode structure for realizing high performance of a semiconductor device, a patented lateral field effect transistor (FET).

[Conventional technology]

Conventionally, as this type of device, IEEE TRANSAC
-TIONS ON MICROWAVE Tf (EO
RY AND TECH-NIQUES VOL MT
T-29Nns JUNE 1981. In these figures, (1) is FE
T, t2+ are semi-insulating substrates, (3) are semi-insulating substrates (
2) is an active layer formed by ion implantation or the like, (41 and +51 are source and drain electrodes, and (6) is a gate electrode formed with fζ to make a Schottky contact. (7) and (8) ) are drain and gate leads for connection to an external circuit (not shown), respectively.The source electrode (4) is a Pi7 hole that penetrates the semi-insulating substrate (2) and the active layer (3). The back electrode [ll (is electrically connected) through (9).

For example, in the case of a V-channel FET, the source electrode is grounded via the via hole (9) and the back electrode αG. The gate electrode (6) is the input side of the high frequency signal. is connected to the external circuit Sζ via
A negative voltage is applied as a DC bias. The drain electrode 15) is connected to an external circuit as a high-frequency signal output side via a drain lead wire, and a positive voltage is applied as a DC bias.

As described above, an FET is often used as a so-called high-frequency amplifier that inputs and outputs a high-frequency signal to the gate electrode (6).

Here, in order to increase the gain of the amplifier, it is essential to reduce the source resistance and source inductance of 1ζ. By directly grounding the source electrode (4) through the 1ζ via hole (9) without using a wire, it is effective (ζ) to reduce the source resistance and source inductance.

[Problem that the invention seeks to solve]

A conventional FET having a Pi7 hole has a via hole structure in which the hole is opened from the back surface of the semiconductor substrate and penetrates to the source electrode on the front surface. On the other hand, when considering high frequency transmission loss, the thicker the semiconductor substrate, the lower the loss (the original performance of FET can be obtained. However, as the thickness of the semiconductor substrate increases, the conventional via hole structure The opening area on the back surface becomes larger, and the area of the via hole portion occupied by the chip Iζ becomes larger.This is disadvantageous for integration.

This invention is a novel semiconductor that achieves high gain due to the low source resistance and low source inductance 1ζ of the via hole structure, and also enables reduction of transmission loss and high integration by using a thick semiconductor substrate. The purpose is to obtain equipment.

[Means for solving problems]

The present invention utilizes at least one or more island-shaped source electrode portions (a front through hole formed on the ζ surface and a back through hole formed on the Eζζ surface corresponding to Cζ) as a via hole for the source electrode. , the back surface of the FET is used as the source electrode terminal.

[Effect]

By employing the surface via hole structure in this invention, integration is possible without impairing the low source resistance and low source inductance of the via hole.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in FIGS.
Figure M-π line cross-sectional view) Iζ is shown. In these tatami mats ζ,
till 1. is the surface through hole of the island-shaped source electrode (4), and is electrically connected to the back electrode u0 via the back surface through hole (121).
The same reference numerals as in the figures indicate the same or corresponding parts.

In the case of the via hole having the structure of this example, if each of the surface through hole or the bottom surface through hole has the same opening area as the conventional via hole, it can be applied to a semiconductor substrate that is twice as thick as the conventional one. I can do things. Similarly, if the thickness of the semiconductor substrate is the same, a via hole can be formed with the conventional opening area of 172, so integration is effective. Therefore, a thick semiconductor substrate 1ζ with low high-frequency transmission loss can be applied without sacrificing the low source resistance and low source inductance of the via hole structure, allowing for high-performance FETs.
There will be an emperor who will realize this.

In addition, in the above embodiment, the case where there is only one island-shaped source electrode was explained, but the present invention can be applied even if a plurality of island-shaped source electrodes are arranged, such as in a power FET. .

In addition, in the case of a power FET, since the back electrode of the NET is formed by thick plating fζ, a heat dissipation effect can be expected.

〔Effect of the invention〕

As described above (ζ), according to the present invention, the island-shaped source electrode is configured to be grounded to the back electrode through the front surface through hole and the back surface through hole.
ET can be realized.

[Brief Description of the Drawings] Fig. 1 is a top view of an FET showing one embodiment of the present invention, Fig. 2 is a top view of an FET showing an embodiment of the present invention;
The figure is a sectional view taken along the line ■-■ in Figure 1, Figure 8 is a top view of a conventional FET, and Figure 4 is the rv-Th line in Figure 8.
FIG. 3 is a cross-sectional view taken along a line. (1) is FET1 (2+ is a semi-insulating substrate, 13) is an active layer, (4) is a source electrode, (5) is a drain electrode, (6)
) is the gate electrode, 17) is the drain lead wire, (8) is the gate lead, wire, (9) is the conventional via hole, 41
G is a back surface electrode, aD is a surface through hole, and (2) is a back surface through hole. Note that the same reference numerals in the figures indicate the same or corresponding parts. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Procedure amendment written spontaneously) 611225 “Showa year, month, day l, case description Japanese Patent Application No. 1983-95619 2, title of the invention Semiconductor device 3, representative of the person making the amendment Moriya Shiki 4, Agent 5, Detailed explanation of the invention column 6 of the specification subject to amendment, Contents of the amendment (1) ``Figure 1'' on page 1, line 20 of the specification has been replaced with ``Figure 3''.
Correct it to "Fig." (2) Similarly, “V channel” on page 2, line 11, r n
Correct as "channel". (3) Also on page 3, line 10, “F with via hole”
ETJ, [FET (1) with via hole (9)
) Correct as J. (4) Similarly, "source electrode" on page 3, line 11 and page 5, line 14 are corrected to "source electrode (4)". (5) Similarly, “Figures 1 and 2” on page 5, lines 1 and 2.
is corrected as "Fig. 3 and Fig. 4". (6) Similarly, change the "front through hole or back through hole" on page 5, line 4 to [front through hole (11) or back through hole (12).
) Correct as J. that's all

Claims (1)

[Claims] In a lateral field effect transistor having a drain electrode, a gate electrode, and an island-shaped source electrode on one main surface, a surface through-hole formed from the main surface in at least one source electrode portion and a corresponding one on the other main surface. A semiconductor device characterized in that the formed back surface through-holes are electrically connected.