JPS6236400B2 - - Google Patents
Info
- Publication number
- JPS6236400B2 JPS6236400B2 JP17875981A JP17875981A JPS6236400B2 JP S6236400 B2 JPS6236400 B2 JP S6236400B2 JP 17875981 A JP17875981 A JP 17875981A JP 17875981 A JP17875981 A JP 17875981A JP S6236400 B2 JPS6236400 B2 JP S6236400B2
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- region
- electrode
- gate electrode
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- FHUGMWWUMCDXBC-UHFFFAOYSA-N gold platinum titanium Chemical compound [Ti][Pt][Au] FHUGMWWUMCDXBC-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は電界効果トランジスタに関し、特にソ
ース電極の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a field effect transistor, and particularly to the structure of a source electrode.
(2) 従来技術と問題点
GaAsよりなる超高周波用シヨツトキバリア型
電界効果トランジスタ等においては、ソース電極
として従来第１図に示すような構造が既に提唱さ
れている。即ち、半絶縁性基板１表面に形成され
たｎ型のGaAsからなる能動層２上に、能動層２
とシヨツトキ接触をなすゲート電極３と、能動層
２とオーミツク接触をなすソース電極４及びドレ
イン電極５を有し、一方半絶縁性基板１の背面に
は前記ソース電極４形成部に半絶縁性基板１及び
能動層２を貫通する貫通孔６が開孔され、この貫
通孔６の内壁面を含む半絶縁性基板１の背面上に
AuGe合金層と金（Au）層が積層された蒸着層７
とその上にAuのメツキ層８とからなる背面電極
９を介して外部に接続されている。(2) Prior Art and Problems In ultra-high frequency shot barrier type field effect transistors made of GaAs, a structure as shown in FIG. 1 has been proposed for the source electrode. That is, the active layer 2 is formed on the active layer 2 made of n-type GaAs formed on the surface of the semi-insulating substrate 1.
It has a gate electrode 3 that is in horizontal contact with the active layer 2, and a source electrode 4 and a drain electrode 5 that are in ohmic contact with the active layer 2. On the other hand, on the back side of the semi-insulating substrate 1, there is a semi-insulating substrate in the area where the source electrode 4 is formed. 1 and the active layer 2, a through hole 6 is formed on the back surface of the semi-insulating substrate 1 including the inner wall surface of the through hole 6.
Vapor deposited layer 7 in which an AuGe alloy layer and a gold (Au) layer are laminated
It is connected to the outside via a back electrode 9 consisting of a plating layer 8 of Au on top of the back electrode 9.
上記従来の構造では厚いAuメツキ層８（凡そ
35〜50〔μｍ〕の厚さ）がヒートシンクとして働
き放熱特性が良好となる。その反面、貫通孔６を
開孔するに際しては、ソース電極４の裏面が露出
するまでエツチングを行なわなければならない
が、エツチングはソース電極４の裏面に到達する
とソース電極４と能動層２の界面に沿つて急速に
進行するので、ソース電極４の剥離を生じやす
い。従つてエツチング量を厳密に制御せねばなら
ないがこの制御は実際には困難で、そのため常に
上述の如く望ましくないエツチングが進行すると
いう危険にさらされる。 In the above conventional structure, the thick Au plating layer 8 (approximately
The thickness of 35 to 50 [μm] acts as a heat sink and provides good heat dissipation characteristics. On the other hand, when opening the through hole 6, etching must be performed until the back surface of the source electrode 4 is exposed; Since the source electrode 4 rapidly progresses along the line, peeling of the source electrode 4 is likely to occur. Therefore, the amount of etching must be strictly controlled, but this control is difficult in practice, and therefore there is always a risk that undesirable etching will proceed as described above.
(3) 発明の目的
本発明の目的は上記問題点を解消して前記望ま
しくないエツチングを生じる危険がなく、しかも
製作容易な構造を有する電界効果トランジスタを
提供することにある。(3) Object of the Invention An object of the present invention is to solve the above-mentioned problems and provide a field effect transistor which is free from the risk of causing the undesirable etching and has a structure that is easy to manufacture.
(4) 発明の構成
本発明によれば上記目的は、ソース領域として
高不純物濃度の領域を設け、基板の背面から高不
純物濃度領域の底面まで達するが表面までは達し
ないように配設された接続導体により高不純物濃
度領域と基板背面の背面電極とを接続する構造と
することにより達成される。(4) Structure of the Invention According to the present invention, the above object is to provide a region with a high impurity concentration as a source region, and arrange it so that it reaches from the back side of the substrate to the bottom of the high impurity concentration region but does not reach the surface. This is achieved by using a structure in which the high impurity concentration region and the back electrode on the back side of the substrate are connected by a connecting conductor.
以下本発明の一実施例として本発明により製作
したGaAsにりなる超高周波電界効果トランジス
タを図面により接続する。 Hereinafter, as an embodiment of the present invention, ultra-high frequency field effect transistors made of GaAs manufactured according to the present invention will be connected according to the drawings.
第２図は上記一実施例を示す要部断面図で、第
１図と同一部分は同一符号で示してある。 FIG. 2 is a sectional view of a main part showing the above embodiment, and the same parts as in FIG. 1 are designated by the same reference numerals.
同図において、１はクロム（Cr）をドープさ
れたGaAsよりなる半絶縁性基板、２はｎ型の
GaAsよりなる能動層で、ゲート電極３の直下部
１１はイオン注入法によりシリコン（Si）、硫黄
（Ｓ）等のｎ型不純物が注入された濃度凡そ0.5〜
３×1017〔cm-3〕のｎ型領域、該ｎ型領域１１を
挾んで両側にシリコン（Si）を２×1018〔cm-3〕
以上の濃度に注入されたn+領域１２及び１３の
三つの領域からなる。 In the figure, 1 is a semi-insulating substrate made of GaAs doped with chromium (Cr), and 2 is an n-type substrate.
The active layer is made of GaAs, and the layer 11 directly below the gate electrode 3 is doped with n-type impurities such as silicon (Si) and sulfur (S) by ion implantation at a concentration of approximately 0.5 to 0.5.
An n-type region of 3×10 17 [cm -3 ] and silicon (Si) of 2×10 18 [cm -3 ] on both sides sandwiching the n-type region 11.
It consists of three regions, n + regions 12 and 13, implanted to the above concentration.
上記n+領域１３はドレイン領域であつて、そ
の表面にはｎ型GaAsとオーミツク接触を形成す
る金属からなるドレイン電極５が設けられる。こ
のドレイン電極５は例えば厚さ凡そ400〔Å〕の
AuGe合金層とその上に凡そ4000〔Å〕の厚さの
Au層を積層したものを用い得る。 The n + region 13 is a drain region, and a drain electrode 5 made of metal is provided on its surface to form ohmic contact with n-type GaAs. This drain electrode 5 has a thickness of approximately 400 [Å], for example.
An AuGe alloy layer with a thickness of approximately 4000 [Å] on top of it
A stack of Au layers can be used.
今一つのn+領域１２はソース領域であつて、
本発明においてはこのn+領域１２上には従来例
に見られるソース電極を省くことが出来る。即ち
本実施例は半絶縁性基板１背面の前記n+領域１
２に対応する位置に、n+領域１２に達する凹部
１４が設けられ、該凹部１４の底面１５及び内壁
面を含む半絶縁性基板１の背面上にAuGe合金層
（厚さ凡そ400〔Å〕）とAu層（厚さ凡そ4000
〔Å〕）が積層された蒸着層７とAuメツキ層８
（厚さ凡そ35〜50〔μｍ〕）が形成されてなる。 Another n + region 12 is a source region,
In the present invention, the source electrode seen in the conventional example can be omitted on this n + region 12. That is, in this embodiment, the n + region 1 on the back surface of the semi-insulating substrate 1
2, a recess 14 reaching the n + region 12 is provided, and an AuGe alloy layer (thickness approximately 400 [Å] ) and Au layer (approximately 4000 mm thick)
[Å]) evaporated layer 7 and Au plating layer 8
(thickness approximately 35 to 50 [μm]).
上記構造とすることにより本実施例は、凹部１
４の底面１５においてn+型GaAsが露呈され、ま
たAuGe合金はn+型GaAsとオーミツク接触を形
成する材料であるので、上記ｎ領域１２即ちソー
ス領域はその底部において背面電極９と直接接続
される。そして本実施例の装置においては動作時
にキヤリアは背面電極９より直接n+領域１２に
供給され、ゲート電極３の電位により制御されて
ドレイン電極１３に流入し、ドレイン電極５より
外部へ送出されるのであるが、n+領域１２は電
気抵抗が低いので従来例の如く表面に電極を設け
る必要がない。 With the above structure, this embodiment has a recess 1
Since n + type GaAs is exposed on the bottom surface 15 of 4, and the AuGe alloy is a material that forms ohmic contact with n + type GaAs, the n region 12, that is, the source region, is directly connected to the back electrode 9 at its bottom. Ru. In the device of this embodiment, during operation, the carrier is directly supplied to the n + region 12 from the back electrode 9, flows into the drain electrode 13 under the control of the potential of the gate electrode 3, and is sent out from the drain electrode 5. However, since the n + region 12 has a low electrical resistance, there is no need to provide an electrode on the surface as in the conventional example.
以上述べた如く本実施例はソース領域を高濃度
領域（n+領域１２）としたことにより、このn+
領域１２を背面電極９と直接接続すればよいこと
となり、この導電路形成のための基板背面からの
エツチングはn+領域１２に到達するまで行なえ
ばよく、従つて従来構造に見られた望ましくない
エツチングを生じることがない。従つて製造工定
が安定し、装置の製造歩留及び信頼度が向上す
る。 As described above, in this embodiment, by making the source region a high concentration region (n + region 12), this n +
It is now possible to connect the region 12 directly to the back electrode 9, and etching from the back surface of the substrate to form this conductive path can be carried out until reaching the n + region 12, which eliminates the undesirable problems seen in conventional structures. No etching occurs. Therefore, the manufacturing schedule is stabilized, and the manufacturing yield and reliability of the device are improved.
更に本実施例は能動層２表面にソース電極を設
ける必要がないため、ゲート電極のパターンの乱
れが発生せず、そのためゲート電極とソース電極
の間隔を任意に選択し得るという大きな利点を有
する。 Furthermore, this embodiment has the great advantage that, since it is not necessary to provide a source electrode on the surface of the active layer 2, the pattern of the gate electrode is not disturbed, and therefore the distance between the gate electrode and the source electrode can be arbitrarily selected.
即ちゲート電極はソース領域に出来るだけ近づ
けることが望ましいが、ソース電極が存在する場
合にはゲート電極をパターニングするためのホト
レジスト膜のゲート電極パターン近傍に段差を生
じ、この段差およびソース電極の段差における光
の乱反射によりゲート電極パターンの乱れが生じ
る。そのためゲート電極とソース電極との間を少
なくとも１〜２〔μｍ〕あける必要があつた。 In other words, it is desirable that the gate electrode be placed as close as possible to the source region, but if the source electrode is present, a step will occur near the gate electrode pattern of the photoresist film for patterning the gate electrode, and this step and the step of the source electrode will Diffuse reflection of light causes disturbances in the gate electrode pattern. Therefore, it was necessary to leave a gap of at least 1 to 2 [μm] between the gate electrode and the source electrode.
本実施例ではかかる問題も除去され、設計上で
はゲート電極の配設位置を任意に選択可能とな
り、製造工程上ではゲート電極のパターニング精
度が向上し、且つ作業が容易となる。そのため電
界効果トランジスタの電気的特性及び製造歩留が
向上する。 In this embodiment, this problem is also eliminated, the placement position of the gate electrode can be arbitrarily selected in the design, and the patterning accuracy of the gate electrode is improved in the manufacturing process, and the work is facilitated. Therefore, the electrical characteristics and manufacturing yield of the field effect transistor are improved.
なお上記一実施例においてはプレーナ構造を掲
げて説明したが、製作する装置が能動層をメサ状
とした構造であつても、またゲート電極形成部を
凹部としたリセス構造であつても、本発明を実施
し得る。 Although the above embodiment has been explained using a planar structure, this invention applies even if the device to be manufactured has a structure in which the active layer has a mesa shape or a recessed structure in which the gate electrode forming part is a concave part. The invention can be carried out.
また本発明はGaAs以外の半導体よりなる電界
効果トランジスタにおいても実施し得るものであ
る。 Furthermore, the present invention can also be implemented in field effect transistors made of semiconductors other than GaAs.
更に本発明を実施するための製造方法及び各部
の材料も特に限定される必要のないことは言うま
でもない。例えば高濃度領域１２に対するオーミ
ツク接触は、AuGe合金層に変えて例えばチタン
−白金−金（Ti−Pt−Au）層を形成することに
よつても得られる。また高濃度領域１２と背面電
極９とを直接接続する接続導体は、前記一実施例
の如く背面電極９と同一材料を用い同一工程で一
体化して形成するものが実用的であるが、この両
者は別個のものとしても差し支えない。 Furthermore, it goes without saying that there are no particular limitations on the manufacturing method and materials for each part for carrying out the present invention. For example, ohmic contact to the high concentration region 12 can also be obtained by forming, for example, a titanium-platinum-gold (Ti-Pt-Au) layer instead of the AuGe alloy layer. Furthermore, it is practical to form the connecting conductor that directly connects the high concentration region 12 and the back electrode 9 using the same material as the back electrode 9 in the same process as in the above-mentioned embodiment; may be separate items.
また前記一実施例ではソース電極を除去した例
を示したが、これらは何らかの理由によりソース
領域上にソース電極を設けることを妨げるもので
はない。例えば本発明を用いて製作する集積回路
装置等において、ソース領域と他の領域とを接続
するための電極を表面に設けても差支えない。 Further, although the above-mentioned embodiment shows an example in which the source electrode is removed, this does not prevent the source electrode from being provided on the source region for some reason. For example, in an integrated circuit device manufactured using the present invention, an electrode for connecting the source region and other regions may be provided on the surface.
以上説明した如く本発明によれば電界効果トラ
ンジスタの製作が容易となり製造歩留が向上と
し、しかも電気的特性及び信頼度が改善される。 As explained above, according to the present invention, it is easy to manufacture a field effect transistor, the manufacturing yield is improved, and the electrical characteristics and reliability are improved.
第１図は従来の電界効果トランジスタの説明に
供するための要部断面図、第２図は本発明の一実
施例を示す要部断面図である。
図において１は半絶縁性もしくは絶縁性基板、
２は能動層、３はゲート電極、９は背面電極、１
１は能動層のゲート直下部、１２は高濃度領域、
１４は凹部、１５は凹部底面を示す。
FIG. 1 is a sectional view of a main part for explaining a conventional field effect transistor, and FIG. 2 is a sectional view of a main part showing an embodiment of the present invention. In the figure, 1 is a semi-insulating or insulating substrate,
2 is an active layer, 3 is a gate electrode, 9 is a back electrode, 1
1 is directly below the gate of the active layer, 12 is a high concentration region,
Reference numeral 14 indicates a concave portion, and 15 indicates a bottom surface of the concave portion.
Claims (1)
一導電型を有する半導体よりなる能動層と、前記
能動層上に配設され前記能動層との間にシヨツト
キ接触を生ずるゲート電極と、前記能動層の前記
ゲート電極直下部を挟んで対向する区域に形成さ
れ前記ゲート電極直下部より不純物濃度が大なる
高濃度領域とを有する電界効果トランジスタにお
いて、 前記基板の背面から前記高濃度領域の一方の底
面まで達するが表面までは達しないように配設さ
れた接続導体により前記高濃度領域の一方と前記
基板の背面に配設された背面電極とが接続されて
なることを特徴とする電界効果トランジスタ。[Claims] 1. An active layer formed on the surface of an insulating or semi-insulating substrate and made of a semiconductor having one conductivity type, and an active layer disposed on the active layer that causes a spot contact with the active layer. In a field effect transistor having a gate electrode and a high concentration region formed in an area of the active layer opposite to each other with a region immediately below the gate electrode in between and having a higher impurity concentration than directly below the gate electrode, One of the high concentration regions is connected to a back electrode disposed on the back surface of the substrate by a connecting conductor arranged so as to reach the bottom of one of the high concentration regions but not to reach the surface. Characteristics of field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17875981A JPS5879773A (en) | 1981-11-06 | 1981-11-06 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17875981A JPS5879773A (en) | 1981-11-06 | 1981-11-06 | Field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5879773A JPS5879773A (en) | 1983-05-13 |
| JPS6236400B2 true JPS6236400B2 (en) | 1987-08-06 |
Family
ID=16054099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17875981A Granted JPS5879773A (en) | 1981-11-06 | 1981-11-06 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5879773A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60161651A (en) * | 1984-02-02 | 1985-08-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0797572B2 (en) * | 1985-07-08 | 1995-10-18 | 株式会社日立製作所 | Method for forming through hole in semiconductor integrated circuit board |
| US5236854A (en) * | 1989-12-11 | 1993-08-17 | Yukio Higaki | Compound semiconductor device and method for fabrication thereof |
| JPH06232180A (en) * | 1993-02-05 | 1994-08-19 | Nec Corp | Semiconductor device |
| US6611002B2 (en) * | 2001-02-23 | 2003-08-26 | Nitronex Corporation | Gallium nitride material devices and methods including backside vias |
| WO2008096521A1 (en) * | 2007-02-07 | 2008-08-14 | Nec Corporation | Semiconductor device |
| WO2009110254A1 (en) * | 2008-03-04 | 2009-09-11 | 日本電気株式会社 | Field effect transistor and method for manufacturing the same |
| US9960127B2 (en) | 2016-05-18 | 2018-05-01 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US10134658B2 (en) | 2016-08-10 | 2018-11-20 | Macom Technology Solutions Holdings, Inc. | High power transistors |
-
1981
- 1981-11-06 JP JP17875981A patent/JPS5879773A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5879773A (en) | 1983-05-13 |
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