JPH07273316A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent indium from diffusing to a second electrode layer and prevent a deterioration of morphology on a surface of the second electrode layer by a method wherein a high melting point metal layer of which a melting point is more than that of platinum is provided between a first metal layer and a second metal layer. CONSTITUTION:In an ohmic electrode structure to an n<+>-type InGaAs ohmic contact layer 17 being a III-V compound semiconductor layer, this is that a Pt layer 22 is inserted into a laminated structure of AuGe-NiAu. thereby, it is possible to prevent In in the n<+>-type InGaAs ohmic contact layer 17 from diffusing excessively to an electrode surface by an alloying heat treatment, and segregation of In of an electrode surface and unequalization of alloying can be reduced. Accordingly, the morphology of the electrode surface becomes excellent, and also as sheet resistance and contact resistance of the ohmic electrode are stabilized, it is possible to enhance element performance and reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an ohmic electrode structure, and in particular, an ohmic electrode is formed on a III-V group compound semiconductor containing indium (In) as a III group element in its composition. The present invention relates to a semiconductor device having the same. As a specific application thereof, for example, a high electron mobility field effect transistor (HEM) is used.
T), a millimeter wave monolithic IC (MMIC), and the like.

[0002]

2. Description of the Related Art Conventionally, indium (I
The method for forming the ohmic electrode on the compound semiconductor layer of the III-V group or the III-V group mixed crystal containing n) includes AuGe-Ni-Au and AuGe-A as the ohmic electrode material.
using a three-layer or two-layer structure of u or AuGe-Ni,
Alloying heat treatment is performed after the ohmic electrode deposition. (Here, the compound semiconductor of the III-V group mixed crystal is
A group III portion is a compound having two or more elements such as InGaAs and InAlAs. For example, InGaAs is In
It is a mixed crystal of two III-V group compound semiconductors of As and GaAs. ) Regarding a method of forming an ohmic electrode on an InGaAs n-type semiconductor layer, see, for example, Japanese Patent Laid-Open No. 62-194.
As disclosed in Japanese Patent Publication No. 671), there is a method in which AuGe-Ni is used as an ohmic electrode material, and the film thickness of each film is in the range of 300Å to 900Å and 100Å to 225Å, and an alloying heat treatment is performed after the electrode material is deposited. is there.

[0003]

However, in the method disclosed in the above publication, although an ohmic junction is obtained, the alloying heat treatment causes indium (In) in the InGaAs n-type semiconductor layer to diffuse to the outermost surface of the ohmic electrode and segregate. There are problems that the morphology of the surface (roughness of the surface) is deteriorated and the variation of the sheet resistance is increased.

Regarding the deterioration of the morphology of the electrode surface due to the segregation of indium (In), when the upper layer wiring or the bonding pad of gold (Au) is formed on the ohmic electrode by, for example, the electron beam evaporation method or the plating method, the indium (In) If a metal having a low melting point such as In) exists between the ohmic electrode and the bonding pad, there is a problem that reliability is deteriorated due to peeling of the upper wiring or the bonding pad.

The present invention has been made in view of the above problems. An object of the present invention is to provide an ohmic electrode structure for a III-V group compound semiconductor layer containing indium (In) as a III group element. 2) to prevent the deterioration of the morphology of the electrode surface and to obtain an ohmic electrode structure with a stable sheet resistance, and secondly to prevent the upper layer wiring, the bonding pad and the like from peeling off.

[0006]

According to another aspect of the present invention, there is provided a semiconductor device, which is formed on a semiconductor substrate and contains indium (In) as a group III element.
And a first metal layer which is formed on the compound semiconductor layer and has an ohmic junction between the compound semiconductor layer and a compound semiconductor layer of the group III-V containing in the composition, and formed on the first metal layer. And a second metal layer made of a low-resistance metal, the first metal layer and the second metal layer
And a high melting point metal layer having a melting point not lower than that of platinum (Pt).

According to another aspect of the present invention, there is provided a semiconductor device having a channel layer formed on a semiconductor substrate for allowing majority carriers to travel, and electrons formed on the channel layer. A dope layer to be supplied, a gate contact layer formed on the doped layer, an ohmic contact layer containing In in the composition formed on a part of the gate contact layer, and a part on the ohmic contact layer. A semiconductor device having an ohmic electrode formed and forming an ohmic contact with the ohmic contact layer, and a gate electrode formed on a portion of the gate contact layer and forming a Schottky contact with the gate contact layer. The ohmic electrode has a first metal layer, a refractory metal layer, and a second electrode layer. A layer is formed on the ohmic contact layer and makes ohmic contact with the ohmic contact layer, and the refractory metal layer is formed on the first metal layer and has a melting point equal to or higher than the melting point of platinum (Pt). The second metal layer is formed on the refractory metal layer and is made of a metal having a low resistance.

According to another aspect of the present invention, there is provided a semiconductor device having a channel layer formed on a semiconductor substrate for allowing majority carriers to travel, and electrons formed on the channel layer. A dope layer to be supplied, a gate contact layer formed on the doped layer, an ohmic contact layer containing In in the composition formed on a part of the gate contact layer, and a part on the ohmic contact layer. Two ohmic electrodes formed and forming an ohmic contact with the ohmic contact layer,
A lower layer electrode electrically connected to the semiconductor substrate, the channel layer, the doped layer, the gate contact layer, the ohmic contact layer, and the ohmic electrode; an upper electrode formed on the lower layer electrode; In a semiconductor device having a gate electrode formed on a part of a gate contact layer and forming a Schottky junction with the gate contact layer, the ohmic electrode and the lower electrode are formed between the ohmic contact layer and the ohmic contact layer. A first metal layer that makes ohmic contact, a high-melting point metal layer formed on the first metal layer and having a melting point equal to or higher than the melting point of platinum (Pt), and formed on the high-melting point metal layer to have a low resistance. And a second metal layer made of the above metal.

In the semiconductor device according to any one of claims 1 to 3, the first metal layer is germanium gold (A).
uGe) and the second metal layer may include gold (Au). The melting point of the high melting point metal layer is preferably 1769 ° C. or higher. The structure may have a platinum (Pt) layer, a molybdenum (Mo) layer, or a tungsten (W) layer.

The III-V group compound semiconductor in the present invention is a III-compound composed of two elements such as InP.
Not only Group V compound semiconductors but also, for example, In _X Ga _1-X A
s, In _Y Al _1-Y As (where 0 <X <1, 0 <Y <
It also includes a so-called III-V mixed crystal compound semiconductor composed of three or four or more elements such as 1).

[0011]

According to the first and second aspects of the invention, the indium diffuses from the III-V group compound semiconductor layer side containing indium (In) into the first metal layer side during the manufacturing process. The refractory metal layer having a melting point equal to or higher than that of platinum (Pt) blocks (In). As a result, the refractory metal layer prevents indium (In) from diffusing into the second electrode layer and prevents the morphology of the surface of the second electrode layer from deteriorating. Then, an ohmic electrode structure with stable sheet resistance is obtained.

According to the third invention having the above-mentioned structure, at the time of manufacturing,
A refractory metal whose melting point is equal to or higher than that of platinum (Pt) for indium (In) that passes through and diffuses from the III-V group compound semiconductor layer side containing indium (In) to the first metal layer side. The layer dams. As a result, the refractory metal layer prevents indium (In) from diffusing into the second electrode layer and prevents the morphology of the surface of the second electrode layer from deteriorating. As a result, an ohmic electrode structure with a stable sheet resistance is obtained and peeling of the upper layer wiring and bonding pad is prevented.

[0013]

According to the first and second aspects of the present invention, the refractory metal layer prevents indium (In) from diffusing into the second electrode layer and deteriorates the morphology of the surface of the second electrode layer. Since this can be prevented, an ohmic electrode structure with a stable sheet resistance can be obtained. According to the third aspect of the present invention, the refractory metal layer can prevent indium (In) from diffusing into the second electrode layer, and can prevent deterioration of the morphology of the surface of the second electrode layer. It is possible to obtain a stable ohmic electrode structure and prevent peeling of the upper wiring and the bonding pad.

[0014]

【Example】

(First Embodiment) The first embodiment specifically describes a case where the present invention is applied to a high electron mobility field effect transistor (hereinafter, HEMT). FIG. 1 is a sectional view showing a structure according to an embodiment of the present invention, and FIG. 2 is a sectional view when it is applied to an electrode of a HEMT.

First, in FIG. 2, an i-type InGaAs channel layer 13 having a thickness of 200Å is formed on an InP substrate 11 via an i-type InAlAs buffer layer 12 having a thickness of 1000Å. Further, on the i-type InGaAs channel layer 13, an n ⁺ -type InAlAs doped layer 15 having a thickness of 150 Å is formed via an i-type InAlAs spacer layer 14 having a thickness of 50 Å. Furthermore, this n ⁺ type InA
A 100 Å thick i-type InAl layer is formed on the lAs-doped layer 15.
N with a thickness of 100Å through the As gate contact layer 16
^{A +} type InGaAs ohmic contact layer 17 is formed.

Here, in this embodiment, the InP substrate 1 is used.
1, i-type InAlAs buffer layer 12, i-type InGaA
s channel layer 13, i-type InAlAs spacer layer 14,
The n ⁺ type InAlAs doped layer 15 and the i type InAlAs gate contact layer 16 correspond to the semiconductor substrate, and the n ⁺ type I
The nGaAs ohmic contact layer 17 corresponds to a III-V group compound semiconductor layer.

An ohmic electrode 18 is deposited on the n ⁺ type InGaAs ohmic contact layer 17 by, for example, an electron beam evaporation method. This ohmic electrode is, as shown in FIG. 1, an n ⁺ type InGaAs ohmic contact layer 1
The AuGe layer 20 is 600 Å, the Ni layer 21 is 200 Å, the Pt layer 22 is 700 Å, and the Au layer 23 is 100
0 Å It is composed by wearing. Then, for example, 36
An alloying heat treatment is performed at 0 ° C. for 2 minutes to obtain an ohmic junction. Further, after recess etching the n ⁺ type InGaAs ohmic contact layer 17, the gate electrodes 19 having a thickness of 1000 Å, 500 Å and 3000 Å of Ti-Pt-Au are formed on the i-type InAlAs gate contact layer 16 by electron beam evaporation, for example. Put on.

According to the present embodiment thus constructed,
N ⁺ type InGaA which is a III-V group compound semiconductor layer
In the ohmic electrode structure for the s ohmic contact layer 17, the Pt layer 2 is formed in the layered structure of AuGe—Ni—Au.
With the ohmic electrode structure in which 2 is inserted, In in the n ⁺ type InGaAs ohmic contact layer 17 can be prevented from excessively diffusing to the electrode surface by the alloying heat treatment, and segregation and alloying of In on the electrode surface can be prevented. Non-uniformity can be reduced. Therefore, the morphology of the electrode surface is improved, and the sheet resistance and contact resistance of the ohmic electrode are stabilized, so that the device performance and reliability can be improved.

The thickness of the Pt layer 22 is 300Å-10.
00Å is desirable. The refractory metal layer is not limited to the Pt layer, but may be any layer as long as it has a melting point higher than that of Pt (1769 ° C.). For example, in addition to this, a Mo layer, a W layer, or the like may be used,
Further, the structure may be a single layer film or a multilayer film. (Second Embodiment) The second embodiment specifically describes a case where the present invention is applied to a millimeter wave monolithic IC (hereinafter, MMIC) using HEMT as a wiring. FIG. 3 is a partial sectional view of an MMIC using a HEMT according to an embodiment of the present invention.

The substrate having the film structure used in the first embodiment is separated by elements by mesa etching. After that, n ⁺ type I
On the nGaAs ohmic contact layer 17, the mesa side wall and the InP substrate 11, for example, by an electron beam evaporation method,
Ohmic electrode 18 and lower layer wiring 24 (corresponding to lower layer electrode)
As AuGe-Ni-Pt-Au with a film thickness of 60
0Å, 200Å, 700Å, 1000Å After that, for example, an alloying heat treatment is performed at 360 ° C. for 2 minutes to obtain an ohmic junction. Further, after the gate electrode 19 is formed, the Au film having a film thickness of 2 μm (20,000 Å) is formed by, for example, a plating method.
Are formed as the upper layer wiring 25 (corresponding to the upper layer electrode).

By using the ohmic electrode as the lower layer wiring 24, the number of steps can be reduced and the adhesion between the lower layer wiring 24 and the InP substrate 11 can be improved. Further, according to this embodiment, an n ⁺ type I which is a III-V group compound semiconductor layer is used.
In the ohmic electrode structure to nGaAs the ohmic contact layer 17, AuGe-Ni-Au laminated structure of by the ohmic electrode structure of inserting the Pt layer 22, an In in the n ⁺ -type InGaAs ohmic contact layer 17 by alloying heat treatment Can be prevented from excessively diffusing to the electrode surface, and segregation of In on the electrode surface and non-uniform alloying can be reduced. Therefore, the morphology of the electrode surface becomes good, and the sheet resistance and contact resistance of the ohmic electrode become stable, so that the performance and reliability of the MMIC can be improved. In addition, segregation of In on the surface is prevented by the effect of the Pt layer 22, and a lower layer wiring that is thermally stable and has a good surface morphology can be obtained. Therefore, peeling from the lower layer wiring 24 of the upper layer wiring 25 can be prevented. it can.

By applying the present invention to an alignment mark used for electron beam exposure when forming a gate electrode, the productivity of forming the gate electrode can be improved. This procedure will be briefly described below. First, AuG was formed on the mesa-etched InP substrate used in the second embodiment.
e20-Ni21-Pt22-Au23 is applied to each film thickness of 600Å, 200Å, 700Å, 1000Å to form an alignment mark. After that, it is exposed to heat of 360 ° C. in the step of alloying heat treatment of the ohmic electrode. However, according to the present invention, the morphology of the alignment mark surface is good due to the effect of the Pt layer 22,
Positioning accuracy during electron beam exposure is improved. In this case, it can be applied to an alignment mark used for electron beam exposure or an alignment mark used for a projection exposure method.

Further, in the first and second embodiments, the single layer film of the Pt layer 22 is used as the third layer of the ohmic electrode 18, but instead of this, a single layer film of Mo or W or M is used.
You may use the multilayer film containing o, W, and Pt. Furthermore, in the first and second embodiments, HEMT and M using HEMT are used.
Although the explanation has been given by taking MIC as an example, In
It can also be applied to a diode, a Hall element, or the like using an III-V group n-type compound semiconductor containing

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view when the present invention is applied to HEMT.

FIG. 3 is a partial sectional view of an MMIC according to a second embodiment of the present invention.

[Explanation of symbols]

11 SI type InP substrate 12 i type InAlAs buffer layer 13 i type InGaAs channel layer 14 i type InAlAs spacer layer 15 n ⁺ type InAlAs doped layer 16 i type InAlAs gate contact layer 17 n ⁺ type InGaAs ohmic contact layer 18 ohmic electrode 19 gate Electrode 20 AuGe layer 21 Ni layer 22 Pt layer 23 Au layer 24 Lower layer wiring 25 Upper layer wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/43 H01L 29/46 G

Claims (8)

[Claims] 1. Between a compound semiconductor layer of a III-V group formed on a semiconductor substrate and containing indium (In) as a group III element in a composition, and the compound semiconductor layer formed on the compound semiconductor layer. In a semiconductor device having a first metal layer that makes ohmic contact with the first metal layer and a second metal layer that is formed on the first metal layer and is made of a low-resistance metal. A semiconductor device comprising a refractory metal layer having a melting point not lower than that of platinum (Pt) between the metal layer and the metal layer. 2. A channel layer formed on a semiconductor substrate for allowing majority carriers to travel, a doped layer for supplying electrons formed on the channel layer, and a gate contact layer formed on the doped layer. An ohmic contact layer containing In in a composition formed on a part of the gate contact layer; an ohmic electrode formed on a part of the ohmic contact layer and forming an ohmic contact with the ohmic contact layer; In a semiconductor device having a gate electrode formed on a part of a gate contact layer and forming a Schottky junction with the gate contact layer, the ohmic electrode includes a first metal layer, a refractory metal layer, and a second metal layer. And a first metal layer formed on the ohmic contact layer to form the ohmic contact layer. Ohmic junction is formed between the tact layer, the refractory metal layer is formed on the first metal layer,
A metal layer having a melting point equal to or higher than that of platinum (Pt), the second metal layer is formed on the refractory metal layer,
A semiconductor device comprising a low-resistance metal. 3. A channel layer formed on a semiconductor substrate for allowing majority carriers to travel, a doped layer for supplying electrons formed on the channel layer, and a gate contact layer formed on the doped layer. An ohmic contact layer containing In in a composition formed on a part of the gate contact layer; an ohmic electrode formed on a part of the ohmic contact layer and forming an ohmic contact with the ohmic contact layer; A semiconductor substrate, the channel layer, the doped layer, the gate contact layer, the ohmic contact layer, and a lower layer electrode electrically connected to the ohmic electrode, an upper electrode formed on the lower layer electrode, and the gate It is formed on a part of the contact layer and has a Schottky contact with the gate contact layer. In the semiconductor device having a gate electrode, the ohmic electrode and the lower electrode are formed on the first metal layer that makes an ohmic contact with the ohmic contact layer, and have a melting point. A semiconductor device comprising: a high melting point metal layer having a melting point of platinum (Pt) or higher; and a second metal layer formed on the high melting point metal layer and made of a low resistance metal. 4. The germanium gold (A) is used as the first metal layer.
4. The semiconductor device according to claim 1, further comprising uGe), and the second metal layer includes gold (Au). 5. The melting point of the refractory metal layer is 1769 ° C.
It is above, The semiconductor device of Claim 1 thru | or 4 characterized by the above-mentioned. 6. The semiconductor device according to claim 1, wherein the refractory metal layer includes a platinum (Pt) layer. 7. The refractory metal layer is molybdenum (M).
7. The semiconductor device according to claim 1, which has a layer of o). 8. The semiconductor device according to claim 1, wherein the refractory metal layer includes a tungsten (W) layer.