JPH0345537B2 - - Google Patents
Info
- Publication number
- JPH0345537B2 JPH0345537B2 JP57059578A JP5957882A JPH0345537B2 JP H0345537 B2 JPH0345537 B2 JP H0345537B2 JP 57059578 A JP57059578 A JP 57059578A JP 5957882 A JP5957882 A JP 5957882A JP H0345537 B2 JPH0345537 B2 JP H0345537B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- tin layer
- opening
- gaas
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 23
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000007733 ion plating Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000010931 gold Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 229910017401 Au—Ge Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
半導体装置の製造方法に係り、特に表面安定化
と活性領域の不純物濃度の制御の改良をはかるも
のである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to improving surface stabilization and control of impurity concentration in an active region.
半導体のうち、GaAsはSiに比して電子の移動
度が５〜６倍大きいため、ポストシリコンの超高
速ロジツクや通信用超高速周波IC（集積回路）と
しての研究開発が進められている。GaAsは常
圧、500℃の温度でAsが蒸発することからも表面
が非常に不安定である。GaAsICを作るには、表
面不安定性の制御、および、単結晶自体の無転位
化を含む高品質化、不純物濃度層の厳密な制御の
確立が要求されている。
Among semiconductors, GaAs has 5 to 6 times higher electron mobility than Si, so research and development is underway for use in post-silicon ultra-high-speed logic and ultra-high-speed frequency ICs (integrated circuits) for communications. The surface of GaAs is extremely unstable, as As evaporates at normal pressure and at a temperature of 500°C. To make GaAsICs, it is necessary to control surface instability, improve quality including dislocation-free single crystals, and establish strict control of impurity concentration layers.
特にGaAsの場合には安定な酸化膜をもたない
ので、GaAsFETにおいてGaAs基板とゲートが
直接接続されている。 In particular, GaAs does not have a stable oxide film, so the GaAs substrate and gate are directly connected in GaAs FETs.
叙上の例えばGaAsFETにおいてはゲート材料
としてAlを用いた場合、GaAsと反応してしま
う。また、AuあるいはAu化合物を用いても400
℃程度で反応を生じてゲートとしての役割を果さ
なくなる。次にゲート材としてTiW合金を用い
たものがあり、上記AlやAuなどに比して大幅に
改善されるが、ゲート電極層をイオンマイクロア
ナリシス（IMA）で分析した結果を示す第１図
に明らかなように、Asが４〜８％、Gaが１〜３
％検出されている。これはTiWとGaAs基板との
反応によるもので、界面に形成される表面準位の
ため再現性良く期待されたゲート特性を得ること
ができない欠点がある。
For example, in the GaAsFET mentioned above, if Al is used as the gate material, it will react with GaAs. In addition, even if Au or Au compounds are used, 400
A reaction occurs at temperatures around ℃ and it no longer functions as a gate. Next, there is a method using TiW alloy as the gate material, which is significantly improved compared to the above-mentioned Al and Au. As is clear, As is 4-8% and Ga is 1-3%.
% detected. This is due to the reaction between TiW and the GaAs substrate, and has the drawback that the expected gate characteristics cannot be obtained with good reproducibility due to surface states formed at the interface.
背景技術の問題点を満足するための半導体装置
の製造方法を提供する。
A method for manufacturing a semiconductor device that satisfies the problems of the background art is provided.
この発明に係る半導体装置の製造方法は、
GaAs半導体基板にCVD法、スパツタリング法、
イオンプレーテイング法のいずれかによりGaお
よびAsを遮断するTiN層を被着する工程と、前
記TiN層に金属層を積層し被着する工程と、ソ
ース、ゲートおよびドレイン領域形成予定域の前
記金属層に開孔を設ける工程と、前記開孔から前
記TiN層を介して基板に不純物をイオン注入し
たのちこの開孔にTiN層と金属層を積層し被着
する工程と、ソース、およびゲート領域形成予定
域の前記金属層に開孔を設ける工程と、前記開孔
から前記TiN層を介して基板に不純物をイオン
注入する工程と、熱処理を施したのちソース、お
よびドレイン電極形成予定域のTiN層に開孔を
設けソース、およびドレイン電極を、またゲート
領域上にゲート電極を夫々形成する工程を備えた
ものである。
The method for manufacturing a semiconductor device according to the present invention includes:
CVD method, sputtering method,
A step of depositing a TiN layer that blocks Ga and As by any of the ion plating methods, a step of laminating and depositing a metal layer on the TiN layer, and a step of depositing the metal layer in the area where the source, gate and drain regions are planned to be formed. a step of forming an opening in the layer, a step of ion-implanting an impurity into the substrate from the opening through the TiN layer, and then laminating and depositing a TiN layer and a metal layer in the opening, and a source and gate region. A step of forming an opening in the metal layer in the region where the metal layer is planned to be formed, a step of ion-implanting an impurity into the substrate from the hole through the TiN layer, and a step of performing heat treatment on the TiN layer in the region where the source and drain electrodes are planned to be formed. This method includes the steps of forming an opening in the layer to form source and drain electrodes, and forming a gate electrode on the gate region.
まず、GaAs単結晶基板にCVD法、スパツタリ
ング法、イオンプレーテイング法のいずれかで
TiNを3000Åの層厚に被着したのちに、H2雰囲
気中、または不活性ガス雰囲気中にて840℃、30
分間熱処理したときのTiN層中のAsおよびGaの
分布を第３図に示す。これによつても、GaAs基
板からのAs、Gaの拡散はIMAの検出限界内で完
全に遮断されていることが明らかである。この遮
断効果はTiWに比して103〜104倍大きいものであ
り、GaAs基板との反応性が小さいためにGaAs
を被覆した場合、GaAs基板の表面の安定化が達
成される。
First, a GaAs single crystal substrate is coated with either the CVD method, sputtering method, or ion plating method.
After depositing TiN to a layer thickness of 3000 Å, it was heated at 840℃ for 30 minutes in an H 2 atmosphere or an inert gas atmosphere.
Figure 3 shows the distribution of As and Ga in the TiN layer after heat treatment for 1 minute. It is clear from this as well that the diffusion of As and Ga from the GaAs substrate is completely blocked within the detection limit of IMA. This blocking effect is 10 3 to 10 4 times greater than that of TiW, and GaAs has a lower reactivity with the GaAs substrate.
When coated with , stabilization of the surface of the GaAs substrate is achieved.
次に第２図ａ〜ｅによつてGaAsFETの製造を
説明する。まず、CrがドープされたGaAs単結晶
基板１にGaAs（エピタキシヤル）層２を形成し、
さらに、CVD法、スパツタリング法、イオンプ
レーテイング法のいずれかでTiN層３を被着し、
Ptまたはその化合物のうち少なくとも１層の金
属層（４第２図では単相で示す）を積層して被着
する。このTiN層上に被着する金属層は前記
TiN層の層厚やFETの特性の設計によつて選定
してよい。一般にワイヤボンデイングにAuワイ
ヤを用いるときにAuまたはAu化合物を多層電極
の最外殻層に選択して用いる場合が多い。次に、
TiN層を含めた前記金属積層層に蝕刻を施して
ソース、ゲート、ドレインの各領域に開孔部を形
成し、この開孔部を通してイオン注入を施し、第
１のシリコン導入層５を形成する（第２図ａ）。
なお、TiN層に対する蝕刻は、このTiN層が例
えば特に厚い場合、被着直後に施し開孔を設けて
おいてもよい。 Next, the manufacturing of GaAsFET will be explained with reference to FIGS. 2a to 2e. First, a GaAs (epitaxial) layer 2 is formed on a GaAs single crystal substrate 1 doped with Cr.
Furthermore, a TiN layer 3 is deposited by either CVD method, sputtering method, or ion plating method,
At least one metal layer (4 shown as a single phase in FIG. 2) of Pt or its compound is laminated and deposited. The metal layer deposited on this TiN layer is
It may be selected depending on the thickness of the TiN layer and the design of FET characteristics. Generally, when using Au wire for wire bonding, Au or an Au compound is often selected and used as the outermost shell layer of a multilayer electrode. next,
The metal laminated layer including the TiN layer is etched to form openings in the source, gate, and drain regions, and ions are implanted through the openings to form the first silicon-implanted layer 5. (Figure 2a).
Note that, if the TiN layer is particularly thick, for example, the TiN layer may be etched immediately after it is deposited to form holes.
ついで、前記開孔部をTiN層１３とこれに積
層して金層１４を被着し、ソースおよびドレイン
の各領域に開孔を設け、この開孔よりイオン注入
法で第２のシリコン導入層１５を形成する（第２
図ｂ）。 Next, a TiN layer 13 is laminated to the opening, and a gold layer 14 is deposited thereon, and an opening is formed in each source and drain region, and a second silicon-introduced layer is formed through the opening by ion implantation. 15 (second
Figure b).
ついで上記シリコン導入層５，１５のシリコン
イオンを活性化させるために、800℃にて20分間
の熱処理を施すことによつて第２図ｃに示すよう
にGaAsFETのソース・ドレインプレーナ構造が
形成される。 Next, in order to activate the silicon ions in the silicon-introduced layers 5 and 15, a heat treatment is performed at 800° C. for 20 minutes to form a GaAsFET source/drain planar structure as shown in FIG. 2c. Ru.
次に、電極形成を施して第２図ｄに示す形状に
する。なお、この図中に示される２４ｓ，２４
ｄ，２４ｇは電極導出のためのソース、ドレイ
ン、ゲートの各電極を導出するためのいずれも電
極金属層である。また、６ｓはソース電極部、６
ｄはドレイン電極部のいずれも一例のAu−Ge合
金層である。 Next, electrode formation is performed to form the shape shown in FIG. 2d. In addition, 24s, 24 shown in this figure
d and 24g are electrode metal layers for leading out the source, drain, and gate electrodes. Moreover, 6s is a source electrode part, 6s
d is an example of an Au-Ge alloy layer in the drain electrode portion.
次に、上記電極金属層に一例としてAuの電極
３４ｓ，３４ｄ，３４ｇを夫々取着け、各電極間
を電気絶縁膜７で被覆しシヨツトキー型の
GaAsFETが得られる（第２図ｅ）。 Next, as an example, Au electrodes 34s, 34d, and 34g are attached to the electrode metal layer, and the space between each electrode is covered with an electrical insulating film 7 to form a Schottky type.
A GaAsFET is obtained (Fig. 2e).
従来法ではイオン注入法で導入したシリコンを
活性化する際、Asを加えた不活性気体雰囲気に
て熱処理を施していたが、この発明によればAs
圧を加える必要がないので、安全衛生の面で極め
て有利な方法である。
In the conventional method, when activating silicon introduced by ion implantation, heat treatment was performed in an inert gas atmosphere containing As, but with this invention, As
Since there is no need to apply pressure, this method is extremely advantageous in terms of safety and health.
次に、GaAsFETを製造する場合、Alゲートで
は約500μA、TiW合金では約800μA程度しか電流
を流すことができなかつた。この発明の方法によ
れば約1.2ｍＡ流すことができ、従来比1.5〜2.5倍
に改良された。またスイツチング速度もゲート
1.4μｍの場合に50psecで、従来比1.4〜2.5倍に改
良された。 Next, when manufacturing GaAsFETs, the current could only flow around 500 μA with an Al gate and around 800 μA with a TiW alloy. According to the method of this invention, it is possible to flow approximately 1.2 mA, which is an improvement of 1.5 to 2.5 times compared to the conventional method. The switching speed is also gated.
In the case of 1.4 μm, it was 50 psec, an improvement of 1.4 to 2.5 times compared to the conventional method.
叙上はTiN電極内のAsまたはGaの分布をIMA
によつて測定した結果を示す第３図に見られるよ
うに、従来に比し顕著に少ないことからも理解で
きる。 The above describes the IMA distribution of As or Ga in the TiN electrode.
As can be seen in FIG. 3, which shows the results measured by the method, this can be understood from the fact that the number of cases is significantly lower than that of the conventional method.
なお、この発明はGaAsに限らずシリコン基板
を用いた場合、シリコン原子に対するブロツク効
果がTiW合金、MoSi2等の金属化合物よりもす
ぐれている。従つてMOSFETについても
GaAsFETと同様の効果があることはいうまでも
ない。 The present invention is not limited to GaAs, and when a silicon substrate is used, the blocking effect on silicon atoms is superior to that of TiW alloys, MoSi2 , and other metal compounds. Therefore, regarding MOSFET as well
Needless to say, it has the same effect as GaAsFET.
第１図は従来のGaAs素子におけるTiW電極内
のAs、Gaの分布を示す線図、第２図ａ〜ｅはこ
の発明の１実施例のシヨツトキー型GaAsFETの
製造方法を工程順に説明するためのいずれも断面
図、第３図は１実施例のTiN電極内のAs、Gaの
分布を示す線図である。
１……GaAs単結晶基板、２……GaAs（エピタ
キシヤル）層、３……TiN層、４，１４ｓ，１
４ｄ，１４ｇ……電極金属層、５……第１のシリ
コン導入層、１５……第２のシリコン導入層、１
６ｓ，１６ｄ……Au−Ge合金層、３４ｓ，３４
ｄ，３４ｇ……電極。
Fig. 1 is a diagram showing the distribution of As and Ga in the TiW electrode in a conventional GaAs device, and Figs. Both are cross-sectional views, and FIG. 3 is a diagram showing the distribution of As and Ga in the TiN electrode of one embodiment. 1...GaAs single crystal substrate, 2...GaAs (epitaxial) layer, 3...TiN layer, 4, 14s, 1
4d, 14g... Electrode metal layer, 5... First silicon introduced layer, 15... Second silicon introduced layer, 1
6s, 16d...Au-Ge alloy layer, 34s, 34
d, 34g...electrode.
Claims (1)
法、イオンプレーテイング法のいずれかにより
GaおよびAsを遮断するTiN層を被着する工程
と、前記TiN層に金属層を積層し被着する工程
と、ソース、ゲートおよびドレイン領域形成予定
域の前記金属層に開孔を設ける工程と、前記開孔
から前記TiN層を介して基板に不純物をイオン
注入したのちこの開孔にTiN層と金属層を積層
し被着する工程と、ソース、およびドレイン領域
形成予定域の前記金属層に開孔を設ける工程と、
前記開孔から前記TiN層を介して基板に不純物
をイオン注入する工程と、熱処理を施したのちソ
ース、およびドレイン電極形成予定域のTiN層
に開孔を設けソース、およびドレイン電極を、ま
たゲート領域上にゲート電極を夫々形成する工程
を備えた半導体装置の製造方法。1 GaAs semiconductor substrate by CVD method, sputtering method, or ion plating method
A step of depositing a TiN layer that blocks Ga and As, a step of laminating and depositing a metal layer on the TiN layer, and a step of providing an opening in the metal layer in the area where the source, gate and drain regions are planned to be formed. , a step of ion-implanting impurities into the substrate through the TiN layer through the opening, and then laminating and depositing a TiN layer and a metal layer in the opening; a step of providing an opening;
After performing ion implantation of impurities into the substrate through the TiN layer through the opening and heat treatment, openings are formed in the TiN layer in the areas where the source and drain electrodes are to be formed, and the source and drain electrodes are formed. A method for manufacturing a semiconductor device, comprising the step of forming gate electrodes on respective regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5957882A JPS58176973A (en) | 1982-04-12 | 1982-04-12 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5957882A JPS58176973A (en) | 1982-04-12 | 1982-04-12 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58176973A JPS58176973A (en) | 1983-10-17 |
| JPH0345537B2 true JPH0345537B2 (en) | 1991-07-11 |
Family
ID=13117247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5957882A Granted JPS58176973A (en) | 1982-04-12 | 1982-04-12 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176973A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH039566A (en) * | 1989-06-07 | 1991-01-17 | Toshiba Corp | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5154367A (en) * | 1974-11-07 | 1976-05-13 | Nippon Electric Co | CHITANSANBISUMASUNIMOKERUDENKYOKU |
| JPS5267277A (en) * | 1975-12-01 | 1977-06-03 | Fujitsu Ltd | Mis field effect transistor |
| JPS5310283A (en) * | 1976-07-15 | 1978-01-30 | Matsushita Electric Ind Co Ltd | 54)mos type semiconductor integrated circuit |
-
1982
- 1982-04-12 JP JP5957882A patent/JPS58176973A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5154367A (en) * | 1974-11-07 | 1976-05-13 | Nippon Electric Co | CHITANSANBISUMASUNIMOKERUDENKYOKU |
| JPS5267277A (en) * | 1975-12-01 | 1977-06-03 | Fujitsu Ltd | Mis field effect transistor |
| JPS5310283A (en) * | 1976-07-15 | 1978-01-30 | Matsushita Electric Ind Co Ltd | 54)mos type semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58176973A (en) | 1983-10-17 |
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