JPS6050967A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the series resistance of sources and to shorten the manufacturing steps of a high frequency Schottky barrier gate type FET by forming source, drain and gate electrodes in a self-alignment and using the same material for the metal for the electrode. CONSTITUTION:Si<+> ion implanted layer 12' is formed on the surface layer of a semi-insulating GaAs substrate 11, and a Ge layer 18 and an SiO2 film 19 are laminated and covered thereon. Then, a photoresist film 10 having a hole 10a is formed on the film 19, a hole 19a perpendicular to the film 19 is opened by reactive ion etching, and an overetched hole 18a is opened by plasma etching at the layer 18. Subsequently, the film 10 is altered to the film 10 for blocking the hole, the exposed portion of the film 19 is removed by etching, As<+> ions are implanted to the layer 12' to activate it, and an operation layer 12 is formed in the layer 12'. Then, a source electrode 6, a drain electrode 17 and a gate electrode 15 made of a Ti layer 21 and an aluminum layer 22 are attached on the layer 18 and the layer 12 interposed therebetween.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to field effect transistors, and particularly to a method for manufacturing a Schottky barrier gate type field effect transistor suitable for high frequency operation.

[Technical background of the invention and its problems]

Research and development of gallium arsenide (GaAp) semiconductors has been rapidly progressing in recent years because they have superior high speed performance compared to silicon semiconductor devices. In particular, GuAs Schottky barrier gate field effect transistor (GaA@MES)
FET) is being put into practical use as a microwave device, and is one of the most important devices as a main component of GaAs IC.

In order to improve the performance of the GaAs MES FET, it is necessary to reduce parasitic resistance and capacitance as much as possible.

In particular, it is important to keep the channel series resistance between the source and gate electrodes low.

However, in a conventional GaAs R4ES FET, for example, as shown in FIG. ) and n+ in the drain region
An injection layer (4) is provided on the n-type semiconductor layer (2), and a gate electrode (5) is provided on the n-type semiconductor layer (2) sandwiched between the peripheral regions. 6), a drain electrode (7) is provided.In the diagonal structure, it is necessary to allow for errors for mask alignment in each photoetching process, and due to the limitations of photoetching technology, there is a gap between the source and gate. Therefore, as mentioned above, the n-type active layer (2
) to reduce the series resistance of the IC, and even if the gate length is made submicron, the performance will not improve as expected.

Furthermore, gold-germanium (Au-Ge) alloy-based electrodes are usually used for the source electrode (C3) and drain electrode (7), but this 1! The formation of poles is always called alloy,
This requires an alloying process between the electrode metal and the QaAs crystal. This MIDS FE
This has been one of the hindrances to the formation of integrated circuits (ICs) that use a number of T's.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks and aims to provide a novel method for manufacturing a Schottky barrier gate field effect transistor. According to this invention, the source, drain, and gate electrodes can be formed by self-alignment, and the source series resistance can also be reduced.

The same metal can be used for the electrode metal and the source and drain electrode electrodes, and they can be formed at the same time. ! ! The sewing process is greatly shortened.

[Summary of the invention]

The method for manufacturing a field effect transistor of the present invention includes the steps of forming an active layer on the main surface of a high resistivity semiconductor substrate, depositing a germanium thin film on the surface of the active layer, and laminating the germanium thin film. forming an insulating film thicker than the electrode gold layer of the device and having a thickness of at least 17M;
forming a first hole in the insulating film in the region where the gate is to be formed, and then etching the germanium thin film over a wide area including the hole using the insulating film as an etching mask; a step of forming a second aperture that faces the first aperture; a step of ion-implanting an impurity that is extremely high with respect to germanium; a step of heat-treating the semiconductor substrate together with the germanium thin film; This method includes the steps of depositing a metal layer and performing patterning to form a gate electrode in the first hole and a source N-electrode and a drain electrode in the second hole, respectively. Further, the atmosphere in the step of performing the -F heat treatment is characterized in that it is an atmosphere containing, for example, arsenic.

[Embodiments of the invention]

Next, one embodiment of the manufacturing method of the present invention is shown in FIGS. 2 to 7.
The steps will be explained in the order of steps using figures.

St ions (S) are applied to the semi-insulating GaAs substrate (11).
i”) at an acceleration energy of 120 keV and a dose of 3
．． 5×1012c*t-2 is selectively implanted into the 11□iES FET formation region to form an implantation IM (t2).

Furthermore, a Ge thin film (
A film of approximately 700 OA thick is then deposited by CVI (CVI) to a thickness of approximately 700 OA.

Next, a photoresist film (Il) is deposited and an opening (10a) with a length of 05 μm is formed on the photoresist film by fumetetching (FIG. 2).

Next, trace the window to CVD SIO, film (1!1 to H,
Etching is performed using gas and CF4 gas or by active ion etching (RIE). As a result, [openings (19a) where the snow surface is almost vertical are made of CVD5iO, film (In
is formed. Next, the a@fj film is O through the opening.
Etching is performed by plasma etching using 1 and CF4 gas. As a result, the Ge thin film is over-etched to form an open pore (IF3
a) is formed (Fig. 3).

Next, as shown in Figure 4, photo etching is performed again.
Windows corresponding to the source and drain regions are formed in a photoresist film (10mm thick) and CVD S10.
Etch the film OI and perform CVD sio.

At the same time, the Ge film layer is exposed in the area where the source and drain regions are to be formed.

Next, using a photoresist film (10 mm) as an ion shielding mask, As+ ions (A++) were accelerated with an energy of 1201 c.
Ge at a dose of I x 10 I'cm' at eV
The ion is implanted into the thin film (119) (FIG. 5). At this time, although the ion species is not limited to 1jAII, care must be taken to ensure that the ion range is within the Ge4 film.

Next, the photoresist film (10') is removed, and annealing is performed at 850° C. for 15 minutes in an argon gas atmosphere containing hydrogen to activate the injection layer (12') and form an active layer. . Note that this annealing also serves as the heat treatment performed after forming the Ge thin film in the claims, whereby the Ge and QaAs react, and the As implanted into the Ge thin film is also activated, resulting in Ge? η door is also 101g
□Doped at a high concentration of 4 or more (m 6 F=71
).

Next, sequentially deposit K, f tan gold fi # (Tl> to about 1000' and aluminum metal layer (AZ) to about 4000 x to form electrode layer 0, source electrode layer Q [9, and drain electrode layer). 07) The CVD 5ill film (11)
It is formed by lift-off. Regarding each electrode layer, (21g) is the titanium metal layer part of the gate electrode layer, (22g) is the titanium metal layer part of the gate electrode layer, and (22g) is the titanium metal layer part of the gate electrode layer.
g) is the aluminum metal layer part of the gate electrode layer, (21+
) Id source electrode electrode layer titanium metal layer part, (22g)
(21d) is the titanium metal layer portion of the drain electrode layer; (22d) is the aluminum metal layer portion of the drain electrode layer. Note that each of the above electrodes can be formed at the same time. In addition, the operating layer (12
The electrode metal layer directly connected to the Ge layer 1 or the Ge layer is not limited to the above-mentioned titanium, and may be made of a high melting point metal such as W or Ta, but the thickness of the electrode metal layer is determined by the thickness of the film. The thickness should be determined in consideration of the film thickness, and the thickness must be such that the metal layer is broken at each portion between the source and the gate and between the top and the drain.

In the example above, CVD5in is used as the insulating film for the spacer.
, the case where the film is only 1 m is shown, but in order to form the insulating film for the -sa thicker and more reliably cut off the undesired metal and electrode parts, the insulating film for the -sa with two or more layers is required. A membrane may also be used.

Below, CVD S10. S on the membrane
An embodiment in which i HN4 films are used in a stacked manner will be explained with reference to FIGS. 8 to 11 showing the manufacturing process regarding the differences from the above-mentioned embodiment. It should be noted that - parts that are the same as those in the above-described embodiments are indicated by the same numbers in the drawings, and explanations thereof will be omitted.

First, a CVD 5i02 film (19') was completely deposited on the formed layer 1 and the Ge thin layer α~, and further laminated with silicon heptaide I
! R (S Is N4 film) (21) is deposited, and the layer used in the subsequent electric and circumferential lift-off formation is made into a -sa layer.For this reason, the film thickness of the -sa layer is set to about 5000λ and about 4000H, respectively.
(Figure 8).

Next, a photoresist film (1 layer) is deposited, and the photoresist film (example 05
An opening (10b) is formed from the micrometer opening (10a) by plasma etching the St, N4 film (a) using, for example, 02 gas and CF, e (FIG. 9).

Furthermore, over-etching is performed on CVD5+otR1 (19') through the 513N, P opening (1, Ob), and the opening (1, Ob) has a wider area than the opening (10b).
0c).

Next, the Ge thin film (lF!j) is etched through the opening (10c).This etching is different from the etching applied to the CVD5iOt film in the first embodiment, but no overetching is necessary (FIG. 10).

The following steps are almost the same as those explained in FIGS. 6 and after in the steps of the first embodiment, and the final state shown in FIG. 11 is also the same as that shown and explained in FIG. 7. A MES FET is formed.

When two layers of insulating films are used,
Not only can the film thickness be increased, but the cross-section of the opening can be modified by taking advantage of the etching characteristics of each film, so even when metal wraps around the side of the opening during the electrode metal deposition process, the gap between the electrodes can be improved. Can prevent short circuits. Here CVD5IOt
Although the case of two layers of film and 5ISN 435% has been described, the combination is not limited to these, for example, P
A combination of an SG film, a Sin film, etc. may be used, or a three-layer insulating film may be provided. In the case of three layers, the upper layer (St, N, film),
Alternatively, it may be implemented in relation to the lower layer (CVD Sloy layer).

In each of the above embodiments, the ion implantation method was used as a means for forming the active layer (l force), but it may be formed by other methods, such as an epitaxial layer formed by vapor phase growth.In this case as well, the GeO heat treatment may be carried out under the same conditions as in the above two embodiments.Also, even when forming the active layer by ion implantation, the impurity to be implanted is not limited to silicon, but other impurity ions such as selenium (Se) may be used. Of course.

In the above two examples, an As5G film was used as the insulating film on the Ge thin film, and AJ was added to the Ge thin film during subsequent heat treatment.
Although consideration has been given to introducing the Ge thin film, the insulating film of the Ge thin film does not necessarily need to contain an impurity that becomes a donor for Ge. However, in order to form high-performance transistors with good reproducibility, it is necessary to dope Ge at a high concentration to reduce the contact resistance of the source and drain portions. Therefore, it is preferable to use an insulating film doped with impurities as in the above embodiment.

Next, the Schottky barrier field effect transistor of the present invention is characterized in that the effective spacing between the source and drain can be significantly shortened, and the source, drain, and gate can be formed in self-alignment at one time. However, since electrode metal remains on the insulating film for insulation, if parasitic interaction with these remaining metals becomes a problem, some or all of these metals must be removed. All you have to do is add a process. This process is the usual 7
This can be easily done by combining the etching technique and the etching technique.

〔Effect of the invention〕

As described above, according to the present invention, an effective source,
The gap between the gates can be controlled by the amount of overetching of the G@thin film explained in the first embodiment or the lower layer G@thin film explained in the second embodiment. Since the source and drain regions can be formed in self-alignment, channel series resistance can be significantly reduced without impairing gate breakdown voltage.

Furthermore, ohmic contact electrodes in the source and drain parts,
The Schottky contact electrode in the gate area can be formed from the same metal at the same time, and there is no need for an alloying process to form an ohmic contact. A ME, S' FET with electrodes is obtained.

Furthermore, since the mask alignment precision required in the conventional MES FET manufacturing process is not required, the effect of improving productivity is significant.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional Schottky barrier gate field effect transistor, and FIGS. Figure 11
The figures are all cross-sectional views showing the manufacturing method of another embodiment in the order of steps. 11... Semi-insulating GaAs substrate 12.
-... Operating layer 15... Gate electrode layer 16... Source electrode layer 17... Drain electrode layer 21 (21g
, 21g, 21d)...Titanium metal layer portion 22 of the electrode (22g, 22g, 22d)...Aluminum metal layer portion 18 of the electrode...Ge thin layer 19...- ...CVD810! Layer (lower layer) 20...81. N4 layer (upper layer) agent Patent attorney Inoue - Male Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure I Figure B Figure 1O

Claims (1)

[Scope of Claims] (11) A step of forming an active layer on the main surface of a high resistivity semiconductor substrate, a step of depositing a germanium thin film on the surface of the active layer, and a step of depositing a bond layer on the germanium thin film. A step of forming an insulating film having at least one layer thicker than the electrode metal layer, and forming a first hole in the insulating film in the area where the gate is to be formed, and then using the insulating film as an etching mask to form the first hole in the germanium thin film. a step of etching a wider area than the opening; a step of providing a second opening in the insulating film that faces the first opening; and a step of ion-implanting an impurity to serve as a donor for germanium; a step of applying pressure heat treatment to the semiconductor substrate together with a germanium N film;
A method for manufacturing a field effect transistor, comprising the steps of depositing and patterning an electrode gold FAN to form a gate electrode in a first opening and a source electrode and a drain electrode in a second opening, respectively. . (2) The method for manufacturing a field effect transistor according to claim 1, wherein the atmosphere in the step of heat-treating the semiconductor substrate together with the germanium thin film is an atmosphere containing arsenic.