JP2003163225A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing on-resistance of channels without increasing an element area and causing characteristic deterioration such as short channel effect or the like, and to provide its manufacturing method. <P>SOLUTION: This device comprises a gate electrode 7 formed on a semiconductor substrate 1, two conductive layers 3 to be a source or drain, which are formed on the semiconductor substrate 1, and at least two channel layers 2a, 2b, which are arranged in a direction perpendicular to a main surface of the semiconductor substrate 1 and are formed so as to connect in parallel to the two conductive layers 3. The channel layers 2a, 2b comprise a prescribed conductivity type, and at least two gate diffusion layers 4a, 4b, which form pn junctions with each channel layer 2a, 2b under a gate electrode 7, respectively, are formed, and at least two gate diffusion layers 4a, 4b are electrically connected by a connection layer 5. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, communication MMIC (Monolithic Mic)
rowave Integrated Circuits) requires not only downsizing but also high frequency operation. Field effect transistors (FETs) are also required to have high performance such as reduction of input / output signal loss and distortion in order to support high frequency use.

The GaAs field effect transistor used in the above MMIC forms an n-type channel layer by implanting, for example, silicon (Si) into a semi-insulating GaAs substrate by an ion implantation method or the like, It is manufactured by forming a gate electrode, a source electrode, and a drain electrode on a substrate on which a channel layer is formed.

The GaAs field effect transistor controls the current flowing from the drain electrode to the source electrode by changing the depletion layer thickness according to the voltage applied to the gate electrode. For example, the Schottky barrier gate structure ( MES-FET), pn junction gate structure (J-FE
T) etc.

A GaAs field effect transistor having a pn junction gate structure has a gate diffusion layer formed by diffusing p-type impurities by a thermal diffusion method or the like under the above-mentioned gate electrode, and has an n-type channel layer. The current flowing from the drain electrode to the source electrode is controlled by controlling the depletion layer thickness caused by the pn junction with.

In order to improve the performance of such a field effect transistor, it is necessary to reduce the on-resistance of the channel. To reduce the on-resistance, the gate length is shortened or the gate width is reduced. Need to be long.

[0007]

However, when the gate length is shortened, there is a problem that a leak current is generated due to the short channel effect, and the characteristics are deteriorated.

Further, if the gate width is lengthened, the element area increases, and there is a problem that the semiconductor chip mounting the field effect transistor cannot be downsized.

The present invention has been made in view of the above circumstances, and an object thereof is to increase the element area without increasing the element area.
Without causing deterioration of characteristics such as short channel effect,
It is an object of the present invention to provide a semiconductor device capable of reducing the on-resistance of a channel and a manufacturing method thereof.

[0010]

In order to achieve the above-mentioned object, a semiconductor device of the present invention comprises a gate electrode formed on a semiconductor substrate and two conductive layers, which are a source and a drain formed on the semiconductor substrate. A layer and at least two channel layers that are arranged in a direction perpendicular to the main surface of the semiconductor substrate and are connected in parallel to the two conductive layers.

The channel layer has a predetermined conductivity type,
It further includes at least two gate diffusion layers each forming a pn junction with each channel layer under the gate electrode, and a connection layer connecting at least two gate diffusion layers.

The connection layer is formed so as to be connected to the gate electrode and not overlap with the channel layer.

In the above semiconductor device of the present invention, at least two channel layers are arranged in a direction perpendicular to the main surface of the semiconductor substrate, and are connected in parallel to the conductive layers to be the source or the drain. Thus, since at least two channel layers are connected in parallel to the conductive layer, the resistance component caused by the channel layers can be suppressed to about half, and the on-resistance of the channel layers can be reduced. In addition, a gate diffusion layer that forms a pn junction is formed in each channel layer, and the gate diffusion layer is electrically connected by the connection layer, so that the gate diffusion layer is always kept at the same potential and the gate electrode is formed. The applied voltage controls the thickness of the depletion layer formed by the pn junction between each channel layer and each gate diffusion layer, thereby controlling the current flowing in each channel layer.

Further, in order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention comprises a first channel layer on a semiconductor substrate and two first channel layers connected to the first channel layer to be a source or a drain. Forming a conductive layer on the semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a second channel layer on the semiconductor layer, and forming a second channel layer on the semiconductor layer.
Forming two second conductive layers which are connected to the channel layer and which are connected to the two first conductive layers, respectively, and which become a source or a drain, and a gate electrode is formed on the semiconductor layer. And the process.

After the step of forming the first channel layer and the first conductive layer, and before the step of growing the semiconductor layer, a pn junction is formed on the semiconductor substrate with the first channel layer. After the step of forming the first gate diffusion layer and the step of forming the second channel layer and the second conductive layer, respectively, and before the step of forming the gate electrode, the semiconductor layer is formed. A step of forming a second gate diffusion layer that forms a pn junction with the second channel layer, and a connection layer that connects the first and second gate diffusion layers to the semiconductor substrate and the semiconductor layer. And a forming step.

In the step of forming the gate electrode,
It is formed so as to be connected to the second gate diffusion layer and the connection layer.

In the step of growing the semiconductor layer,
The semiconductor layer is grown by an epitaxial growth method. In the step of growing the semiconductor layer, a semiconductor layer having substantially the same composition as that of the semiconductor substrate is grown by the epitaxial growth method. The same composition as used herein means that, for example, those including crystal orientation, resistivity, impurity concentration, etc. are equal.

In the method of manufacturing a semiconductor device of the present invention described above, after the first channel layer and the first conductive layer are formed on the semiconductor substrate, the semiconductor layer is grown on the semiconductor substrate. Then, after growing the semiconductor layer, the second channel layer and the second contact layer are formed, and the last gate electrode is formed. Thus, the channel layer formed in step 1 will be formed.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of the semiconductor device according to the present embodiment, FIG. 1B is a sectional view taken along the line AA 'of FIG. 1A, and FIG. Is B- in FIG.
It is sectional drawing in a B'line.

As shown in FIG. 1, the semiconductor device according to this embodiment is a semiconductor substrate 1 made of semi-insulating GaAs.
In addition, n containing, for example, silicon (Si) as an n-type impurity
Type first channel layer 2a and second channel layer 2b
Are formed side by side in the vertical direction on the main surface of the substrate 1.

At both ends of the first channel layer 2a, an n-type first contact layer 3a which serves as a source or a drain and contains silicon as an n-type impurity is formed.
Further, both ends of the second channel layer 2b serve as a source or a drain, and have n containing silicon as an n-type impurity.
A second mold contact layer 3b is formed. The first contact layer 3a and the second contact layer 3b are connected to each other to form the contact layer 3, and the first and second channel layers 2a and 2b are electrically parallel to the contact layer 3. It is connected to the.

A first gate diffusion layer 4a containing zinc (Zn) as a p-type impurity is formed in the first channel layer 2a, and the n-type first channel layer 2a and the p-type first channel layer 2a are formed.
A pn junction is formed with the gate diffusion layer 4a.

A second gate diffusion layer 4b containing zinc (Zn) as a p-type impurity is also formed in the second channel layer 2b, and the n-type second channel layer 2b and the p-type second channel layer 2b are formed.
A pn junction is formed with the gate diffusion layer 4b.

First and second gate diffusion layers 4a and 4b
Are formed by stretching so as to be orthogonal to the channel forming directions of the first and second channel layers 2a and 2b. In the regions where the first and second channel layers 2a and 2b are not formed, the first and second gate diffusion layers 4a and 4b are formed by the p-type connection layer 5 containing magnesium (Mg) as a p-type impurity. Are connected.

A first interlayer insulating film 6a made of silicon nitride or the like is formed on the semiconductor substrate 1, and the first interlayer insulating film 6a is formed.
In the inter-layer insulation film 6a, an opening for exposing the second gate diffusion layer 4b, the connection layer 5 and the second contact layer 3b is formed.

In the gate opening portion of the first interlayer insulating film 6a, for example, titanium (Ti), platinum (Pt), gold (A
The gate electrode 7 composed of the laminated film of u) is formed,
The gate electrode 7 is connected to the second gate diffusion layer 4b and the connection layer 5 formed on the semiconductor substrate 1.

In the opening of the first interlayer insulating film 6a to the second contact layer 3b, for example, a laminated film of gold-germanium (AuGe) and nickel (Ni) and the second contact layer 3b are formed. An alloyed layer 8 with a semiconductor material is formed.

First interlayer insulating film 6a and gate electrode 7
Is covered with a second interlayer insulating film 6b made of silicon nitride or the like, and an opening for exposing the alloying layer 8 is formed in the second interlayer insulating film 6b.

In the opening exposing the alloying layer 8 of the second interlayer insulating film 6b and on the second interlayer insulating film 6b, for example, titanium (Ti), platinum (Pt), and gold (Au) are laminated. A source / drain electrode 9 serving as a source or drain made of a film is formed.

In the semiconductor device according to this embodiment, the two first and second channel layers 2a and 2b are electrically connected in parallel to the contact layer 3, and the n-type channel layer 2 is connected.
Since the p-type gate diffusion layers 4a and 4b are formed on the a and 2b, respectively, a pn junction gate structure (J-FE) is formed.
The GaAs transistor of T) is formed. The two gate diffusion layers 4a and 4b formed in the respective channel layers 2a and 2b are electrically connected by the connection layer 5, so that the same potential is always obtained, and the voltage applied to the gate electrode 7 is obtained. As a result, the depletion layer thickness formed by the pn junction between the channel layers 2a and 2b and the gate diffusion layers 4a and 4b is controlled, and the channel layers 2a and 4b are controlled.
The current flowing in 2b will be controlled.

As described above, according to the semiconductor device of the present embodiment having the above-described structure, since the channel layers 2a and 2b are connected in parallel to the contact layer 3, the resistance caused by the channel layers 2a and 2b is reduced. The component can be reduced to about half, and the on-resistance of the transistor can be reduced. In addition, the channel layers 2a,
Since 2b are formed side by side, the element area is not increased. Further, as described above, since the on-resistance of the transistor can be reduced with the same gate length as that of the conventional one, deterioration of characteristics such as a short channel effect due to the shortened gate length is not caused. In this way, since the on-resistance of the transistor can be reduced, it is possible to improve the performance while suppressing loss and distortion of the signal.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. The sectional views shown in FIGS. 2 to 9 are sectional views corresponding to FIG.

First, as shown in FIG.
An insulating film such as silicon nitride (SiN) is formed on a semiconductor substrate 1a made of a compound semiconductor such as CVD (Chem.
A protective film (hereinafter referred to as a through film) 11 at the time of ion implantation is formed by depositing about 50 nm by the ical vapor deposition method. For example, the resistivity of the semiconductor substrate 1a is about 2.5 × 10 ¹⁷ Ωcm.

Next, a resist is applied on the through film 11 and a resist film R1 having a pattern having an opening in a region for forming a contact layer is formed by a photolithography technique.
To form. Subsequently, as shown in FIG. 2B, with the patterned resist film R1 as a mask, an impurity such as silicon (Si) is used as an n-type impurity at 150 keV.
The n-type first contact layer 3a is formed on the semiconductor substrate 1a by implanting at about 3 × 10 ¹³ atoms / cm ² with an accelerating voltage of about 3 × 10 ¹³ atoms / cm ² .

Next, after removing the resist film R1 by wet etching or dry etching, a resist is applied again on the through film 11 and a pattern having an opening is formed in a region for forming a channel layer of a transistor by photolithography technique. A resist film R2 is formed.
Subsequently, as shown in FIG. 2C, using the patterned resist film R2 as a mask, an impurity such as silicon (Si) as an n-type impurity is accelerated to 8 × 10 ¹² atoms / cm 2 at an acceleration voltage of about 140 keV. ^{About 2 is} implanted to form the n-type first channel layer 2a on the semiconductor substrate 1a.

Next, after removing the resist film R2 by wet etching or dry etching, FIG.
As shown in (d), a resist is applied again on the through film 11, and a resist film R3 having a pattern having an opening in a region where a gate diffusion layer is to be formed is formed by a photolithography technique.

Next, as shown in FIG. 3E, the through film 11 exposed in the opening is selectively removed by dry etching using the patterned resist film R3 as a mask to gate the through film 11 to the gate. After forming the opening 11a, the resist film R3 is removed by wet etching or dry etching.

Next, as shown in FIG. 3F, for example, zinc (Zn) is diffused as a p-type impurity from the gate opening 11a formed in the through film 11 to form a p-type first film. The gate diffusion layer 4a is formed on the semiconductor substrate 1a on which the first channel layer 2a is formed.

Next, after removing the through film 11 by wet etching or dry etching, FIG.
As shown in FIG.
a GaAs epitaxial layer 1b having the same composition as a is grown to obtain a substrate 1a and an epitaxial layer 1b having the same composition.
A semiconductor substrate 1 made of is formed. The same composition as used herein means that, for example, those including crystal orientation, resistivity, impurity concentration, etc. are equal. Then, in order to make the formation conditions of the first and second channel layers formed later the same, the resistivity of the epitaxial layer 1b is set to the substrate 1a.
The same as above, about 2.5 × 10 ¹⁷ Ωcm.

Next, on the semiconductor substrate 1, for example, again,
An insulating film such as silicon nitride (SiN) is deposited to a thickness of about 50 nm by the CVD method to form the through film 12. Subsequently, a resist is applied on the through film 12, and a resist film R4 having a pattern having an opening in a region where a contact layer is formed is formed by a photolithography technique. Subsequently, as shown in FIG. 4H, using the patterned resist film R4 as a mask, an impurity such as silicon (Si) as an n-type impurity is accelerated to 3 × 10 ¹³ atoms / cm 3 at an acceleration voltage of about 150 keV. Inject about ^two , the first
An n-type second contact layer 3b connected to the contact layer 3a is formed. As a result, the first contact layer 3
The contact layer 3 including a and the second contact layer 3b is formed.

Next, after removing the resist film R4 by wet etching or dry etching, a resist is applied again on the through film 12 and a pattern having an opening is formed in a region for forming a channel layer of a transistor by photolithography technique. A resist film R5 is formed.
Subsequently, as shown in FIG. 4I, using the patterned resist film R5 as a mask, an impurity such as silicon (Si) as an n-type impurity is accelerated to an acceleration voltage of about 140 keV and a pressure of 8 × 10 ¹² atoms / cm 2. ^{About 2 is} implanted to form the n-type second channel layer 2b on the semiconductor substrate 1.

Next, after removing the resist film R5 by wet etching or dry etching, a resist is applied again on the through film 12, and the first gate diffusion layer is formed by the photolithography technique in a region which does not overlap with the channel layer. A resist film R6 having a pattern having an opening in a region for forming a connection layer connected to 4a is formed.
Then, as shown in FIG. 5 (j-1), using the patterned resist film R6 as a mask, impurities such as magnesium (Mg) as a p-type impurity are accelerated at an accelerating voltage of about 200 keV and 1 × 10 ¹⁴ atoms. / Cm ^{2 is} implanted to form the p-type connection layer 5 on the semiconductor substrate 1. As a result, as shown in the plan view of FIG. 5 (j-2), the connection layer 5 connected to the first gate diffusion layer 4a is formed in the region which does not overlap with the channel layers 2a and 2b.

Next, as shown in FIG. 5K, after removing the resist film R6 and the through film 12 by wet etching or dry etching, a heat treatment at about 800 ° C. is performed in an arsenic (As) atmosphere. Then, the implanted ions are activated.

Next, as shown in FIG. 6L, on the activated semiconductor substrate 1, for example, silicon nitride (Si
An insulating film such as N) is deposited to a thickness of about 300 nm by the CVD method to form the first interlayer insulating film 6a.

Next, a resist is applied on the first interlayer insulating film 6a, and a resist film R7 having a pattern having an opening in a region for forming a gate diffusion layer is formed by a photolithography technique. Subsequently, as shown in FIG. 6M, the first interlayer insulating film 6a exposed in the opening is selectively removed by dry etching using the patterned resist film R7 as a mask to remove the first interlayer insulating film 6a. A gate opening C1 is formed in the insulating film 6a.

Next, as shown in FIG. 6 (n), after removing the resist film R7 by wet etching or dry etching, a p-type impurity is introduced through the gate opening C1 formed in the first interlayer insulating film 6a. For example, zinc (Zn) is diffused to form the p-type second gate diffusion layer 4b.
Are formed on the semiconductor substrate 1 on which the second channel layer 2b is formed. At this time, the first gate diffusion layer 4a and the second gate diffusion layer 4b are electrically connected by the connection layer 5 in a region (not shown).

Next, as shown in FIG. 7 (o), by vapor deposition or sputtering on the semiconductor substrate 1 exposed on the gate opening C1 of the first interlayer insulating film 6a and on the first interlayer insulating film 6a. Metals such as titanium, titanium (Ti), platinum (Pt), and gold (Au) are 30 nm and 50 nm, respectively.
The gate electrode layer 7a is formed by depositing about 200 nm. Subsequently, a resist is applied on the gate electrode layer 7a, and a resist film R8 having a gate electrode pattern is formed by a photolithography technique.

Next, as shown in FIG. 7P, the gate electrode layer 7a is selectively removed by an ion milling method using the patterned resist film R8 as a mask to form the gate electrode 7. After that, the resist film R8 is removed by wet etching or dry etching.

Next, as shown in FIG. 7 (q), a resist is applied on the gate electrode 7 and the first interlayer insulating film 6a, and the contact layer 3 is formed by a photolithography technique.
A resist film R9 having a pattern that exposes the film is formed. Then, using the patterned resist film R9 as a mask, the first interlayer insulating film 6a exposed in the opening is selectively removed by dry etching to form the electrode extraction opening C2 in the first interlayer insulating film 6a. Form.

Next, as shown in FIG. 8 (r), the entire surface of the semiconductor substrate 1 and the resist film R9 exposed in the electrode lead-out opening C2 of the first interlayer insulating film 6a is vapor-deposited or sputtered. Gold germanium (AuGe)
And a metal such as nickel (Ni)
The metal layer 8a is formed by depositing about 0 nm and 45 nm.

Next, as shown in FIG. 8 (s), the resist film R9 is formed together with the resist film R9 by the lift-off method.
By removing the metal layer 8a deposited thereon and performing heat treatment at about 400 ° C., the alloyed layer 8 of the metal layer 8a remaining in the electrode extraction opening C2 and the n-type second contact layer 3b is removed. Form.

Next, as shown in FIG. 8 (t), a CV insulating film such as silicon nitride (SiN) is formed on the entire surface of the first interlayer insulating film 6a, the alloying layer 8 and the gate electrode 7.
The second interlayer insulating film 6b is formed by depositing about 200 nm by the D method.

Next, as shown in FIG. 9 (u), a resist is applied on the second interlayer insulating film 6b, and a photolithography technique is used to form an opening in a region where a contact hole reaching the alloying layer 8 is formed. Forming a resist film R10 having a pattern. Then, by using the patterned resist film R10 as a mask, the second interlayer insulating film 6b exposed in the opening is selectively removed by wet etching or dry etching to alloy the second interlayer insulating film 6b. A contact hole C3 reaching the layer 8 is formed.

Next, as shown in FIG. 9 (v), the resist film R10 is removed by wet etching or dry etching, and then the alloying layer 8 exposed in the contact hole C3 of the second interlayer insulating film 6b and Metals such as titanium (Ti), platinum (Pt), and gold (Au) are deposited on the second interlayer insulating film 6b by vapor deposition or sputtering to a thickness of about 50 nm, 50 nm, and 600 nm, respectively, to form a source or a drain. The source / drain electrode layer 9a is formed. Subsequently, a resist is applied on the source / drain electrode layer 9a, and a resist film R11 having a source or drain electrode pattern is formed by photolithography.

In the subsequent steps, the source / drain electrode layer 9a is selectively removed by the ion milling method using the patterned resist film R11 as a mask to form the source / drain electrodes 9, and then the resist is formed. The film R11 is removed by wet etching or dry etching. As described above, the semiconductor device according to this embodiment is manufactured.

According to the method of manufacturing the semiconductor device of the present embodiment, the second channel layer 2b and the contact layer 3 are formed.
After performing an epitaxial process for producing a new substrate 1b on which b and the like are formed, an ion implantation process for forming a channel layer, a contact layer, a gate diffusion layer, and the like is performed in the same manner as the conventional process. By performing in the same manner, it is possible to manufacture a semiconductor device having the above-described effects.
Then, a photomask used to form the first and second channel layers 2a and 2b by ion implantation, a photomask used to form the first and second contact layers 3a and 3b by ion implantation, and a first mask By using the same photomask as the photomask used to form the second gate diffusion layers 4a and 4b by ion implantation, the first channel layer 2a, the first contact layer 3a, and the first The second channel layer 2b, the second contact layer 3b, and the second contact layer 3b are formed at substantially the same location as the gate diffusion layer 4a.
The second gate diffusion layer 4b can be formed, which facilitates reliable alignment. Further, the photomask required for adding a new step is only the photomask used for forming the connection layer 5 by ion implantation,
It is possible to reduce an increase in cost due to an increase in the number of steps.

The semiconductor device of the present invention is not limited to the description of the above embodiment. For example, in the present embodiment, an example in which two channel layers are formed in parallel on the main surface of the substrate has been described, but at least two or more channel layers may be formed.
For example, three channel layers can be arranged in parallel on the main surface of the substrate. Besides, various modifications can be made without departing from the scope of the present invention.

[0059]

According to the present invention, the on-resistance of the channel can be reduced without increasing the element area and without deteriorating the characteristics such as the short channel effect.

[Brief description of drawings]

1A is a plan view of a semiconductor device according to this embodiment, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A, and FIG. ) Is BB ′ in FIG.
It is sectional drawing in a line.

FIG. 2 is a plan view of a semiconductor device manufacturing method according to the present embodiment.
It is sectional drawing to the formation process of a 1st channel layer.

FIG. 3 is a cross-sectional view following FIG. 2 up to the step of forming a first gate diffusion layer.

FIG. 4 is a cross-sectional view following FIG. 3 up to a step of forming a second channel layer.

FIG. 5 is a cross-sectional view up to the step of forming a connection layer, which is subsequent to FIG.

FIG. 6 is a cross-sectional view following FIG. 5 up to the step of forming a second gate diffusion layer.

FIG. 7 is a cross-sectional view following FIG. 6 up to the step of forming an electrode extraction opening.

8 is a cross-sectional view following FIG. 7 up to the step of forming a second interlayer insulating film.

FIG. 9 is a cross-sectional view following FIG. 8 up to the step of forming source / drain electrode layers.

[Explanation of symbols]

1, 1a, 1b ... Semiconductor substrate, 2a ... First channel layer, 2b ... Second channel layer, 3 ... Contact layer, 3a
... first contact layer, 3b ... second contact layer, 4
a ... a first gate diffusion layer, 4b ... a second gate diffusion layer,
5 ... Connection layer, 6a ... First interlayer insulating film, 6b ... Second interlayer insulating film, 7 ... Gate electrode, 8 ... Alloying layer, 9 ... Source / drain electrode, 11, 12 ... Through film, R1, R2
R3, R4, R5, R6, R7, R8, R9, R10,
R11 ... Resist film, C1 ... Gate opening, C2 ... Electrode extraction opening, C3 ... Contact hole.

Claims (8)

[Claims] 1. A gate electrode formed on a semiconductor substrate, two conductive layers serving as a source or a drain formed on the semiconductor substrate, and two conductive layers that are arranged in a direction perpendicular to a main surface of the semiconductor substrate. A semiconductor device having at least two channel layers formed in parallel with a conductive layer. 2. The channel layer has a predetermined conductivity type, and comprises at least two gate diffusion layers each forming a pn junction with each channel layer under the gate electrode, and at least two gate diffusion layers. The semiconductor device according to claim 1, further comprising a connection layer for connection. 3. The semiconductor device according to claim 2, wherein the connection layer is connected to the gate electrode and is formed so as not to overlap with the channel layer. 4. A step of forming a first channel layer on a semiconductor substrate and two first conductive layers which are connected to the first channel layer and serve as a source or a drain, respectively, and a semiconductor on the semiconductor substrate. A step of growing a layer, a second channel layer in the semiconductor layer, and two second channel layers connected to the second channel layer and a source or a drain respectively connected to the two first conductive layers. A method of manufacturing a semiconductor device, comprising: forming two conductive layers respectively; and forming a gate electrode on the semiconductor layer. 5. After the step of forming the first channel layer and the first conductive layer, and before the step of growing the semiconductor layer, the first channel layer and the pn are formed on the semiconductor substrate. After the step of forming a first gate diffusion layer that forms a junction, the step of forming the second channel layer and the second conductive layer, and before the step of forming the gate electrode, the semiconductor A second gate diffusion layer that forms a pn junction with the second channel layer in the layer, and a connection that connects the first and second gate diffusion layers to the semiconductor substrate and the semiconductor layer. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of forming a layer. 6. In the step of forming the gate electrode,
6. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is formed so as to be connected to the second gate diffusion layer and the connection layer. 7. In the step of growing the semiconductor layer,
The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor layer is grown by an epitaxial growth method. 8. In the step of growing the semiconductor layer,
8. A semiconductor layer having a composition substantially the same as that of the semiconductor substrate is grown by the epitaxial growth method.
A method for manufacturing a semiconductor device as described above.