JPS6038883A - Manufacture of schottky gate type field effect transistor - Google Patents
Manufacture of schottky gate type field effect transistorInfo
- Publication number
- JPS6038883A JPS6038883A JP14632083A JP14632083A JPS6038883A JP S6038883 A JPS6038883 A JP S6038883A JP 14632083 A JP14632083 A JP 14632083A JP 14632083 A JP14632083 A JP 14632083A JP S6038883 A JPS6038883 A JP S6038883A
- Authority
- JP
- Japan
- Prior art keywords
- lift
- material layer
- gate
- semiconductor layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 230000005669 field effect Effects 0.000 title 1
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 238000002513 implantation Methods 0.000 claims abstract description 4
- 239000007769 metal material Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 229910052594 sapphire Inorganic materials 0.000 abstract description 2
- 239000010980 sapphire Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
［技術分野］
この発明は、ショットキゲート型Ｆ Ｌ！： Ｔ （Ｍ
ＪＥＳＦＥＴ）の製造技術、特に、セルフアライメン
ト構造のガリウムひ素Ｍ Ｅ Ｓ ｌ？ Ｅ Ｔの製造
に利用して有効な技術に関するものである。[Detailed Description of the Invention] [Technical Field] This invention relates to a Schottky gate type F L! : T (M
JESFET) manufacturing technology, especially self-aligned structure gallium arsenide M E S I? This article relates to effective technology that can be used to manufacture ET.
［背景技術］
ガリウムひ素（ＧａＡｓ）はシリコンに代わる次世代の
半導体材料であるといわれている。それは、ＧａＡｓの
電子移動度がシリコンに比べて大きく、しかもＧａＡｓ
自体が半絶縁性で素子間分離が容易であるなどという材
料面での利点を有しているからである。[Background Art] Gallium arsenide (GaAs) is said to be a next-generation semiconductor material that will replace silicon. This is because GaAs has higher electron mobility than silicon, and GaAs
This is because it has material advantages such as being semi-insulating and easy to isolate between elements.
ＧａＡｓを基板とした集積回路においては、ＭＥＳＦＥ
Ｔ構造が主どして用いられる。高速なＭＥ Ｓ Ｆ Ｅ
Ｔを得ようとする場合、ゲー１〜・ソース間およびゲ
ート・ドレイン間の寄生直列抵抗が問題となる。In integrated circuits using GaAs as a substrate, MESFE
The T structure is mainly used. Fast ME S F E
When trying to obtain T, parasitic series resistance between gate and source and between gate and drain becomes a problem.
この寄生直列抵抗を低減しＦＥＴを高速化するには、ゲ
ー１−とソースおよびドレインとの間を自己整合的に形
成することが有効である（以上、たとえば、「日経エレ
クトロニクスＪ 、１９８２年１１月８日号、ｐ１０５
−１２７、特ニｐ１２０〜１２２参照）。In order to reduce this parasitic series resistance and speed up the FET, it is effective to form the gate 1- and the source and drain in a self-aligned manner. Monthly 8th issue, p105
-127, special page 120-122).
［発明の目的コ
この発明の目的は、ＭＥＳＦＥＴにおけるゲーｉ〜とソ
ースおよびドレインとの間を自己整合的に形成しうるセ
ルファライン技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a self-line technology that can form self-alignment between the gate i and the source and drain in a MESFET.
この発明の他の目的は、絶縁基板の一面に形成された半
導体層に、イオン打込みによる打込み深さの差を利用す
ることによって、低濃度領域と高濃度領域とを形成する
ようにした技術を提供することにある。Another object of the present invention is to provide a technique for forming a low concentration region and a high concentration region in a semiconductor layer formed on one surface of an insulating substrate by utilizing the difference in implantation depth due to ion implantation. It is about providing.
この発明の前記ならびにそのほかの目的と新規な特徴は
、この明細書の記述および添付図面から明らかになるで
あろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
この出願において開示される発明のうち代表的なものの
概要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、この発明の代表例では、配線をリフトオフ処
理によって形成するが、そのためのリフ１−オフ材料層
をイオン打込みに対するマスクとしても利用し、絶縁基
板の一面に形成されたＧ ａＡ ｓ半導体層に対し、ソ
ースおよびドレインとなる高濃度領域と、ゲート下の低
濃度領域とを形成するようにしている。それによって、
ゲー１−とソースおよびドレインとの間を自己整合的に
形成するという目的を達成するものである。That is, in a typical example of the present invention, wiring is formed by lift-off processing, and the lift-off material layer for this purpose is also used as a mask for ion implantation, and a GaAs semiconductor layer formed on one surface of an insulating substrate is On the other hand, a high concentration region serving as a source and a drain, and a low concentration region under the gate are formed. Thereby,
This achieves the purpose of forming the gate 1- and the source and drain in a self-aligned manner.
［実施例コ
以下、この発明の内容を第１図〜第５図に示した実施例
に基づいて具体的に説明する。[Example 7] Hereinafter, the content of the present invention will be specifically explained based on the example shown in FIGS. 1 to 5.
（第１図を参照して）
まず、サファイヤなどの絶縁基板１の一面にＧａ Ａｓ
単結晶薄膜からなる半導体層２を形成し、その上に二酸
化シリコン膜３１およびシリコンナイトライド膜３２か
らなるリフトオフ材料層３を全体的に堆積する。リフト
オフ材料層３の主体は下層の二酸化シリコン膜３１であ
り、その膜３１−の厚さはリフトオフの必要上かなり厚
い。しかし、リフトオフ材料Ｍ３は、それを通して下層
の半導体層２にイオン打込みが可能な厚さをもっている
ことも必要であり、それら両者の兼ね合いからその厚さ
が定まる。(Refer to Figure 1) First, GaAs is deposited on one surface of an insulating substrate 1 made of sapphire or the like.
A semiconductor layer 2 made of a single crystal thin film is formed, and a lift-off material layer 3 made of a silicon dioxide film 31 and a silicon nitride film 32 is entirely deposited thereon. The main body of the lift-off material layer 3 is the underlying silicon dioxide film 31, and the thickness of the film 31- is quite thick due to the necessity of lift-off. However, the lift-off material M3 also needs to have a thickness that allows ions to be implanted into the underlying semiconductor layer 2 through it, and its thickness is determined by the balance between these two factors.
（第２図を参照して）
ついで、通常のホトエツチングによって、リフトオフ材
料層３のうち、ゲートを形成すべき部分を選択的に除去
する。この場合、上層の膜３２をマスクとして下層の膜
３１をサイドエッチすることにより、エツチング端部に
ひさし構造４を形成する。このひさし構造４は、後で行
なうリフトオフを容易にし、またゲー１〜とソースおよ
びドレインとの間の電気的ショー１〜を確実に防止する
という好ましい機能を有するものである。(See FIG. 2) Next, the portion of the lift-off material layer 3 where the gate is to be formed is selectively removed by normal photoetching. In this case, by side-etching the lower film 31 using the upper film 32 as a mask, the canopy structure 4 is formed at the etched end. This canopy structure 4 has the desirable function of facilitating lift-off performed later and reliably preventing electrical shorts 1~ between the gates 1~ and the source and drain.
（第３図を参照して）
部分的なリフトオフ材料層３の形成後、基板１上の半導
体層２に対し、Ｎ型不純物たとえばシリコンを全体的に
イオン打込み法によって導入する。(See FIG. 3) After the formation of the partial lift-off material layer 3, an N-type impurity, such as silicon, is entirely introduced into the semiconductor layer 2 on the substrate 1 by ion implantation.
この際、主として打込みエネルギーを制御することによ
って、打込みイオンが、グー１〜部では大部分が下地の
絶縁基板１に達するようにするとともに、ゲート以外の
その他の場所では半導体層２中になるようにする。した
がって、このようなイオン打込みおよびそれに続くアニ
ール処理により、リフトオフ材料層３下の半導体層２の
部分２１がＮ＋型の高濃度領域、露出しているゲー１〜
を形成すべき部分２２がＮ−型の低濃度領域とそれぞれ
なすことができる。At this time, mainly by controlling the implantation energy, the implanted ions are made to reach the underlying insulating substrate 1 in most of the regions 1 to 1, and to be in the semiconductor layer 2 in other locations other than the gate. Make it. Therefore, by such ion implantation and subsequent annealing treatment, the portion 21 of the semiconductor layer 2 under the lift-off material layer 3 becomes an N+ type high concentration region, and the exposed gates 1 to
The portions 22 to be formed can be respectively formed as N-type low concentration regions.
（第４図を参照して）
次に、スパッタリング法などのような高指向性の堆積方
法によってグー１−用金属材料（たとえば。(See FIG. 4) Next, a metal material for goo 1 (for example) is deposited by a highly directional deposition method such as a sputtering method.
白金あるいは白金シリサイド）を堆積すると、前記ひさ
し構造４によりゲート用金属材Ｍｌ ５は段切れを伴な
って形成される。したがって、リフトオフ材料層３をエ
ツチングすることによって、ゲート用金属材料５のうち
、層３上に付着していた部分を層３とともに除去（リフ
トオフ）し、Ｎ−型の領域２２上にのみグー１〜用金属
材料５を残すことができる。この部分的なものがゲーＩ
−金属膜５１となる。When platinum (platinum or platinum silicide) is deposited, the gate metal material Ml 5 is formed with steps due to the eaves structure 4. Therefore, by etching the lift-off material layer 3, the portion of the gate metal material 5 that was attached to the layer 3 is removed (lifted off) together with the layer 3, and the goo 1 is formed only on the N-type region 22. The metal material 5 for ~ can be left behind. This partial thing is game I
- Becomes a metal film 51.
（第５図を参照して）
その後、ホトエツチングにより素子以外の部分のＮ＋型
の領域２１を選択的に除去した後、全面にＣＶＤ法によ
って二酸化シリコンなどからなるパシベーション膜６を
形成する。そして、膜６に接続用の穴７をあけてから、
公知の真空蒸着およびホトエツチングの各技術によって
ソース電極８１１、ドレイン電極８２およびゲート引出
し電極（図示せず）、ならびに素子間の配線（図示せず
）を形成し、Ｇａ Ａｓ’ ＭＥＳＦＥＴを完成する。(Refer to FIG. 5) After that, the N+ type region 21 other than the element is selectively removed by photoetching, and then a passivation film 6 made of silicon dioxide or the like is formed on the entire surface by CVD. Then, after making a connection hole 7 in the membrane 6,
A source electrode 811, a drain electrode 82, a gate lead electrode (not shown), and interconnections between elements (not shown) are formed by known vacuum evaporation and photoetching techniques to complete the GaAs' MESFET.
［効果］
ＭＥＳＦＥＴのゲートとソースおよびドレインとの間を
セルファライン化しているので、前記寄生直列抵抗を低
減してデバイスを高速化することカテキル。そして、特
に配線形成のためのリフトオフ材料層をイオン打込みに
苅するマスクどしても利用しているので、比較的に簡易
なプロセスとなるという効果が得られる。[Effects] Since the gate, source, and drain of the MESFET are formed into a self-aligned line, the parasitic series resistance can be reduced and the device speed can be increased. In particular, since the lift-off material layer for wiring formation is also used as a mask for ion implantation, the process is relatively simple.
以上この発明者によってなさ汎だ発明を実施例に基づき
具体的に説明したが、この発明はそれに限定されるもの
ではなく、その要旨を逸脱しない範囲で種々変更可能で
あることはいうまでもない。Although the general invention made by this inventor has been specifically explained based on examples, it goes without saying that this invention is not limited thereto and can be modified in various ways without departing from the gist thereof. .
たとえば、ゲート材料としてはタングステンまたはタン
グステンシリサイド等を用いてもよい。また、Ｎ型不純
物としてイオン打込みするものはシリコン以外のものを
用いてもよい。For example, tungsten, tungsten silicide, or the like may be used as the gate material. Furthermore, the N-type impurity to be ion-implanted may be other than silicon.
［利用分野］
この発明は、Ｇ ａ Ａ ｓデバイスに限らずＭＥＳＦ
ＥＴのセルファライン技術とし−Ｃ広範に利用すること
ができる。なお、この発明ば〜１０ｓＦＥＴへの適用も
可能である。[Field of Application] This invention is applicable not only to GaAs devices but also to MESF devices.
ET's self-line technology can be widely used. Note that this invention can also be applied to a 10s FET.
第１図〜第５図はこの発明の一実施例をコニ程順に示す
断面図である。
１・・・絶縁基板、２・・・半導体層、 ３・・・リフ
トオフ材料層、４・・・ひさし構造、５・・・グー１〜
用金属材料、５１・・・グー１〜金属膜、６・・・パシ
ベーション膜、７・・・穴、８１・・・ソース電極、８
２・・・ドレイン電極。
代理人 弁理士 高 橋 明 夫
４３５
第 １ 図
３
第 ２ 図
第 ３１４
第 ４ 図
ｚ
第５図FIGS. 1 to 5 are cross-sectional views showing one embodiment of the present invention in order of height. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Semiconductor layer, 3... Lift-off material layer, 4... Eaves structure, 5... Goo 1~
metal material for use, 51... goo 1 to metal film, 6... passivation film, 7... hole, 81... source electrode, 8
2...Drain electrode. Agent Patent Attorney Akio Takahashi 435 Figure 1 Figure 3 Figure 2 Figure 314 Figure 4 z Figure 5
Claims (1)
製造方法。 （Ａ）絶縁基板の一面に形成された半導体層の表面上、
ゲー１−を、形成ずべき部分以外をリフトオフ材料層で
被う工程。 （Ｂ）イオン打込みによる打込み深さの差を利用するこ
とによって、前記リフトオフ材料層下の半導体層の部分
を高濃度領域、ゲー１〜を形成すべき部分の半導体層の
部分を低濃度領域とそれぞれなす工程。 （Ｃ）（Ｂ）工程後、グー１−用金属材料の堆積および
前記リフ１〜オフ材料層を用いたリフ１〜オフ処理によ
って、前記低濃度領域の部分にのみゲート用金属材料を
残す工程。 （Ｄ）（Ｃ）工程で部分的に残したグー１−用金属材料
をグー１−金属膜、その両側に位置する前記高濃度領域
の各部分をソースＪ′？よびトレーｒンどして電極およ
び配線を形成する工程。 ２、前記リフトオフ材料層は、」二下二層膜からなり、
上層の膜が下層の膜のサイドエッチ処理に対するマスク
となりうる特許請求の範囲第１項に記載のショットキゲ
ート型ＦＥＴの製造方法。[Claims] 1. A method for manufacturing a Schottky gate FET, comprising the following steps. (A) On the surface of the semiconductor layer formed on one surface of the insulating substrate,
A process of covering the gate 1- with a layer of lift-off material except for the areas to be formed. (B) By utilizing the difference in implantation depth due to ion implantation, the portion of the semiconductor layer under the lift-off material layer is made into a high concentration region, and the portion of the semiconductor layer where the gates 1~ are to be formed is made into a low concentration region. Each process. (C) After the step (B), a step of leaving the gate metal material only in the low concentration region by depositing the goo 1 metal material and performing a riff 1 off process using the riff 1 off material layer. . (D) The Goo 1 metal material partially left in the step (C) is used as the Goo 1 metal film, and each part of the high concentration region located on both sides thereof is used as the source J'? and a process of forming electrodes and wiring. 2. The lift-off material layer is composed of "two lower two-layer films,"
2. The method of manufacturing a Schottky gate FET according to claim 1, wherein the upper layer film can serve as a mask for side etching of the lower layer film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14632083A JPS6038883A (en) | 1983-08-12 | 1983-08-12 | Manufacture of schottky gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14632083A JPS6038883A (en) | 1983-08-12 | 1983-08-12 | Manufacture of schottky gate type field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6038883A true JPS6038883A (en) | 1985-02-28 |
| JPH0439773B2 JPH0439773B2 (en) | 1992-06-30 |
Family
ID=15404998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14632083A Granted JPS6038883A (en) | 1983-08-12 | 1983-08-12 | Manufacture of schottky gate type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6038883A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6337701A (en) * | 1986-07-31 | 1988-02-18 | Nippon Dengiyou Kosaku Kk | Composite band stop filter |
| WO2007072247A2 (en) * | 2005-12-22 | 2007-06-28 | Koninklijke Philips Electronics N.V. | An improved lift-off technique suitable for nanometer-scale patterning of metal layers |
-
1983
- 1983-08-12 JP JP14632083A patent/JPS6038883A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6337701A (en) * | 1986-07-31 | 1988-02-18 | Nippon Dengiyou Kosaku Kk | Composite band stop filter |
| WO2007072247A2 (en) * | 2005-12-22 | 2007-06-28 | Koninklijke Philips Electronics N.V. | An improved lift-off technique suitable for nanometer-scale patterning of metal layers |
| WO2007072247A3 (en) * | 2005-12-22 | 2007-10-25 | Koninkl Philips Electronics Nv | An improved lift-off technique suitable for nanometer-scale patterning of metal layers |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0439773B2 (en) | 1992-06-30 |
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