JPS6077469A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6077469A JPS6077469A JP18542383A JP18542383A JPS6077469A JP S6077469 A JPS6077469 A JP S6077469A JP 18542383 A JP18542383 A JP 18542383A JP 18542383 A JP18542383 A JP 18542383A JP S6077469 A JPS6077469 A JP S6077469A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- source
- metal film
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 15
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PUUOOWSPWTVMDS-UHFFFAOYSA-N difluorosilane Chemical compound F[SiH2]F PUUOOWSPWTVMDS-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、くわしくは、電界効果
トランジスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a field effect transistor.
シリコン（以下、８ｉと略す）を用いた乗積回路（以下
、ＩＣと略す）より高速な装置として、ガリウム砒素（
以下、（ＪＢＡｓと略す）を用いたＩＣが注目され、各
所で開発が進められている。ＧａＡｓ ＩＣが８ｉＩＣ
に比べて高速である理由は、ＧａＡｓ ＩＣが半絶縁性
ＧａＡｓ ″−基板上に
ヤ晟しうるため、紫子分離が容易なため、より高密度に
集積化でき配線答斎が低減されると共に単位長さ当りの
配線容蛍が低減されうろことと、ＧａＡｓ中の電流のキ
ャリアである電子の移動度が、Ｓｉのそれに比べ１３〜
５倍大きいため、に畜生抵抗が低減しうろこととによる
。さらにＧａＡｓ ＩＣを高速化させるためには、Ｇａ
Ａｓ ＩＣの基本素子である電界効果トランジスタ（以
下、ＦＥＴと略す）のカットオフ周波数（以下、ｆＴと
略す）を上げる必要がある。セしてＦＥＴのｆ 、、、
の向上は、寄生ヨ１（抗をより低減することにより相互
コンダクタンス（以下、ｇ□と略す）を高くすることと
ゲート畏ヲ短縮してゲートとノース間容量（以下、（４
，と略す）を低（することが必要である。ＦＥｉ”の寄
生抵抗すなわち、ソースとゲート間抵抗（以下、Ｒｓと
略す）を低減するためＫは、ソースとゲート間に高キャ
リアａＷＷ＊導入するか、ソースとゲート間距離を短縮
する必要がある。しかＩ２、一般にイオン注入法により
形成される高キャリア濃度層の導入においては、注入さ
れた不純物がポストイオン注入アニール時に、横方向に
拡散し、ゲート下のチャネル層中のキャリヤ濃度を高め
るため、初期に設計したＦＥＴのスレッショルド電圧（
以下、ＶＴ と略す）を変化させると共にゲート電極に
高キャリア濃度層が接触するためゲ−ト１嗣圧が劣化す
る等のいわゆるショートチャネル効果を招来する。一方
ソースとゲート間の距離を短縮することによりＲｓ を
低減する方法は、前記のショートチャネル効果を招くこ
とはないが、Ｃｐｓを低減させるためにＦｆｆＴのゲー
ト長（以下、Ｉ９ と略す）を短縮しようとする場合に
は、自己整合法でＦ Ｅ Ｔを形成する必要が生じる。Gallium arsenide (hereinafter referred to as 8i) is a faster device than multiplication circuit (hereinafter referred to as IC) using silicon (hereinafter referred to as 8i).
ICs using JBAs (hereinafter abbreviated as JBAs) have attracted attention and are being developed in various places. GaAs IC is 8iIC
The reason why GaAs IC is faster than that is because it can be formed on a semi-insulating GaAs'' substrate, which makes it easier to separate the semiconductors, which allows for higher density integration and reduced wiring costs. The wiring capacity per unit length is reduced, and the mobility of electrons, which are current carriers, in GaAs is 13~13% higher than that of Si.
Because it is 5 times larger, the resistance to the beast is reduced due to the scales. In order to further speed up GaAs IC, GaAs
It is necessary to increase the cutoff frequency (hereinafter abbreviated as fT) of a field effect transistor (hereinafter abbreviated as FET), which is a basic element of As IC. f of the FET,...
The improvement of the parasitic resistance can be achieved by increasing the mutual conductance (hereinafter referred to as g
In order to reduce the parasitic resistance of FEi'', that is, the resistance between the source and gate (hereinafter abbreviated as Rs), K is a high carrier aWW* introduced between the source and gate. However, when introducing a high carrier concentration layer that is generally formed by ion implantation, the implanted impurity diffuses laterally during post-ion implantation annealing. In order to increase the carrier concentration in the channel layer under the gate, the threshold voltage (
In addition to changing the high carrier concentration layer (hereinafter abbreviated as VT), the contact of the high carrier concentration layer with the gate electrode causes a so-called short channel effect such as deterioration of the gate voltage. On the other hand, the method of reducing Rs by shortening the distance between the source and gate does not cause the above-mentioned short channel effect, but the gate length of FffT (hereinafter abbreviated as I9) is shortened in order to reduce Cps. In this case, it becomes necessary to form FET using a self-alignment method.
この自己整合法においては、ソースとゲート量比ｔＡ＆
Ｌｒ５ａとゲートとドレイン間距離ＬＧＤとが同じ値に
なり、ソースとゲート間距離ＬＳＧを短縮してＲｓを低
減させようとすると、ゲートとドレイン間距離ＬＧＤも
小さくなるため、ゲートとドレイン間の逆方向耐圧（以
下、ｈｉＶｏｎと配す）が低下し、ゲートとドレイ／間
に掛ゆられる電圧を低（しなければならず。In this self-alignment method, the source and gate amount ratio tA&
Lr5a and the distance between the gate and drain LGD become the same value, and if you try to reduce Rs by shortening the distance between the source and gate LSG, the distance between the gate and drain LGD will also become smaller. The directional breakdown voltage (hereinafter referred to as hiVon) decreases, and the voltage applied between the gate and the drain must be reduced.
ＦＥＴの特性を十分に引き出ぜないことＫなる。This results in not being able to fully bring out the characteristics of the FET.
自己整合法により形成されたＧａＡｓ ＦＥＴを第１図
に示す。第１図において、ｌは半絶縁性ＧａＡ。FIG. 1 shows a GaAs FET formed by the self-alignment method. In FIG. 1, l is semi-insulating GaA.
也３はソース、４はゲート、５はドレインである。3 is a source, 4 is a gate, and 5 is a drain.
本発明はかかる欠点を除去し、ソースとゲート量比１ｍ
Ｌｓ Ｇ：：ｘ ｔｍ＋桶しでＲＢを低減するととも
に、ゲートとトンーｒン聞距離１１＋１１１はソースと
ゲート量比ｔｌＬｓｏよりも大きくしてゲートとドレイ
ン間によ− ・ “り高いぼ
圧が掛けられるようにすることにより、より高い性能を
示すＦｇＴの製造方法を提供しようとするものである。The present invention eliminates such drawbacks and achieves a source and gate amount ratio of 1m.
Ls G: : The present invention aims to provide a method for manufacturing FgT that exhibits higher performance.
本発明の！′ｆｆ畝は、高抵抗基板上に導電層を形成す
る工程と、該導電層−ヒに該導′Ｉｔ層と７コツトキ接
合を形成しうる第１の金属膜を被着する工程と、第１の
金属膜上の少くともゲートが位置し５る領域に第１の金
属膜を保護しうる・物質膜を被着する工程と、前記の物
質膜をマスクとしてマスクされた領域の第１の金属膜を
除去すると共Ｋ、さらにマスクとし℃用いた前記の物質
膜の下の一部の第１の金属膜を除去する工程と、前記の
導電層とオーム性接触をしうる第２の金属膜な被着する
工程と、前記の物質膜な除去する工程と、残された第１
の金Ｍ４膜のゲートとなる領域のうち少くともソースに
近い領域上には仮着されないように第１０金栖膜を保護
しうる物質膜を被着する工程と、前記物質膜をマスクと
して少くとも露出されている第１の金属膜を除去する工
程とを含む半導体装置の製造方法にある。The invention! The 'ff ridges are formed by forming a conductive layer on a high-resistance substrate, depositing a first metal film capable of forming a 7-point junction with the conductive It layer on the conductive layer, and a step of depositing a material film capable of protecting the first metal film on at least a region where the gate is located on the first metal film; At the same time as removing the metal film, a step of removing a part of the first metal film under the material film used as a mask at °C, and a second metal film capable of making ohmic contact with the conductive layer is performed. A step of depositing a film, a step of removing the above-mentioned material film, and a step of removing the remaining first material film.
A step of depositing a material film capable of protecting the tenth gold M4 film from being temporarily deposited on at least a region close to the source of the region that will become the gate of the gold M4 film, and a step of depositing a material film capable of protecting the tenth gold film from being temporarily deposited, and using the material film as a mask to deposit a material film on at least a region close to the source. The method of manufacturing a semiconductor device includes a step of removing both the exposed first metal film and the exposed first metal film.
次に本発明を実ｉｊ＊ｕ ５１Ｊな用いて説明する。第
２図は本発明の一実施例を示す。第２図ｔａ＋において
、半絶縁性Ｇ ａ Ａ ｓ基板１１上ＫＩＩＦＩえばキ
ャリア濃度が１． Ｘ １０１′ｙｃ、ｑｒ−”である
ｎ型０ａＡｓ ＩＱ １２を例えば０，１３μｍの厚さ
に形成した後、ｎＭＧａＡｓ層とシ曹ットキバリア接曾
を形成するｌ第１の金属膜１６例えばアルミニウム（以
下、ＡＪと略す）を、例えば０．５μｍの長さに被着す
る。さらに写Ｘ食刻法を用いてＡＩ膜１６上に、Ａｌ膜
１６を保護する物質膜１７として、例えばホトレジスト
を例えば長さ３μｍｎにわたり被着する。次に、第２Ｆ
ｌ（ｂ） Ｋ示すように保−物質膜１７の下のう１↓１
の金箔膜１６以外の第１の金属膜１６をシ１ｊえばリン
酸液によりエツチング除去した後、さらに保長物ｊ（膜
１７下の第１の金属膜１６の一部をオーバーエツチング
することにより保護物質膜１７であるホトレジストのオ
ーバーハングを０．５μｍだけ形成する。Next, the present invention will be explained using an actual ij*u 51J. FIG. 2 shows an embodiment of the invention. In FIG. 2 ta+, if KIIFI is on the semi-insulating GaAs substrate 11, the carrier concentration is 1. After forming an n-type 0aAs IQ 12 with a thickness of, for example, 0.13 μm, which is 101'yc,qr-'', a first metal film 16, such as aluminum (hereinafter referred to as . The second F is deposited over a thickness of 3 μm.
l(b) As shown in K, the bottom 1↓1 of the preservation material film 17
After removing the first metal film 16 other than the gold foil film 16 by etching with a phosphoric acid solution, a part of the first metal film 16 under the film 17 is further protected by over-etching. An overhang of photoresist, which is the material film 17, is formed by 0.5 μm.
次に１第２図（Ｃ）に示すように、” ｍＧａＡｓ層１
２とオーム性接触をなしうる第２の金！膜１Ｂとして、
例えば金ゲルマニウム合金次いでニッケル（Ａｕ０ｅ
Ｎｉと略す）をｎｍＧａＡ、１２上および保護物質膜１
７であるホトレジスト上に被着する。次に、第２図（ｄ
） Ｋ示すよう尾、前記のホトレジス）、４１Ｑをその
溶剤により除去すると同時Ｋ、ホトレジス）４１７ｆ上
に被着された第２の金属膜１８を除去する。いわゆるリ
フトオフ法によりソースおよびドレインとなる第２の金
属膜１８のみを残す。ここまでの製造工程により、第１
の金属１６をゲートとし、第２の金属膜１８をソースお
よびドレインとし、ＬＳＧ＝０．５μ飢、ＬＧＤ ＝
０．５μｍ１およびゲート長（Ｌｙと略す）＝２μｍの
ＦＥＴが形成される。ここで、第２図（ｄ）よりわかる
ようＫ、ゲートとドレイン間の距離ＬＧＤがせまいため
に、ＢＶＧＤは約５ＶＬかなく、一般に、かかるＦｇＴ
におい℃は、ドレイン電圧は３■程度しか掛けられない
ため例えばゲート幅３００μｍ程度の素子では、その飽
和出力は１０ｄＢｍ程度である。Next, as shown in FIG. 2(C), the mGaAs layer 1
The second gold that can make ohmic contact with 2! As membrane 1B,
For example, gold-germanium alloy, followed by nickel (Au0e)
abbreviated as Ni) on nmGaA, 12 and a protective material film 1
7 on the photoresist. Next, Figure 2 (d
) As shown in FIG. 1, the second metal film 18 deposited on the photoresist 417f is removed at the same time as the photoresist 41Q is removed using the solvent. A so-called lift-off method is used to leave only the second metal film 18 that will become the source and drain. Through the manufacturing process up to this point, the first
The second metal film 18 is used as the gate, the second metal film 18 is used as the source and drain, LSG = 0.5μ, LGD =
An FET of 0.5 μm1 and gate length (abbreviated as Ly)=2 μm is formed. Here, as can be seen from FIG. 2(d), since the distance LGD between the gate and the drain is small, BVGD is only about 5VL, and generally such FgT
Since the drain voltage can only be applied at a temperature of about 3.degree. C., a device with a gate width of about 300 .mu.m, for example, has a saturated output of about 10 dBm.
従ってさらに出力を増すためには、ＢｖＧＤを高くし、
ドレイン電圧を３ｖ以上にする必要がある。Therefore, in order to further increase the output, increase BvGD,
It is necessary to set the drain voltage to 3V or higher.
本発明はゲート・ドレイン間距離ＬＧＩ）をより広くす
ると共Ｋ、ゲート長をさらに短縮し、ＦＢＴの性能を向
上するものである。次に１２図ｆｅ）に示すように、写
真食刻法を用いて、少くともゲートとなる第１の金属層
１６のソースに近い領域を覆い、ドレインに近い領域を
露出させた状態に、第１の金属膜を保護する物質膜１９
、例えば前記のホトレジストと同種のものか否かは問わ
ず、ホトレジストを被着する。次に、第２図（ｆ）に示
すように、第１の金属膜を例えばリン酸液を用いて保護
物質膜１９の下の第１の金属膜であるＡ［が残るように
第１の金属膜、例えばＡｌをエツチング除去し、その後
、保護物質膜１９を溶剤で除去する。ここでＬｓｏ＝０
．５μｍ、 Ｌｙ＝１．０μｍ１ＬＧＤ＝１．５μｍの
ＦＥＴが形成される。かかる）’ １３ Ｔではソース
とゲート間の距１ｍｔＬｓｏが小さいためｎｓが低減さ
れていると共に１ゲートとドレイン間の距離Ｌｏｐが長
いため、ＢＶＧＤが高くなり、ドレイン電圧がより高く
かけられるため、従来法のものに比べてより尚利得・高
出力を得ることができる。また、本方法は本負的にセル
フアライメントであるため、特性の均一性も従来法に比
べて劣ることはない。The present invention further widens the gate-drain distance (LGI), further shortens the gate length, and improves the performance of the FBT. Next, as shown in Fig. 12 (fe), a photolithographic method is used to cover at least the region of the first metal layer 16 that will become the gate near the source, and expose the region near the drain. Material film 19 that protects the metal film 1
, for example, depositing a photoresist, whether or not of the same type as the photoresist described above. Next, as shown in FIG. 2(f), the first metal film is coated using, for example, a phosphoric acid solution, so that the first metal film A[] remains under the protective material film 19. The metal film, for example Al, is removed by etching, and then the protective material film 19 is removed using a solvent. Here Lso=0
．． A FET of 5 μm, Ly=1.0 μm, 1LGD=1.5 μm is formed. )'13 T, the distance 1mtLso between the source and the gate is small, so ns is reduced, and the distance Lop between the 1 gate and the drain is long, so the BVGD becomes high and the drain voltage is applied higher. Even more gain and higher output can be obtained compared to the conventional method. Furthermore, since this method is essentially self-alignment, the uniformity of characteristics is not inferior to conventional methods.
本実楕例では、第１の金属膜の除去にリン酸液で除去す
るいわゆるウェットエツチングを用いたが、ＡＪＫかわ
る他の金属、たとえばモリブデンやタングステンを使え
ばドライエツチングによりゲート形成することも可能で
ある。In this example, we used so-called wet etching to remove the first metal film using a phosphoric acid solution, but if you use other metals instead of AJK, such as molybdenum or tungsten, it is also possible to form the gate by dry etching. It is.
また、ＧａＡｓのかわりＫ、他の化合物半導体例えばＩ
？ＬＰや、例えば、サファイヤや２醗化シリコン上に半
導体膜を形成するいわゆる８０５ｒ４成の基板にも本発
明は適用しうる。Also, instead of GaAs, K, other compound semiconductors such as I
? The present invention can also be applied to a so-called 805r4 substrate in which a semiconductor film is formed on LP or, for example, sapphire or silicon difluoride.
第１図は従来法によるＦ’ Ｅ ′ｒの構造を示す断面
図、第２図（ａ）〜（ｆ）は本発明の一実施例による製
造方法を工程順に示す断面図である。
１・・・・・・尚抵抗Ｇ、ＡＳ基板、２・・・・・・ｎ
型ＧａＡｓ層、３・・・・・・ソース、４・・・・・・
ゲート、５・・・・・・ドレイン、１１・・・・・・半
絶縁性ＧａＡｓ基板、１２・・・・・・ｎ型ＧａＡｓ層
、１６・・・・・・第１の金属膜、１７．１９・・・・
・・第１の金属膜を保護する物質膜、１８・・・・・・
第２の金＆４膜。
８ｚ図FIG. 1 is a cross-sectional view showing the structure of F'E'r according to a conventional method, and FIGS. 2(a) to (f) are cross-sectional views showing the manufacturing method according to an embodiment of the present invention in the order of steps. 1...Resistance G, AS board, 2...n
Type GaAs layer, 3... Source, 4...
Gate, 5...Drain, 11...Semi-insulating GaAs substrate, 12...N-type GaAs layer, 16...First metal film, 17 .19...
...Material film that protects the first metal film, 18...
2nd gold & 4 membranes. 8z diagram
Claims (1)
層上に該導電層とショットキ接合を形成しうる第１０金
絹膜を被着する工程と、該第１の金属膜上の少くともゲ
ートが位置しうる領域に第１の金属膜を保護しうる物質
膜を被着する工程と、前記の物質膜をマスクとして、マ
スクされた領域の第１の金属膜を除去すると共忙、さら
忙マスクとして用いた前記の物質膜の下の一部の第１の
金属膜を除去する工程と、前記の導電層とオーム性接触
をしうる第２の金属膜を被着する工程と、前記の物質膜
を除去する工程と、残された第１の金属膜のゲートとな
る領域のうち少くともソースに近い領域を覆い、ドレイ
ンに近い領域上には被着されないように第１０金属膜を
保護しうる物質膜を被着する工程と、前記物質膜をマス
クとして、少くとも露出されていま第１の金、？Ａ 膜
を除去する工程とを含むことを／ｌ？徴とする半導体装
置の、４造方法。 ２、前記導電層は４電性半導体層であることを特徴とす
る特許請求の範囲外１項記載の半導体装置の製造方法。[Claims] 1. A step of forming an ε conductive layer on a high-resistance substrate, a step of depositing a No. 10 gold silk film capable of forming a Schottky junction with the conductive layer on the conductive layer, and a step of depositing a material film capable of protecting the first metal film on at least a region where a gate can be located on the first metal film; removing a portion of the first metal film under the material film used as a mask; and a second metal film capable of making ohmic contact with the conductive layer. a step of depositing the material film, a step of removing the above-mentioned material film, and a step of depositing the remaining first metal film to cover at least the region that will become the gate, covering at least the region close to the source, and depositing the material film on the region close to the drain. a step of depositing a material film capable of protecting the tenth metal film from being damaged; and using the material film as a mask, at least the first metal film is exposed. A /l? Four manufacturing methods for semiconductor devices. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is a tetraconductive semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18542383A JPS6077469A (en) | 1983-10-04 | 1983-10-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18542383A JPS6077469A (en) | 1983-10-04 | 1983-10-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6077469A true JPS6077469A (en) | 1985-05-02 |
Family
ID=16170526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18542383A Pending JPS6077469A (en) | 1983-10-04 | 1983-10-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6077469A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04275438A (en) * | 1991-03-04 | 1992-10-01 | Nec Corp | Field effect transistor |
-
1983
- 1983-10-04 JP JP18542383A patent/JPS6077469A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04275438A (en) * | 1991-03-04 | 1992-10-01 | Nec Corp | Field effect transistor |
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