JPH0831481B2 - Field effect transistor - Google Patents

Description

The present invention relates to a field effect transistor, and more particularly to a field effect transistor using a compound semiconductor suitable for operation in a high frequency band.

[Conventional technology]

Compound semiconductors are often used for ultra-high frequency devices due to their physical characteristics. Among them, the field-effect transistor (hereinafter referred to as FET) using GaAs, which is a III-V group binary compound semiconductor, has been remarkably developed. Moreover, it is shifting to IC.

A conventional GaAs-FET has a structure having a buffer layer 2 and a mesa-shaped operation layer 3 on a semi-insulating GaAs substrate 1, as shown in the sectional view of FIG. Then, in order to reduce the source resistance, a dug portion is provided in the operating layer 3, and a metal that forms a Schottky barrier, for example, a gate electrode 10 made of titanium 5 and aluminum 4 is formed in the dug portion.
In addition, the source electrode 20A and the drain electrode 20B made of a metal that makes ohmic contact with the operating layer 3, for example, an Au-Ge alloy and the Ni layer 8
Are formed. Further, the surface of the operating layer 3 is covered with the silicon nitride film 6.

[Problems to be solved by the invention]

In the conventional GaAs-FET described above, when the RF energization test is performed, the values of the saturation current I _DSS and the cutoff voltage V _P decrease,
There is a problem that the gain is reduced.

The reason for this is that the gate electrode is formed deeply and in the narrow dug portion, so that the silicon nitride film 6 as the passivation film is not normally formed on the side surface of the gate electrode 10 or the bottom of the dug portion, or the film is not formed. Since the thickness is much thinner than the flat part and pinholes are easily formed, the ionic gas released from the package during the RF current test may generate pinholes in the silicon nitride film. This is because it passes through and concentrates in the vicinity of the end of the gate electrode to change the shape of the surface depletion layer and cause characteristic variations.

An object of the present invention is to provide a field effect transistor whose characteristics do not change due to the influence of outside air.

[Means for solving problems]

The field effect transistor of the present invention is sandwiched between a source electrode and a drain electrode that make ohmic contact with a one-conductivity-type semiconductor operating layer formed on a semi-insulating semiconductor substrate, and the source electrode and the drain electrode. In a field effect transistor having a dug portion formed on the surface of the semiconductor operating layer, a gate electrode provided in the dug portion and in Schottky contact with the semiconductor operating layer, and a passivation film covering the semiconductor operating layer. The passivation film is formed of three layers of insulating films of a silicon nitride film, a silicon oxide film and a silicon nitride film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a sectional view of an embodiment of the present invention.

In FIG. 1, p-type Ga is placed on a semi-insulating GaAs substrate 1.
The buffer layer 2 made of As and the operating layer 3 made of n-type GaAs are formed in a mesa shape. An AuGe-Ni layer 8 which makes ohmic contact with the operating layer 3 is formed on the operating layer 3, and a source electrode 20A and a drain electrode 20B are formed on the AuGe-Ni layer 8.

Further, a gate electrode 10 made of titanium 5 and aluminum 4 is formed in the dug portion of the operating layer 3 and is in Schottky contact with the operating layer 3. Further, on the operation layer 3, a silicon nitride film 6A, a silicon oxide film 7 and a silicon nitride film 6B are formed.
The passivation film is formed of three layers of insulating films.

In this embodiment having such a structure, the passivation film is composed of three layers of insulating films, so that the semiconductor element is completely shielded from the outside air and is not affected thereby.

When a current-carrying test is performed on this embodiment, the conventional GaAs-FET
It is shown in FIG.

As shown in FIG. 4, in the conventional GaAs-FET, the saturation current was reduced by about 20% after 2000 hours, whereas in this example, almost no change was observed.

 Next, a manufacturing method of one embodiment of the present invention will be described.

2 (a) and 2 (b) are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 2 (a), after forming the buffer layer 2 and the operating layer 3 in a mesa shape on the semi-insulating GaAs substrate 1,
The gate electrode forming portion is etched to form the dug portion 30. Next, after depositing titanium 5 having a thickness of about 500Å and aluminum 4 having a thickness of 4500Å, the gate electrode 10 is formed by patterning. Next, the thickness of about 150
A 0Å silicon nitride film 6A is formed. Next, the silicon nitride film 6A on the source and drain forming portions is removed. continue
After AuGe alloy and Ni are vapor-deposited and patterned to form the AuGe-Ni layer 8, heat treatment is performed at about 420 ° C. Next, as shown in FIG. 2B, a silicon oxide film 7 having a thickness of about 1500 Å is formed on the entire surface by a CVD method, and then a silicon nitride film 6B having a thickness of about 1500 Å is formed by a plasma CVD method or a sputtering method. Form.

Next, after removing the silicon oxide film 7 and the silicon nitride film 6B on the AuGe-Ni layer 8, Ti, Pt, and Au are deposited by the sputtering method and patterned to form the source electrode 20A and the drain electrode 20B. The embodiment shown in FIG. 1 is completed.

〔The invention's effect〕

As described above, according to the present invention, by forming the passivation film by the three-layer insulating film of the silicon nitride film, the silicon oxide film, and the silicon nitride film, a field effect transistor whose characteristics do not change due to the influence of the outside air can be provided. It has the effect of being obtained.

[Brief description of drawings]

1 is a sectional view of an embodiment of the present invention, FIG. 2 (a),
(B) is a sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, FIG. 3 is a sectional view of an example of a conventional GaAs-FET, and FIG. 4 is an embodiment of the present invention. And conventional GaAs
FIG. 6 is a diagram showing a relationship between a conduction test time of a FET and a change rate of a saturation current. 1 ... GaAs substrate, 2 ... buffer layer, 3 ... operating layer, 4
... Aluminum, 5 ... Titanium, 6,6A, 6B ... Silicon nitride film, 7 ... Silicon oxide film, 8 ... AuGe-Ni layer,
10 ... Gate and electrode, 20A ... Source electrode, 20B ... Drain electrode.

Claims (1)

[Claims] 1. A semiconductor operating layer sandwiched between a source electrode and a drain electrode, which are in ohmic contact with a one conductivity type semiconductor operating layer formed on a semi-insulating semiconductor substrate, and sandwiched between the source electrode and the drain electrode. A field effect transistor having a dug portion formed on a surface, a gate electrode provided in the dug portion and in Schottky contact with the semiconductor operating layer, and a passivation film covering the semiconductor operating layer, wherein the passivation film is formed. Is a field-effect transistor characterized by being formed from three insulating films of a silicon nitride film, a silicon oxide film, and a silicon nitride film.