JPS61236166A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the effect of producing a coarse pattern, by providing a first insulation film on the side walls of a gate electrode provided on a first semiconductor active layer on a substrate, then forming a second insulation film on the periphery and in the vicinity of the first active layer, and then growth depositing a second semiconductor active layer. CONSTITUTION:A first semiconductor active layer 102 is formed on an insulating substrate 101 and then a gate electrode 103 is adhered thereon. A part of the gate electrode is etched so as to separate the active layer 102 into two regions so that one of the regions provides a source electrode region and the other provides a drain electrode region. An insulation film is formed and dry etched anisotropically so that an insulation film 106 is provided only on the side walls of the gate electrode 103. A second insulation film is adhered on the whole surface of the substrate and etched so that the insulation film 108 surrounds the active layer 102. Subsequently, a semiconductor active layer 107 is formed to cover the exposed insulating substrate 101 and the semiconductor active layer 102 and removed except its region surrounded by the insulation film 108. A source electrode 104 and a drain electrode 105 are then provided. An MES FET is thereby obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a Schittky junction gate field effect transistor and a semiconductor integrated circuit using the same as a component. be.

[Conventional technology]

Traditionally, Sittke junction gate field effect transistors (
In particular, an integrated circuit (hereinafter abbreviated as GaAsIC) that uses gallium arsenide (hereinafter abbreviated as GaAs) and has MES FET as one component.
In general, MES FETs as shown in Figure 2 are used.
structure is used. Semi-insulating GaAa substrate 201
A GaAs active layer 202 is provided on the GaAs active layer 2.
A gate electrode 203 is attached to 02 to form a Schottky barrier, and a first electrode 204 and a drain electrode 2 are attached on both sides of the gate electrode 203 to form a Schottky barrier.
05 was ohmically attached to the GaAs active layer 202.

In order to improve the performance of such a MES FET structure, it is necessary to connect the source electrode 204 from the end of the gate electrode 203.
GaAs active layer 2 below and below the drain electrode 205
The thickness of 02 and its carrier concentration are increased to reduce parasitic resistance. However, such MES F
In the structure of ET, when the gate length is shortened and the performance is further improved, the semi-insulating substrate 201 under the gate electrode 203 is
There is a limit to the shortening of the gate length due to the short channel effect caused by the current flowing through the gate. Generally, the limit for reducing the gate length of the MES FET shown in Figure 2 is approximately 2.0.
μm, and at that time, the mutual conductance (hereinafter abbreviated as “J”), which is an index of MES FET performance, is approximately 70 m5.
/mm.

The short channel effect of the MES FET shown in FIG. 2 is due to the fact that the thickness of the GaAs active layer 202 from the edge of the gate electrode 203 to below the source electrode 204 and below the drain electrode 205 is thicker than the thickness of the channel layer below the gate electrode 203. As a measure to alleviate the short channel effect, as shown in Fig. 3, Ga
MES F manufactured by additionally forming an As active layer 307
The structure of ET is considered. Figure 3 shows the structure of a MES FET for suppressing short channel effects, and Figure 3 (A
) is the plan view, and Fig. 3 (B) is the x-x of Fig. 3 (A).
A cross-sectional view taken along the ' line is shown. Semi-insulating GaAs substrate 30
A first GaAs active layer 302 is provided in the surface area of 1, a gate electrode 303 is attached to the first GaAs active layer 302 to form a Schottky barrier, and a source electrode 304 and a drain electrode 305 are provided on both sides of the gate electrode 303. It is being An insulating film 306 is provided on the side surface of the gate electrode 303, and a second G is provided below the source and drain electrodes 304 and 305.
First GaAs active layer 30 via aAs active layer 307
Connected to 2.

In the MES FET structure shown in FIG. 3, the short channel effect does not occur until the gate length is 0.5 μm, and the MES
The performance of S FET can be significantly improved. For example, the third
In the MES FET shown in the figure, the gate length is approximately 130 m5/mm at a gate length of 0.5 μm.The method for realizing the MET FET structure shown in Fig. 3 is as follows.
From the viewpoint of forming the second GaAs active layer 307, it can be roughly divided into two types. The first method is to form the second GaAs active layer 307 on the entire surface of the GaAs substrate 301 after forming the gate electrode 303 and the sidewall insulating film 306, and then to form the second GaAs active layer 307 on the entire surface of the GaAs substrate 301, leaving only the necessary areas. This is a method of etching away. There are wet etching and dry etching methods for etching removal, but the latter method does not allow a high selectivity between GaAa and gate electrode metal, so wet etching is often used. In the structure shown in FIG. 3, in the vicinity of the sidewall of the second GaAs active layer 307 in contact with the insulating film 306, the crystallinity is poor and the crystal density is coarse. When removing the second GaAs active layer 307 by wet etching, the etching speed of the second GaAs active layer 307 in the vicinity of the insulating film 306 on the sidewall is fast. There was a drawback that the liquid entered along the side wall insulating film 306 and etched even the first GaAs active layer 302.

On the other hand, the second method attempts to selectively form the second GaAs active layer 307, for example, by using an insulating film such as a silicon oxide film, excluding the region where the second GaAs active layer 307 is to be formed. Then, a second GaAs active layer 307 is formed by covering the GaAa substrate 301, for example, by a metal organic thermal decomposition method (hereinafter abbreviated as MOCVD method). However, in this method, the second GaAs active layer 3
Depending on the size and arrangement of the area where 07 is to be formed, the second G
Not only does the thickness of the aAs active layer 307 vary from region to region, but it also has the disadvantage of causing so-called pattern density effect or layout effect, in which GaAa polycrystals grow on the gate electrode 303 or on the insulating film used as a mask. . This pattern density effect is caused by the second GaAs active layer 307.
It does not appear when the total formation area of is large.

[Problem that the invention seeks to solve]

Therefore, the conventional GaAs MES shown in FIG.
In the FET manufacturing method, the first method involves forming the second GaAs active layer 307 on the entire surface of the GaAs substrate 301 and then removing it by etching. The second GaAs active layer 307 is formed only in the necessary regions because of the poor crystallinity of the GaAs 307.
The second method, which uses a so-called selective growth method, has the disadvantage that it cannot be applied to GaAa integrated circuits due to the pattern density effect.

[Means for solving problems]

According to the present invention, the steps include forming a first semiconductor active layer on an insulating substrate or a semiconductor substrate, forming a gate electrode on the first semiconductor active layer, and at least forming a gate electrode on the first semiconductor active layer. A process of depositing a first insulating film so as to cover the insulating substrate or semiconductor substrate and the first semiconductor active layer in the vicinity, and etching the first insulating film only on the sidewalls of the gate electrode using an anisotropic etching technique. a step of removing the second insulating film so that it remains; and a step of depositing a second insulating film, leaving the second insulating film only around and in the vicinity of the region of the first semiconductor active layer, and forming the second insulating film on the insulating substrate or the semiconductor substrate. A step of removing the first semiconductor active layer so as to expose most of the region, a step of forming a second semiconductor active layer by vapor phase epitaxy, and a step of forming a second semiconductor active layer in which a source electrode and a drain electrode are to be formed. a step of masking the second semiconductor active layer region, the other necessary second semiconductor active layer region, and at least a part of the second insulating film, and removing the second semiconductor active layer outside the mask; and forming a source electrode and a drain electrode on a second semiconductor active layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and in FIG.
-1), (B-1), (C-1),...
... is a plan view, (A-2), (B-2), (
C-2), . . . A sectional view taken along line A-A′ of each plan view is shown. In FIGS. 1(A-1) and (A-2), n-type GaAa is implanted into an insulating substrate 101 made of 90Ag doped with chromium, for example, by implanting silicon, for example, by an ion implantation method. A first semiconductor active layer 102 is formed. Here, when silicon is used as the semiconductor substrate, it is necessary to use a semiconductor substrate exhibiting a conduction plate opposite to the first semiconductor active layer 102. Furthermore, the gist of the present invention will not be impaired even if other methods such as vapor phase growth are used to form the first semiconductor active layer. Next, as shown in FIGS. 1(B-1) and 1(B-2), after depositing tungsten, for example, as a gate electrode 103 on the insulating substrate 101 including the first semiconductor active layer 102, photolithography is performed. Using a cutting method, at least a portion of the gate electrode 103 is formed so as to divide the first semiconductor active layer region 102 into two. At this time, one side of the first semiconductor active layer region 102 becomes a source electrode region, and the other side becomes a drain electrode region. Next, Figure 1 (C-1), (
As shown in C-2), the gate electrode 103. First semiconductor active layer 102. After forming the first insulating film to cover the insulating substrate 101, anisotropic dry etching is performed to form the first insulating film 106 only on the side walls of the gate electrode 103. Next, Figure 1 (D-1), (D-2)
After depositing the second insulating film on the entire surface of the substrate, as shown in
A second insulating film 108 is formed by photolithography to surround the first semiconductor active layer region 102. If anisotropic dry etching is used when removing a part of the second insulating film by photolithography, the second insulating film will remain on the sidewalls of the first insulating film 106, but isotropic dry etching will The first semiconductor active layer 102 is etched using etching or wet etching.
The second insulating film can be removed without leaving any second insulating film on the sidewalls of the second insulating film 106 above. When using anisotropic dry etching, the first insulating film 106 and the second insulating film 108 may be of the same type. Here, most regions of the insulating substrate 101 and the first semiconductor active layer 102 are exposed. Next, as shown in FIGS. 1(E-1) and (E-2), when GaAs is grown by vapor phase epitaxy, such as pyrolysis using trimethyl gallium and trimethyl arsenic, the exposed insulation is removed. A second semiconductor active layer 107 is formed on the semiconductor substrate 101 and the first semiconductor active layer 102 . In this vapor phase growth, when impurities such as sulfur and sulfur are introduced, the second semiconductor active layer 307 becomes an n-type semiconductor active layer and exhibits a very small resistivity.

In addition, since the exposed areas of the insulating substrate 101 and the first semiconductor active layer 102 are very wide, the gate electrode 101
The second semiconductor active layer 107 can be formed with a uniform thickness in each region without forming polycrystalline GaAs on the second semiconductor active layer 107, and the pattern density effect does not appear. Next, as shown in FIGS. 1(F-1) and (F-2), after removing the second semiconductor active layer 107 formed in the area other than the area surrounded by the second insulating film 108. , a source electrode 104 and a drain electrode 105 are respectively formed on the second semiconductor active layer 107 formed on the first semiconductor active layer 102 which is the source and drain region, and the MES FET
Configure. Since there is no second semiconductor active layer 107 in the area other than the area surrounded by the second insulating film, wiring required when forming a GaAs integrated circuit can also be formed on the insulating substrate 101. Moreover, the second semiconductor active layer 10
7, a mask made of, for example, photoresist is formed on the second insulator 108, and during etching, the etching solution travels along the first insulating film 106, which is the side wall of the gate electrode 103, and removes the source and drain. The regions of the second semiconductor active layer 107 and the first semiconductor active layer 102 are not etched.

〔Effect of the invention〕

As explained above, the present invention reduces the parasitic resistance of the MESFET by forming an active layer with high carrier concentration and low resistivity in the source and drain regions of the MESFET by selective epitaxial growth using the vapor phase growth method. This manufacturing method is also suitable for integrated circuits because it can improve high performance and prevent the pattern density effect, which was a drawback of selective epitaxial growth.

In this manufacturing method, since the active layers in the source and drain regions are not formed deeper than the channel layer under the gate electrode, deterioration of characteristics due to the short channel effect can be prevented.

Furthermore, as can be easily inferred from the embodiments of the present invention, G
The present invention is not limited to aA@, and can be applied to other semiconductors such as silicon.

According to the embodiment of the present invention shown in FIG. 1, the limit for shortening the gate length without exhibiting the short channel effect is 0.5 μm maternary,
When sono, MES FET+7)gm is approximately 140m5/m
I got m.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention in the order of its manufacturing process, and (A-1), (B-1), (C
-1) (D-1), (E-1), (F-1) are plan views, (A-2), (B-2), (
C-2), (n-2), (E-2), (F
7-2) is shown in Figure 1 (A-1), (B-1), (
C-1), (D-1), (TiP-1), (F
-1) is a sectional view taken along line xx' in each figure. Second
The figure is a cross-sectional view of a semiconductor device using a conventional method, and FIG. 3 is used to explain the conventional technique. (A) is a plan view of the semiconductor device, and (B) is a line xx' of (A). FIG. 101... Insulating substrate, 102... First semiconductor active layer, 103, 203, 303...
・Gate electrode, 104.204,304...Source electrode, 105,205°305...Drain electrode, 106,306...First insulating film, 1
07... Second semiconductor active layer, 108...
...Second insulating film, 201,301...Semi-insulating GaAg substrate, 202-----GaAB active layer,
302-----First GaAs active layer, 307...
...Second GaAa active 1-0-5F2 Figure, 3rd UJ

Claims (1)

[Claims] a step of forming a first semiconductor active layer on an insulating substrate or a semiconductor substrate; a step of forming a gate electrode on the first semiconductor active layer; and a step of forming at least the gate electrode and the insulating substrate in the vicinity thereof. Alternatively, a step of depositing a first insulating film to cover the semiconductor substrate and the first semiconductor active layer, and a step of removing the first insulating film so that it remains only on the sidewalls of the gate electrode; a step of depositing a second insulating film, leaving the second insulating film only on the periphery of the first semiconductor active layer and its vicinity; a step of removing the second semiconductor active layer so as to expose most of the region between the layers, a step of forming a second semiconductor active layer by a vapor phase growth method, and a step of removing the source electrode and the drain electrode of the second semiconductor active layer. masking the region to be formed and at least a portion of the second insulating film;
removing the second semiconductor active layer outside the mask;
A method of manufacturing a semiconductor device, comprising the step of forming a source electrode and a drain electrode on the second semiconductor active layer.