JPH0439228B2 - - Google Patents
Info
- Publication number
- JPH0439228B2 JPH0439228B2 JP16027486A JP16027486A JPH0439228B2 JP H0439228 B2 JPH0439228 B2 JP H0439228B2 JP 16027486 A JP16027486 A JP 16027486A JP 16027486 A JP16027486 A JP 16027486A JP H0439228 B2 JPH0439228 B2 JP H0439228B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- metal film
- film
- forming
- pad electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 19
- 150000001875 compounds Chemical class 0.000 claims description 14
- 239000010410 layer Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000010931 gold Substances 0.000 description 22
- 238000000034 method Methods 0.000 description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Description
【発明の詳細な説明】
〔概要〕
本発明のボンデイングパツド電極の形成方法
は、化合物半導体基板に形成された不純物導電領
域の上に第１の金属膜を被着して該不純物導電領
域との間でオーミツクコンタクトを形成し、かつ
同時に該第１の金属膜を化合物半導体基板に直接
被着してボンデイングパツド用の第１の層を形成
する工程と、層間絶縁膜の上に第２の金属膜を被
着して配線用金属膜を形成し、かつ同時に該第２
の金属膜を前記第１の層の上にも直接被着してボ
ンデイングパツド用の第２の層を形成する工程と
を有することを特徴とする。第１の金属膜は化合
物半導体基板に対し極めて密着性が良好であるか
ら、ワイアボンデイングの際の化合物半導体基板
とのはがれの少ないボンデイングパツド電極を得
ることができる。またボンデイングパツド電極を
構成する第１の金属膜および第２の金属膜はそれ
ぞれ半導体デバイスの形成に用いられる金属膜を
用いて形成されるものだから、特別のボンデイン
グパツド電極の形成工程が不要となる。[Detailed Description of the Invention] [Summary] The method for forming a bonding pad electrode of the present invention includes depositing a first metal film on an impurity conductive region formed on a compound semiconductor substrate and forming a bonding pad electrode on the impurity conductive region. forming an ohmic contact between the bonding pads and at the same time directly depositing the first metal film on the compound semiconductor substrate to form a first layer for a bonding pad; 2 to form a wiring metal film, and at the same time deposit the second metal film.
The method further comprises the step of directly depositing a metal film on the first layer to form a second layer for a bonding pad. Since the first metal film has extremely good adhesion to the compound semiconductor substrate, it is possible to obtain a bonding pad electrode with little peeling from the compound semiconductor substrate during wire bonding. Furthermore, since the first metal film and the second metal film constituting the bonding pad electrode are each formed using metal films used for forming semiconductor devices, there is no need for a special process for forming the bonding pad electrode. becomes.
本発明はボンデイングパツド電極の形成方法に
関するものであり、更に詳しく言えば、化合物半
導体基板上に形成されるボンデイングパツド電極
の形成方法に関するものである。
The present invention relates to a method of forming a bonding pad electrode, and more specifically, to a method of forming a bonding pad electrode formed on a compound semiconductor substrate.
第２図は従来例の形成方法に係るボンデイング
パツド電極の断面図であり、１はGaAs基板（化
合物半導体）ある。また２はSiO2膜であり、３
はボンデイングパツド電極としてのAu系メタル
膜である。
FIG. 2 is a cross-sectional view of a bonding pad electrode according to a conventional forming method, and 1 is a GaAs substrate (compound semiconductor). Also, 2 is a SiO 2 film, and 3
is an Au-based metal film used as a bonding pad electrode.
このように、従来の形成方法によればSiO2膜
２（絶縁膜）の上にAu系メタル膜３を形成する。 In this way, according to the conventional formation method, the Au-based metal film 3 is formed on the SiO 2 film 2 (insulating film).
ところでSiO2膜２とAu系メタル膜３との密着
度はあまり良くないため、Auメタル膜３にワイ
ヤボンデイングするとき該Au系メタル膜３が
SiO2膜２からはがれるという問題点がある。
By the way, the degree of adhesion between the SiO 2 film 2 and the Au-based metal film 3 is not very good, so when wire bonding is performed to the Au-based metal film 3, the Au-based metal film 3
There is a problem that it peels off from the SiO 2 film 2.
本発明はかかる従来例の問題点に鑑みて創作さ
れたものであり、ワイヤボンデイングするときは
がれのないボンデイングパツド電極の形成方法の
提供を目的とする。 The present invention was created in view of the problems of the prior art, and aims to provide a method for forming a bonding pad electrode that does not peel off during wire bonding.
本発明のボンデイングパツド電極の形成方法
は、化合物半導体基板に形成された不純物導電領
域の上に第１の金属膜を被着して該不純物導電領
域との間でオーミツクコンタクトを形成し、かつ
同時に該第１の金属膜を化合物半導体基板に直接
被着してボンデイングパツド用の第１の層を形成
する工程と、層間絶縁膜の上に第２の金属膜を被
着して配線用金属膜を形成し、かつ同時に該第２
の金属膜を前記第１の層の上にも着接被着してボ
ンデイングパツド用の第２の層を形成する工程と
を有することを特徴とする。
The method for forming a bonding pad electrode of the present invention includes depositing a first metal film on an impurity conductive region formed on a compound semiconductor substrate to form an ohmic contact with the impurity conductive region; At the same time, the first metal film is directly deposited on the compound semiconductor substrate to form a first layer for a bonding pad, and the second metal film is deposited on the interlayer insulating film to form a wiring. forming a second metal film and simultaneously forming the second metal film.
and adhesively depositing a metal film on the first layer to form a second layer for a bonding pad.
不純物導電領域とオーミツクコンタクトを形成
する第１の金属膜は、化合物半導体基板に対して
も密着度の高いコンタクトを形成する。従つてワ
イヤボンデイングの際のはがれの少ないボンデイ
ングパツド電極を得ることができる。なお化合物
半導体基板は一般に絶縁性又は半絶縁性であるか
ら、該基板を通じて内部の半導体デバイスに電流
が流れ込むという不都合はない。
The first metal film forming an ohmic contact with the impurity conductive region also forms a highly adhesive contact with the compound semiconductor substrate. Therefore, a bonding pad electrode with less peeling during wire bonding can be obtained. Note that since the compound semiconductor substrate is generally insulating or semi-insulating, there is no problem of current flowing into the internal semiconductor device through the substrate.
またボンデイングパツド電極を構成する第１の
金属膜および第２の金属膜も内部半導体デバイス
を形成するときの金属膜は、用いるものであるか
ら、特別のボンデイングパツド電極形成用の工程
が不要である。 Furthermore, since the first metal film and the second metal film constituting the bonding pad electrode are those used when forming the internal semiconductor device, a special process for forming the bonding pad electrode is not required. It is.
次に図を参照しながら本発明の実施例について
説明する。第１図は本発明の実施例に係るボンデ
イングパツド電極の形成方法を説明する断面図で
ある。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view illustrating a method of forming a bonding pad electrode according to an embodiment of the present invention.
(1) 第１図ａにおいて、４はGaAs基板であり、
半絶縁性（例えば107〜108Ω・cm）の化合物半
導体基板である。５はFETのチヤンネル層を
形成するｎ型GaAs領域５であり、６はFETの
ソース・ドレインとしての高濃度ｎ型GaAs領
域である。また７はFETのゲート電極として
のWSi膜であり、ｎ型GaAs領域５に対してシ
ヨツトキーバリア電極を形成している。ここま
での製造工程は公知の方法により行われる。(1) In Figure 1a, 4 is a GaAs substrate,
It is a semi-insulating (for example, 10 7 to 10 8 Ω·cm) compound semiconductor substrate. 5 is an n-type GaAs region 5 forming the channel layer of the FET, and 6 is a highly doped n-type GaAs region as the source and drain of the FET. Further, 7 is a WSi film as a gate electrode of the FET, and forms a Schottky barrier electrode for the n-type GaAs region 5. The manufacturing steps up to this point are performed by known methods.
次に約4000ÅのAuGe−Au膜８をソース・
ドレイン領域及びボンデイングパツド電極にリ
フトオフ法で形成する。これによりFET側で
はソース・ドレイン電極が形成されるととも
に、ボンデイングパツド側ではボンデイングパ
ツドを構成する第１層目の金属膜が形成され
る。次いでアロイ処理を施すと、FET側では
AuGe−Au膜８と高濃度ｎ型GaAs領域６との
間でオーミツクなコンタクトが形成されるとと
もに、ボンデイングパツド側ではAuGe−Au
膜８とGaAs基板４とがアロイ化して密着性の
極めて強いコンタクトが形成される。 Next, a AuGe-Au film 8 of approximately 4000 Å is applied as a source.
It is formed on the drain region and bonding pad electrode by a lift-off method. As a result, source/drain electrodes are formed on the FET side, and a first layer metal film constituting the bonding pad is formed on the bonding pad side. Next, when alloy processing is applied, on the FET side,
An ohmic contact is formed between the AuGe-Au film 8 and the high concentration n-type GaAs region 6, and the AuGe-Au film 8 is formed on the bonding pad side.
The film 8 and the GaAs substrate 4 are alloyed to form a highly adhesive contact.
(2) 次に第１図ｂに示すように、全面に層間絶縁
膜としてのSiO2膜９を形成した後、パターニ
ングして開口部１０，１１を形成する。(2) Next, as shown in FIG. 1b, after forming a SiO 2 film 9 as an interlayer insulating film over the entire surface, openings 10 and 11 are formed by patterning.
(3) 次いで第１図ｃに示すように、約1000Åの
WSi又はTiN膜１２を全面に形成し、さらにそ
の上に約1000ÅのAu又はTi／Pt／Au蒸着膜１
３を形成する。WSi又はTiN膜１２はGaの拡
散防止のためのバリア膜としての機能を有し、
Au又はTi／Pt／Au蒸着膜１３は金メツキ膜形
成工程における電極の機能を有する。(3) Next, as shown in Figure 1c, about 1000 Å
A WSi or TiN film 12 is formed on the entire surface, and then an Au or Ti/Pt/Au vapor-deposited film 1 of about 1000 Å is further formed on the WSi or TiN film 12.
form 3. The WSi or TiN film 12 has a function as a barrier film to prevent Ga diffusion,
The Au or Ti/Pt/Au vapor deposited film 13 has the function of an electrode in the gold plating film forming process.
(4) 次に第１図ｄに示すように、Au蒸着膜１３
上に第２層目の配線パターンを形成した後、約
1μのAuメツキ膜を構成する。その後配線以外
の部分のAu又はWSiを除去する。これにより
FET側では所定の電極配線を形成することが
できるとともに、ボンデイングパツド側では所
定のボンデイングパツド電極を形成することが
できる。(4) Next, as shown in FIG. 1d, the Au vapor deposited film 13
After forming the second layer wiring pattern on top, approx.
Constitutes a 1μ Au plating film. After that, remove Au or WSi from areas other than the wiring. This results in
A predetermined electrode wiring can be formed on the FET side, and a predetermined bonding pad electrode can be formed on the bonding pad side.
以上説明したように、本発明の実施例によれば
ボンデイングパツド電極の第１層目の金属膜
（AuGe−Au膜８）がGaAs基板４に強度の密着
度をもつてコンタクトしているので、従来の問題
点であるワイヤボンデイングする際のボンデイン
グパツド電極のはがれを有効に防止することが可
能となる。 As explained above, according to the embodiment of the present invention, the first layer metal film (AuGe-Au film 8) of the bonding pad electrode is in contact with the GaAs substrate 4 with strong adhesion. This makes it possible to effectively prevent the bonding pad electrode from peeling off during wire bonding, which is a conventional problem.
またボンデイングパツド電極を形成する場合の
各金属膜は内部の半導体デバイスを形成するとき
のものを用いているので、ボンデイングパツド電
極形成用の特別の工程を必要としない。 Furthermore, since the metal films used to form the bonding pad electrodes are those used to form internal semiconductor devices, no special process for forming the bonding pad electrodes is required.
以上説明したように、本発明によればボンデイ
ングパツド電極の第１層目の金属膜は化合物半導
体基板に対し極めて密着性良くコンタクトしてい
るので、ワイヤボンデイングする際のはがれのな
い信頼性の高いボンデイングパツド電極を形成す
ることができる。またボンデイングパツド電極を
構成する第１の金属膜および第２の金属膜はいず
れも半導体デバイスの形成のときに用いられる金
属膜を使用するものだから、工程も簡単となる。
As explained above, according to the present invention, the first layer metal film of the bonding pad electrode is in contact with the compound semiconductor substrate with extremely good adhesion, so that reliability without peeling can be achieved during wire bonding. A high bonding pad electrode can be formed. Furthermore, since the first metal film and the second metal film constituting the bonding pad electrode are both metal films used in the formation of semiconductor devices, the process is simplified.
第１図は本発明の実施例に係るボンデイングパ
ツド電極の形成方法を説明する断面図、第２図は
従来例の形成方法に係るボンデイングパツド電極
の断面図である。
（符号の説明）、１，４……GaAs基板、２，
９……SiO2膜、３……Au系メタル膜、５……ｎ
型GaAs領域、６……高濃度ｎ型GaAs領域、７，
１２……WSi膜、８……AuGe−Au膜、１０，１
１……開口部、１３……Au又はTi／Pt／Au蒸着
膜、１４……Auメツキ膜。
FIG. 1 is a cross-sectional view illustrating a method for forming a bonding pad electrode according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a bonding pad electrode according to a conventional method. (Explanation of symbols), 1, 4...GaAs substrate, 2,
9...SiO 2 film, 3...Au-based metal film, 5...n
type GaAs region, 6...high concentration n-type GaAs region, 7,
12...WSi film, 8...AuGe-Au film, 10,1
1...Opening part, 13...Au or Ti/Pt/Au vapor deposited film, 14...Au plating film.
Claims (1)
域の上に第１の金属膜を被着して該不純物導電領
域との間でオーミツクコンタクトを形成し、かつ
同時に該第１の金属膜を化合物半導体基板に直接
被着してボンデイングパツド用の第１の層を形成
する工程と、 層間絶縁膜の上に第２の金属膜を被着して配線
用金属膜を形成し、かつ同時に該第２の金属膜を
前記第１の層の上にも直接被着してボンデイング
パツド用の第２の層を形成する工程とを特徴とす
るボンデイングパツド電極の形成方法。[Claims] 1. A first metal film is deposited on an impurity conductive region formed on a compound semiconductor substrate to form an ohmic contact with the impurity conductive region, and at the same time A step of directly depositing a metal film on a compound semiconductor substrate to form a first layer for a bonding pad, and a step of depositing a second metal film on an interlayer insulating film to form a metal film for wiring. and simultaneously depositing the second metal film directly on the first layer to form a second layer for the bonding pad. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16027486A JPS6315436A (en) | 1986-07-08 | 1986-07-08 | Forming method for bonding pad electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16027486A JPS6315436A (en) | 1986-07-08 | 1986-07-08 | Forming method for bonding pad electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6315436A JPS6315436A (en) | 1988-01-22 |
| JPH0439228B2 true JPH0439228B2 (en) | 1992-06-26 |
Family
ID=15711452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16027486A Granted JPS6315436A (en) | 1986-07-08 | 1986-07-08 | Forming method for bonding pad electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6315436A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5422307A (en) * | 1992-03-03 | 1995-06-06 | Sumitomo Electric Industries, Ltd. | Method of making an ohmic electrode using a TiW layer and an Au layer |
-
1986
- 1986-07-08 JP JP16027486A patent/JPS6315436A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6315436A (en) | 1988-01-22 |
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