JP3123217B2 - Method of forming ohmic electrode - Google Patents

Method of forming ohmic electrode

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Publication number
JP3123217B2
JP3123217B2 JP14108692A JP14108692A JP3123217B2 JP 3123217 B2 JP3123217 B2 JP 3123217B2 JP 14108692 A JP14108692 A JP 14108692A JP 14108692 A JP14108692 A JP 14108692A JP 3123217 B2 JP3123217 B2 JP 3123217B2
Authority
JP
Japan
Prior art keywords
layer
ohmic electrode
compound semiconductor
alloy
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14108692A
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Japanese (ja)
Other versions
JPH05315282A (en
Inventor
幹夫 鎌田
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Sony Corp
Original Assignee
Sony Corp
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Priority to JP14108692A priority Critical patent/JP3123217B2/en
Publication of JPH05315282A publication Critical patent/JPH05315282A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、オーミック電極の形成
方法、更に詳しくは、構成成分としてGaを含む化合物
半導体層におけるオーミック電極の形成方法に関する。
The present invention relates to a method for forming an ohmic electrode, and more particularly to a method for forming an ohmic electrode in a compound semiconductor layer containing Ga as a constituent.

【0002】[0002]

【従来の技術】GaAs系の化合物半導体装置に形成さ
れたGaAs系半導体層上には、従来、AuGe又はN
i−AuGeから成る金属層を合金化することによっ
て、オーミック電極が形成される。オーミック電極は、
例えば、n形GaAs化合物半導体層上に、Au−Ge
(12重量%)層、及びNi層を順に真空蒸着法で形成
した後、400〜450゜Cで合金化処理を行うことに
よって形成される。この合金化処理によって、Au−G
eの溶解が起こり液相が形成される。このとき、n形G
aAs化合物半導体層の表面は非飽和状態であるためA
u−Ge溶液中に溶解し、Au−Ga、及び過剰のAs
とNi、Geから成るNi−As−Geから成る合金層
が形成される。次いで、合金層上に電極材料層を堆積
し、更に電極材料層を所望の形状にエッチングすること
によってオーミック電極を完成させる。
2. Description of the Related Art Conventionally, AuGe or N is formed on a GaAs semiconductor layer formed in a GaAs compound semiconductor device.
An ohmic electrode is formed by alloying a metal layer made of i-AuGe. Ohmic electrodes are
For example, Au-Ge is formed on the n-type GaAs compound semiconductor layer.
(12% by weight) layer and a Ni layer are formed in this order by a vacuum deposition method, and then alloyed at 400 to 450 ° C. By this alloying treatment, Au-G
Dissolution of e occurs and a liquid phase is formed. At this time, n-type G
Since the surface of the aAs compound semiconductor layer is in an unsaturated state, A
Au-Ga dissolved in u-Ge solution and excess As
And an alloy layer composed of Ni-As-Ge composed of Ni and Ge. Next, an electrode material layer is deposited on the alloy layer, and the electrode material layer is further etched into a desired shape to complete an ohmic electrode.

【0003】[0003]

【発明が解決しようとする課題】この合金層中にはβ−
AuGaが生成することが知られている。β−AuGa
の生成の結果、合金層は熱的に不安定となる。即ち、β
−AuGaの融点は約360゜Cであり、合金層形成後
に経なければならない種々の工程、例えば、約350゜
Cで行うSiN層のCVD法による形成、の処理温度と
同程度である。そのため、このような後工程における処
理温度にオーミック電極が曝されると、電極のコンタク
ト抵抗が増加するという問題がある(例えば、文献 "De
velopmentof Ohmic contact materials for GaAs integ
rated circuit", M. Murakami, Material Science Repo
rts 5 (1990), pp273-317 参照)。更に、室温において
すら、速さは遅いものの、電極のコンタクト抵抗の増加
が進行する。このような現象は、AuGeから成る金属
層を合金化することによって形成されるオーミック電極
においても発生する。
The alloy layer contains β-
It is known that AuGa is generated. β-AuGa
As a result, the alloy layer becomes thermally unstable. That is, β
The melting point of AuGa is about 360 ° C., which is about the same as the processing temperature of various steps that must be performed after the formation of the alloy layer, for example, the formation of the SiN layer by the CVD method at about 350 ° C. Therefore, when the ohmic electrode is exposed to the processing temperature in such a post-process, there is a problem that the contact resistance of the electrode is increased (for example, the literature "De"
velopmentof Ohmic contact materials for GaAs integ
rated circuit ", M. Murakami, Material Science Repo
rts 5 (1990), pp273-317). Furthermore, even at room temperature, the contact resistance of the electrode increases, albeit at a low speed. Such a phenomenon also occurs in an ohmic electrode formed by alloying a metal layer made of AuGe.

【0004】このような現象のために、AuGe又はN
i−AuGeから成る金属層を合金化することによって
形成された合金層から成るオーミック電極は信頼性に乏
しいという問題を有する。
Due to such a phenomenon, AuGe or N
An ohmic electrode made of an alloy layer formed by alloying a metal layer made of i-AuGe has a problem of poor reliability.

【0005】従って、本発明の目的は、熱的に安定し
た、高い信頼性を有するオーミック電極を、構成成分と
してGaを含む化合物半導体層に形成する方法を提供す
ることにある。
Accordingly, it is an object of the present invention to provide a method for forming a thermally stable, highly reliable ohmic electrode on a compound semiconductor layer containing Ga as a constituent.

【0006】[0006]

【課題を解決するための手段】本発明者は、Ni−Au
Geから成る金属層を合金化することによって形成され
た合金層の厚さ方向の組成を分析したところ、合金層の
表層には主にAu及びGaが含まれ、表層以外の合金層
には主にNi−As−Geが含まれていることを見い出
し、本発明を完成するに至った。即ち、本発明のオーミ
ック電極の形成方法は、 (イ)構成成分としてGaを含む化合物半導体層上に、
Auを含む金属層を形成する工程と、 (ロ)この金属層に合金化処理を施し合金層とする工程
と、 (ハ)合金層における、主にAu−Gaを含む表層を除
去する工程と、 (ニ)表層が除去された合金層に電極材料層を堆積させ
る工程、から成ることを特徴とする。
Means for Solving the Problems The present inventor has proposed a Ni—Au
When the composition in the thickness direction of the alloy layer formed by alloying the metal layer made of Ge was analyzed, the surface layer of the alloy layer mainly contained Au and Ga, and the alloy layers other than the surface layer mainly contained Au and Ga. Contained Ni-As-Ge in the present invention, and completed the present invention. That is, the method for forming an ohmic electrode according to the present invention includes the following steps: (a) forming a compound semiconductor layer containing Ga
A step of forming a metal layer containing Au; (b) a step of subjecting the metal layer to alloying to form an alloy layer; and (c) a step of removing a surface layer mainly containing Au—Ga in the alloy layer . (D) depositing an electrode material layer on the alloy layer from which the surface layer has been removed.

【0007】本発明のオーミック電極の形成方法の一態
様においては、金属層は、AuGe層及びNi層の2層
から構成されることが好ましい。
In one aspect of the method for forming an ohmic electrode of the present invention, the metal layer is preferably composed of two layers, an AuGe layer and a Ni layer.

【0008】[0008]

【作用】構成成分としてGaを含む化合物半導体層上に
形成された金属層に合金化処理を施し合金層とする工程
において、Auは合金層の表層に移動し、合金層の表層
は主にAu及びGaを含む層となる。本発明の方法にお
いては、この表層をエッチング等によって除去するの
で、前述した熱的に不安定なβ−AuGaがオーミック
電極中に殆ど存在しなくなり、その結果、熱的に安定し
たオーミック電極を得ることができる。
In the process of forming an alloy layer by subjecting a metal layer formed on a compound semiconductor layer containing Ga as a component to an alloy layer, Au moves to the surface of the alloy layer, and the surface of the alloy layer is mainly Au. And a layer containing Ga. In the method of the present invention, since the surface layer is removed by etching or the like, the above-mentioned thermally unstable β-AuGa hardly exists in the ohmic electrode, and as a result, a thermally stable ohmic electrode is obtained. be able to.

【0009】[0009]

【実施例】以下、実施例に基づき、図面を参照して本発
明のオーミック電極の形成方法を説明する。先ず、従来
の方法でGaAs系の化合物半導体を作製する。図1の
(A)に模式的な一部断面図を示すように、最上層の構
成成分としてGaを含む化合物半導体層10は、n形G
aAs化合物半導体層から成る。化合物半導体層10の
オーミック電極を形成する領域以外の領域に、例えばS
iNから成る絶縁層12を通常のCVD法等で形成す
る。尚、絶縁層12を、場合によっては省略することが
できる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for forming an ohmic electrode according to the present invention will be described with reference to the drawings based on embodiments. First, a GaAs-based compound semiconductor is manufactured by a conventional method. As shown in a schematic partial cross-sectional view of FIG. 1A, the compound semiconductor layer 10 containing Ga as a component of the uppermost layer is an n-type G
It consists of an aAs compound semiconductor layer. In regions other than the regions where the ohmic electrodes of the compound semiconductor layer 10 are formed, for example, S
An insulating layer 12 made of iN is formed by a normal CVD method or the like. Note that the insulating layer 12 can be omitted in some cases.

【0010】次いで、化合物半導体層10上にAuを含
む金属層を形成する。金属層のパターニングはリフトオ
フ法にて行うことができる。このAuを含む金属層14
は、化合物半導体層10側から、200nm厚さのAu
−Ge(12重量%)層16、及びその上に形成された
50nm厚さのNi層18から成る(図1の(A)参
照)。これらの層は、例えば真空蒸着法、その他各種の
成膜方法にて形成することができる。この状態では、金
属層14は、下地である化合物半導体層10とショット
キー接合となっており、電流−電圧特性はオーミックで
はなく、整流性を示す。
Next, a metal layer containing Au is formed on the compound semiconductor layer 10. The patterning of the metal layer can be performed by a lift-off method. This metal layer 14 containing Au
Is a 200 nm thick Au from the compound semiconductor layer 10 side.
A Ge (12% by weight) layer 16 and a 50 nm-thick Ni layer 18 formed thereon (see FIG. 1A). These layers can be formed by, for example, a vacuum evaporation method or other various film formation methods. In this state, the metal layer 14 has a Schottky junction with the underlying compound semiconductor layer 10, and the current-voltage characteristics are not ohmic but show rectification.

【0011】その後、金属層14に合金化処理を施し合
金層20とする。合金化処理は、例えば、450゜C、
1分の熱処理である。尚、熱処理における温度、時間は
適宜変更することができる。これによって、化合物半導
体層10中のGaAsと、金属層14中のNi−AuG
eとが反応し合金化される。この合金層20及び構成成
分としてGaを含む化合物半導体層10の厚さ方向の組
成をオージェ分析により解析した結果を図2に示す。合
金層20の表層にはAuが多く含まれている。即ち、G
aAs半導体層10上には主にNi−As−Geから成
る層22が形成され、Auは合金層の表層に移動してい
る。図1の(B)に模式的にこの状態を示すが、合金層
20は、GaAs半導体層10側から主にNi−As−
Geを含む層22及び主にAu−Gaを含む表層24の
2層構造となっている。
Thereafter, an alloying process is performed on the metal layer 14 to form an alloy layer 20. The alloying process is performed, for example, at 450 ° C.
This is a heat treatment for one minute. Note that the temperature and time in the heat treatment can be appropriately changed. Thereby, GaAs in the compound semiconductor layer 10 and Ni-AuG in the metal layer 14 are formed.
reacts with e to form an alloy. FIG. 2 shows the result of Auger analysis of the composition in the thickness direction of the alloy layer 20 and the compound semiconductor layer 10 containing Ga as a constituent. The surface layer of the alloy layer 20 contains much Au. That is, G
A layer 22 mainly composed of Ni-As-Ge is formed on the aAs semiconductor layer 10, and Au has moved to the surface of the alloy layer. FIG. 1B schematically shows this state, and the alloy layer 20 is mainly composed of Ni—As— from the GaAs semiconductor layer 10 side.
It has a two-layer structure of a layer 22 containing Ge and a surface layer 24 mainly containing Au-Ga.

【0012】次に、合金層20の表層24をエッチング
法にて除去する。除去すべき表層の厚さは、合金層全体
の厚さの20〜80%程度である。エッチング法とし
て、例えばイオンミーリング法や、I2:NH4I:H2
O:C25OHから成るエッチング液を使用したウエッ
トエッチング法を挙げることができる。エッチングによ
って主にAu及びGaを含む表層24を除去した後に残
る合金層20は、主にNi−As−Geを含む層であ
る。この合金層20と化合物半導体層との接触は、従来
の方法で形成されるNi−As−Geから成る合金層と
基本的には同一であり、本発明の方法で形成されるオー
ミック電極は、従来の方法で形成されるオーミック電極
と同じ程度のコンタクト抵抗値となる。しかるに、熱的
に不安定な主にβ−AuGaを含む表層24が除去され
ている。それ故、オーミック電極は熱的に安定したもの
となる。
Next, the surface layer 24 of the alloy layer 20 is removed by an etching method. The thickness of the surface layer to be removed is about 20 to 80% of the total thickness of the alloy layer. As an etching method, for example, an ion milling method or I 2 : NH 4 I: H 2
A wet etching method using an etchant composed of O: C 2 H 5 OH can be used. The alloy layer 20 remaining after the surface layer 24 mainly containing Au and Ga is removed by etching is a layer mainly containing Ni-As-Ge. The contact between the alloy layer 20 and the compound semiconductor layer is basically the same as the alloy layer made of Ni—As—Ge formed by the conventional method, and the ohmic electrode formed by the method of the present invention is: The contact resistance is about the same as that of an ohmic electrode formed by a conventional method. However, the surface layer 24 mainly containing β-AuGa which is thermally unstable is removed. Therefore, the ohmic electrode becomes thermally stable.

【0013】次いで、図1の(C)に示すように、主に
Au及びGaを含む表層24が除去された合金層20、
即ち主にNi−As−Geを含む層上に電極材料層26
を従来の方法で堆積させる。電極材料層26は、例え
ば、合金層20側から、50nm厚さのTi層、50n
m厚さのW層、50nm厚さのTi層、50nm厚さの
Pt層、500nm厚さのAu層とすることができ、こ
れらの電極材料を、例えば真空蒸着法で堆積させること
ができる。その後、イオンミーリング法等で電極材料層
26をパターニングして所望の電極形状にする。尚、電
極材料層中、最下層のTi層は合金層20との接着性向
上のために、また、W層は、この上に形成される電極材
料層(本実施例の場合、Ti−Pt−Au層)との金属
間反応を抑制するために形成される。
Next, as shown in FIG. 1C, the alloy layer 20 from which the surface layer 24 mainly containing Au and Ga has been removed,
That is, the electrode material layer 26 is formed on the layer mainly containing Ni-As-Ge.
Is deposited in a conventional manner. The electrode material layer 26 is, for example, a 50 nm thick Ti layer, 50 n
A W layer having a thickness of m, a Ti layer having a thickness of 50 nm, a Pt layer having a thickness of 50 nm, and an Au layer having a thickness of 500 nm can be used. These electrode materials can be deposited by, for example, a vacuum evaporation method. Thereafter, the electrode material layer 26 is patterned by an ion milling method or the like to obtain a desired electrode shape. In the electrode material layer, the lowermost Ti layer is used for improving the adhesion to the alloy layer 20, and the W layer is used for the electrode material layer (Ti-Pt in this embodiment) formed thereon. —Au layer) to suppress an intermetallic reaction.

【0014】以上、本発明を好ましい実施例に基づき説
明したが、本発明はこの実施例に限定されるものではな
い。本発明の方法で、オーミック電極をn形GaAs基
板上に形成することができる。Auを含む金属層とし
て、AuGeを用いることができる。また、化合物半導
体層として、GaAs以外にも、AlGaAs、InG
aAs等、構成成分としてGaを含む化合物半導体を挙
げることができる。
Although the present invention has been described based on the preferred embodiment, the present invention is not limited to this embodiment. With the method of the present invention, an ohmic electrode can be formed on an n-type GaAs substrate. AuGe can be used as the metal layer containing Au. As the compound semiconductor layer, other than GaAs, AlGaAs, InG,
Compound semiconductors containing Ga as a constituent such as aAs can be given.

【0015】本発明の方法は、MESFET、JFE
T、HEMT、HET等の各種化合物半導体装置、半導
体レーザ、受光素子等、オーミック接触を必要とする各
種装置の作製に適用することができる。
[0015] The method of the present invention comprises a MESFET, a JFE
The present invention can be applied to the manufacture of various devices requiring ohmic contact, such as various compound semiconductor devices such as T, HEMT, and HET, semiconductor lasers, light receiving elements, and the like.

【0016】[0016]

【発明の効果】本発明の方法においては、オーミック電
極の熱的不安定を生じさせる原因となるβ−AuGaが
合金層から除去される。従って、合金層形成後に行われ
る種々の工程、例えば層間絶縁層であるSiN層のCV
D法による形成工程、においてオーミック電極が高温に
曝されても、電極のコンタクト抵抗は増加することがな
い。また、MESFETやJFETのような構成成分と
してGaを含む化合物半導体層上にAuGe又はNi−
AuGeから形成される合金層を備えた化合物半導体装
置や、半導体レーザ、受光素子の信頼性を向上させるこ
とができる。
According to the method of the present invention, β-AuGa which causes thermal instability of the ohmic electrode is removed from the alloy layer. Therefore, various processes performed after the formation of the alloy layer, for example, the CV of the SiN layer as the interlayer insulating layer
Even if the ohmic electrode is exposed to a high temperature in the formation process by the method D, the contact resistance of the electrode does not increase. In addition, AuGe or Ni-type is formed on a compound semiconductor layer containing Ga as a component such as MESFET or JFET.
The reliability of a compound semiconductor device, a semiconductor laser, and a light receiving element having an alloy layer formed of AuGe can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のオーミック電極の形成方法を説明する
ための、化合物半導体装置の模式的な一部断面図であ
る。
FIG. 1 is a schematic partial cross-sectional view of a compound semiconductor device for explaining a method of forming an ohmic electrode according to the present invention.

【図2】合金層及び化合物半導体層の厚さ方向のオージ
ェ分析結果を示す図である。
FIG. 2 is a diagram showing Auger analysis results in the thickness direction of an alloy layer and a compound semiconductor layer.

【符号の説明】[Explanation of symbols]

10 構成成分としてGaを含む化合物半導体層 12 絶縁層 14 金属層 16 AuGe層 18 Ni層 20 合金層 22 主にNi−As−Geを含む層 24 主にAu及びGaを含む層 26 電極材料層 DESCRIPTION OF SYMBOLS 10 Compound semiconductor layer containing Ga as a constituent 12 Insulating layer 14 Metal layer 16 AuGe layer 18 Ni layer 20 Alloy layer 22 Layer mainly containing Ni-As-Ge 24 Layer mainly containing Au and Ga 26 Electrode material layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/28 H01L 29/80 H01L 31/02 H01L 33/00 H01S 5/042 H01S 5/323 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/28 H01L 29/80 H01L 31/02 H01L 33/00 H01S 5/042 H01S 5/323

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】構成成分としてGaを含む化合物半導体層
にオーミック電極を形成する方法であって、 (イ)該化合物半導体層上にAuを含む金属層を形成す
る工程と、 (ロ)該金属層に合金化処理を施し合金層とする工程
と、 (ハ)合金層における、主にAu−Gaを含む表層を除
去する工程と、 (ニ)表層が除去された合金層に電極材料層を堆積させ
る工程、 から成ることを特徴とするオーミック電極の形成方法。
1. A method for forming an ohmic electrode on a compound semiconductor layer containing Ga as a constituent component, comprising: (a) forming a metal layer containing Au on the compound semiconductor layer; (C) removing a surface layer mainly containing Au—Ga in the alloy layer ; and (d) forming an electrode material layer on the alloy layer from which the surface layer has been removed. Depositing an ohmic electrode.
【請求項2】前記金属層は、AuGe層及びNi層の2
層から構成されることを特徴とする請求項1に記載のオ
ーミック電極の形成方法。
2. The metal layer includes an AuGe layer and a Ni layer.
The method for forming an ohmic electrode according to claim 1, comprising a layer.
【請求項3】記表層が除去された合金層には主にNi
−As−Geが含まれていることを特徴とする請求項1
又は請求項2に記載のオーミック電極の形成方法。
3. Primarily Ni before Symbol alloy layer surface is removed
-As-Ge is contained.
Or the method of forming an ohmic electrode according to claim 2.
JP14108692A 1992-05-07 1992-05-07 Method of forming ohmic electrode Expired - Lifetime JP3123217B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14108692A JP3123217B2 (en) 1992-05-07 1992-05-07 Method of forming ohmic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14108692A JP3123217B2 (en) 1992-05-07 1992-05-07 Method of forming ohmic electrode

Publications (2)

Publication Number Publication Date
JPH05315282A JPH05315282A (en) 1993-11-26
JP3123217B2 true JP3123217B2 (en) 2001-01-09

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