JPS61139064A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61139064A JPS61139064A JP26073984A JP26073984A JPS61139064A JP S61139064 A JPS61139064 A JP S61139064A JP 26073984 A JP26073984 A JP 26073984A JP 26073984 A JP26073984 A JP 26073984A JP S61139064 A JPS61139064 A JP S61139064A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- ohmic contact
- mogexsiy
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 239000000956 alloy Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- -1 TaSix and Ge Chemical compound 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、Ｇ ａ Ａ ｓ Ｍ Ｅ Ｓ Ｆ Ｅ Ｔ等
の化合物半導体に用いられるオーミックコンタクト電極
に適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to ohmic contact electrodes used in compound semiconductors such as GaAsMESFET.
［背景技術］
従来のＩｎＰ、ＧａＡｓなどのオーミックコンタクト電
極には、Ａｕ−Ｇｅ合金をベースとした合金が多く用い
られてきた。しかし、例えばＮ型Ｇ ａ Ａ ｓに対す
るＡ ｕ Ｇ ｅ電極では５ｏｌｉｄ ５ｔａｔｅＥｌ
ｅｃｔｒｏｎｉｃｓ、１９８２年、第２６巻の第２５９
頁から第２６６頁に記載されているように、初期１０−
５Ωｄ以下であった電極の接触抵抗が３５０°Ｃ１１０
時間程度の熱処理によって１．５Ｘ１０−’ Ωｄに劣
化する。また、４００℃程度の熱処理で電極の平坦性が
悪化し、１μｍ程度の凹凸が発生する場合もある。この
ようにＡ ｕ Ｇ ａ を極は熱的に信頼性が劣るとい
う欠点があった。[Background Art] For conventional ohmic contact electrodes such as InP and GaAs, alloys based on Au-Ge alloys have often been used. However, for example, in the A u G e electrode for N-type Ga As, 5 solid 5 tate El
electronics, 1982, Volume 26, No. 259
The initial 10-
The contact resistance of the electrode was 5Ωd or less at 350°C110
It deteriorates to 1.5×10 −' Ωd by heat treatment for about an hour. In addition, heat treatment at about 400° C. may deteriorate the flatness of the electrode, resulting in unevenness of about 1 μm. As described above, the A u Ga electrode has a drawback of poor thermal reliability.
さらに、ＡｕＧａオーミックコンタクト電極は。Furthermore, the AuGa ohmic contact electrode.
一般にリフトオフ加工がなされ歩留まり低下の原因とな
る。また、上層のアルミニウム配線との間にバリア層が
必要であったり、絶縁膜との密着性が悪＜、Ａｕを用い
るのでコスト高となる等の問題も有している。Generally, lift-off processing is performed, which causes a decrease in yield. Further, there are other problems, such as the need for a barrier layer between the upper layer aluminum wiring, poor adhesion with the insulating film, and high cost since Au is used.
［発明の目的コ
本発明の目的は、熱的に安定であり、かつ、上述の種々
の問題点を解消し得るオーミックコンタクト電極を有す
る化合物半導体装置を提供することにある。[Object of the Invention] An object of the present invention is to provide a compound semiconductor device having an ohmic contact electrode that is thermally stable and capable of solving the various problems described above.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
［発明の概要コ
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Summary of the Invention A brief outline of typical inventions disclosed in this application is as follows.
Ｍ ｏ 、Ｗ、 Ｔ ａなとの高融点金属とＳｉとＧｅ
とからなるオーミックコンタクト電極を用いることによ
り、耐熱性のあるＭｏ Ｓ ｉｘ 、 ＷＳ ｉｘ 。High melting point metals such as Mo, W, Ta, Si and Ge
By using an ohmic contact electrode consisting of Mo S ix and WS ix which have heat resistance.
Ｔ ａ Ｓ ｉ ｘなどの金属シリサイドとＧｅの化合
物であるので、半導体装置の耐熱性を向上させ熱的な安
定を可能とするものである。さらに、このようにオーミ
ックコンタクト電極を用いることにより、半導体基板と
の選択比が大きくとれ、ドライエツチングプロセスの適
用が容易となり、さらに、アルミニウム配線との間のバ
リア層が不要であり、絶縁膜との密着性が良く、コスト
的にも問題がな１＋’ａ
［実施例］
以下、本発明をＧ ａ Ａ ｓ化合物半導体のオーミッ
クコンタクト電極に適用した場合につき、その製造プロ
セスに従って説明する。第１図はその一実施例であるＧ
ａ Ａ ｓ Ｌ Ｓ Ｉの構造断面の一部を示す。Since it is a compound of metal silicide such as TaSix and Ge, it improves the heat resistance of the semiconductor device and makes it thermally stable. Furthermore, by using an ohmic contact electrode in this way, a high selectivity with respect to the semiconductor substrate can be obtained, making it easy to apply a dry etching process, and furthermore, there is no need for a barrier layer between the aluminum wiring and the insulating film. 1+'a has good adhesion and causes no cost problems.Example: Hereinafter, a case where the present invention is applied to an ohmic contact electrode of a GaAs compound semiconductor will be explained according to its manufacturing process. Figure 1 shows an example of G
a Part of the structural cross section of A s L S I is shown.
半絶縁性Ｇ ａ Ａ ｓ基板１に選択的にＳｉイオンを
打込み、Ｎ型Ｇ ａ Ａ、 ｓ層２を形成する。この後
、Ｍ ｏ 、Ｗ、 Ｔ ａ等の高融点金属とＳｉとＧｅ
とからなる合金（以下ＭｏＧｅｘＳｉｙと略記する）層
をスパッタ蒸着により］、ＯＯｒ＋Ｉ１１の厚さに被着
する。このＭｏＧｅｘＳｉｙ層をＣＦ４ガスを用いたド
ライ二ソ・チングにより加工し、オーミックコンタクト
電極３を形成する６オーミツク特性を得るために電極３
形成後、Ｇ ａ Ａ ｓ基板１に７００〜１０００℃の
熱処理を加える。この後、絶縁層４を６０Ｏｎ＋ｍ程度
の厚さに形成する。絶縁層４はＣＶＤ法による５ｉ０２
もしくはＰＳＧとする。この後、Ａ２による配線５を形
成する。ＡＱ配線５の厚さは約１μｍとする。なお、Ｍ
ｏＧｅｘＳｉｙ電極３とＡＱ配線５の導通のために絶縁
層４に必要に応じ導通穴を開ける。Si ions are selectively implanted into a semi-insulating GaAs substrate 1 to form an N-type GaAs layer 2. After this, high melting point metals such as Mo, W, Ta, Si and Ge
(hereinafter abbreviated as MoGexSiy) is deposited by sputter deposition] to a thickness of OOr+I11. This MoGexSiy layer is processed by dry diode etching using CF4 gas, and the electrode 3 is processed to obtain 6-ohmic characteristics to form the ohmic contact electrode 3.
After the formation, the GaAs substrate 1 is subjected to heat treatment at 700 to 1000°C. Thereafter, the insulating layer 4 is formed to a thickness of about 60 On+m. Insulating layer 4 is made of 5i02 by CVD method.
Or PSG. After this, the wiring 5 of A2 is formed. The thickness of the AQ wiring 5 is approximately 1 μm. In addition, M
A conductive hole is made in the insulating layer 4 as necessary to establish conduction between the oGexSiy electrode 3 and the AQ wiring 5.
このようなＧ ａ Ａ ｓ Ｌ Ｓ Ｉのオーミックコ
ンタクト電極３は、３５０’Ｃ１１０時間の熱処理後も
、１０−５Ωｄ以下の接触抵抗を示し熱的に安定である
。また、４００℃、１０時間の熱処理後も電極の凹凸は
ＬＯＯｎｍ以下である。また、従来のＡ ｕ Ｇ ｅ電
極６では、第２図に示すように、ＡＱとＡｕＧｅとの反
応を抑止するために配線はＡＱ層８とバリヤ層７からな
る２層構造とする必要があった。なお、第２図において
第１図と同様な構成に対しては同一符号を付して示して
いる。バリヤ層７はＴｉＷ合金またはＭｏが用いられて
いた。The ohmic contact electrode 3 of such a GaAs LSI exhibits a contact resistance of 10-5 Ωd or less and is thermally stable even after heat treatment at 350'C for 110 hours. Moreover, even after heat treatment at 400° C. for 10 hours, the unevenness of the electrode is less than LOO nm. Furthermore, in the conventional A u G e electrode 6, as shown in FIG. 2, the wiring needs to have a two-layer structure consisting of the AQ layer 8 and the barrier layer 7 in order to suppress the reaction between AQ and AuGe. Ta. In FIG. 2, the same components as in FIG. 1 are designated by the same reference numerals. The barrier layer 7 was made of TiW alloy or Mo.
しかし、ＭｏＧｅｘＳｉｙ電極３では、ＡＱ配線５を直
接接触させることができ、素子製造上の利点がある。However, with the MoGexSiy electrode 3, the AQ wiring 5 can be brought into direct contact, which is advantageous in terms of device manufacturing.
［効果コ
本発明によれば、Ａ ｕ Ｇ ｅ電極よりも高耐熱のオ
ーミックコンタクト電極を用いることができるので、化
合物半導体装置の熱的な信頼性が向上する。[Effects] According to the present invention, it is possible to use an ohmic contact electrode which is more heat resistant than an A.sub.G e electrode, so the thermal reliability of the compound semiconductor device is improved.
また、ＡｕＧｅ電極を用いる半導体装置に比べさらに次
の利点がある。Furthermore, there are the following advantages compared to semiconductor devices using AuGe electrodes.
（１）Ａｕを用いないため製造原価が低減できる。(1) Since Au is not used, manufacturing costs can be reduced.
（２）Ｓ ｉ ０２ 、Ｓ ｉＮｘなどの絶縁膜とＡｕ
Ｇｅは密着性が良くないため、絶縁膜上をＡ ｕ Ｇ
ｅで配線すると信頼性が悪化する。−力木発明によるＭ
ｏＧｅｘＳｉｙは絶縁膜との密着性が良いので絶縁膜上
を配線できる。これは、集積回路素子に有利である。(2) Insulating films such as Si02 and SiNx and Au
Since Ge does not have good adhesion, A u G is applied on the insulating film.
If wiring is done with e, reliability will deteriorate. - M invented by strength tree
Since oGexSiy has good adhesion to the insulating film, it is possible to conduct wiring over the insulating film. This is advantageous for integrated circuit devices.
（３）ＡｕＧｅ電極では、イオンミリング法を除いて、
ドライエッチプロセスが困難である。しかし、イオンミ
リング法では半導体基板とＡ ｕ Ｇ ｅ電極との選択
比が小さい問題がある。本発明の電極では、半導体基板
ＧａＡｓとの選択比が大きくとれるドライエツチングプ
ロセスの適用が容易で、電極の微細加工ができる。(3) For AuGe electrodes, except for the ion milling method,
Dry etch process is difficult. However, the ion milling method has a problem in that the selectivity between the semiconductor substrate and the AuGe electrode is low. In the electrode of the present invention, a dry etching process that has a high etching selectivity with respect to the semiconductor substrate GaAs can be easily applied, and the electrode can be microfabricated.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが１本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.
［利用分野］
本発明はＧ ａ Ａ ｓ以外の化合物半導体装置、たと
えば、ＩｎＰなどにも適用できる。[Field of Application] The present invention can also be applied to compound semiconductor devices other than GaAs, such as InP.
第１図は本発明の半導体装置の一実施例を示す断面図、
第２図は従来の半導体装置の断面図である。
１・・・化合物半導体基板、２・・・Ｎ型層、３・・・
ＭｏＧｅｘＳｉｙ電極、４・・・絶縁膜、５−−−ＡＱ
配線、６・・・Ａ ｕ Ｇ ｅ電極、７・・・バリヤ層
、８・・・ＡＱ第 １ 図
第 ２ 図FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1... Compound semiconductor substrate, 2... N-type layer, 3...
MoGexSiy electrode, 4...insulating film, 5---AQ
Wiring, 6... A u G e electrode, 7... Barrier layer, 8... AQ Fig. 1 Fig. 2
Claims (1)
らなる合金を用いたオーミックコンタクト電極が化合物
半導体上に形成されてなることを特徴とする半導体装置
。1. A semiconductor device comprising an ohmic contact electrode formed on a compound semiconductor using an alloy of a high-melting point metal such as Mo, W, or Ta, and Si and Ge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26073984A JPS61139064A (en) | 1984-12-12 | 1984-12-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26073984A JPS61139064A (en) | 1984-12-12 | 1984-12-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61139064A true JPS61139064A (en) | 1986-06-26 |
Family
ID=17352074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26073984A Pending JPS61139064A (en) | 1984-12-12 | 1984-12-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61139064A (en) |
-
1984
- 1984-12-12 JP JP26073984A patent/JPS61139064A/en active Pending
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