JPH06177200A - Formation of semiconductor integrated circuit device - Google Patents

Formation of semiconductor integrated circuit device

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Publication number
JPH06177200A
JPH06177200A JP4329104A JP32910492A JPH06177200A JP H06177200 A JPH06177200 A JP H06177200A JP 4329104 A JP4329104 A JP 4329104A JP 32910492 A JP32910492 A JP 32910492A JP H06177200 A JPH06177200 A JP H06177200A
Authority
JP
Japan
Prior art keywords
film
laminated wiring
layer
bonding pad
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4329104A
Other languages
Japanese (ja)
Inventor
Shinji Nishihara
晋治 西原
Masashi Sawara
政司 佐原
Masayuki Kojima
雅之 児島
Yukio Tanigaki
幸男 谷垣
Akira Haruta
亮 春田
Yasushi Kawabuchi
靖 河渕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4329104A priority Critical patent/JPH06177200A/en
Publication of JPH06177200A publication Critical patent/JPH06177200A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve bondability of the surface of a bonding pad and also reflectivity of the surface of a bonding pad. CONSTITUTION:In a semiconductor integrated circuit device, a laminated wiring 10 and an oxide layer 10D between the aluminum alloy film 10B of a bonding pad and a cap metal film (TiW film, W film, TiN film) are formed, and after a bonding opening 11 is formed, the cap metal film 10C of the bonding pad and the oxide layer 10D respectively are removed in sequence.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は配線形成技術に関する。
特に、本発明は、積層配線に結線されかつ同一断面構造
を有するボンディングパッドを被覆するパッシベーショ
ン膜にボンディング開口を形成する半導体集積回路装置
の配線形成技術に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming technique.
In particular, the present invention relates to a technique effectively applied to a wiring forming technique of a semiconductor integrated circuit device in which a bonding opening is formed in a passivation film which covers a bonding pad connected to a laminated wiring and having a same cross-sectional structure.

【０００２】[0002]

【従来の技術】シリコンデバイスとしての半導体集積回
路装置は半導体素子間の結線にアルミニウム合金配線が
使用される。このアルミニウム合金配線は純アルミニウ
ムにエレクトロマイグレーション耐性を高めるＣｕ、ア
ロイスパイク耐性を高めるＳｉの夫々が添加される。2. Description of the Related Art In a semiconductor integrated circuit device as a silicon device, aluminum alloy wiring is used for connecting semiconductor elements. In this aluminum alloy wiring, pure aluminum is added with Cu for enhancing electromigration resistance and Si for enhancing alloy spike resistance.

【０００３】製造プロセスにおける最小加工寸法が０.
８〔μｍ〕所謂０.８〔μｍ〕プロセスの世代に移行す
ると、アルミニウム合金配線の単層からアルミニウム合
金膜を配線の主層とした積層配線が採用される。この積
層配線はアルミニウム合金膜の下層にバリアメタル膜、
上層にキャップメタル膜の夫々が積層される。The minimum processing size in the manufacturing process is 0.0.
8 [μm] In the so-called 0.8 [μm] process generation, laminated wiring having a single layer of aluminum alloy wiring as the main layer of the aluminum alloy wiring is adopted. This laminated wiring has a barrier metal film under the aluminum alloy film,
Each of the cap metal films is laminated on the upper layer.

【０００４】バリアメタル膜は、シリコン基板のＳｉ、
アルミニウム合金膜のアルミニウムの夫々の相互拡散を
防止する目的で形成され、高融点金属珪化膜具体的には
ＭｏＳｉ2 膜が使用される。キャップメタル膜は、アル
ミニウムヒルロックを防止する目的もあるが、一般的に
はアルミニウム合金膜のパターンニングの際の詳細には
フォトリソグラフィ技術のフォトレジスト膜の露光時の
回析現象（ハレーション）を減少する目的で形成され
る。このため、キャップメタル膜はアルミニウム合金膜
の表面の反射率に比べて低い反射率を有する材料、通常
は同一スパッタ装置内（同一真空系内）で処理を行いか
つ製造プロセスの工程数を削減することを目的としてＭ
ｏＳｉ2 膜が使用される。The barrier metal film is made of Si on a silicon substrate,
The refractory metal silicide film is formed for the purpose of preventing mutual diffusion of aluminum in the aluminum alloy film, and specifically, a MoSi 2 film is used. The cap metal film also has the purpose of preventing aluminum hillocks, but in general, details of the diffraction phenomenon (halation) at the time of exposure of the photoresist film of the photolithography technique are described in detail when patterning the aluminum alloy film. It is formed for the purpose of decreasing. For this reason, the cap metal film is a material having a reflectance lower than that of the surface of the aluminum alloy film, which is usually processed in the same sputtering apparatus (in the same vacuum system) and reduces the number of manufacturing processes. For that purpose
An oSi 2 film is used.

【０００５】最近の０.５〔μｍ〕プロセスの世代にお
いては、前記積層配線の下層のバリアメタル膜、上層の
キャップメタル膜のいずれもＭｏＳｉ2 膜に変えて２種
類の高融点金属の合金つまりＴｉＷ膜が使用される。こ
のＴｉＷ膜は、ＭｏＳｉ2 膜をバリアメタル膜として使
用した場合に発生するアルミニウム合金膜中のＳｉの析
出を防止でき、しかもエレクトロマイグレーション耐性
がＭｏＳｉ2 膜に比べて優れている。In the recent generation of the 0.5 [μm] process, the barrier metal film as the lower layer and the cap metal film as the upper layer of the laminated wiring are both replaced with MoSi 2 films, that is, alloys of two kinds of refractory metals, that is, A TiW film is used. This TiW film can prevent the precipitation of Si in the aluminum alloy film that occurs when the MoSi 2 film is used as a barrier metal film, and is superior in electromigration resistance to the MoSi 2 film.

【０００６】このＴｉＷ膜、アルミニウム合金膜、Ｔｉ
Ｗ膜の夫々を順次積層した積層配線は半導体集積回路装
置の多層配線構造の最終配線層にも配置されかつボンデ
ィングパッド（外部端子）としても使用される。このボ
ンディングパッドはその表面上を被覆するファイナルパ
ッシベーション膜（最終保護膜）に形成されたボンディ
ング開口を通してワイヤがボンディングされる。ワイヤ
としては例えばＡｕワイヤが使用される。This TiW film, aluminum alloy film, Ti
The laminated wiring in which the W films are sequentially laminated is arranged also in the final wiring layer of the multilayer wiring structure of the semiconductor integrated circuit device and is also used as a bonding pad (external terminal). A wire is bonded to the bonding pad through a bonding opening formed in a final passivation film (final protective film) covering the surface of the bonding pad. For example, Au wire is used as the wire.

【０００７】前記ボンディングパッドは、半導体集積回
路装置の製造プロセスにおいて、前記積層配線と同一製
造工程で形成されかつ同一断面構造で構成されるが、ボ
ンディング開口を形成した後にこのボンディング開口を
マスクとしてエッチングにより上層のキャップメタル膜
が除去される。このキャップメタル膜の除去はボンディ
ングパッドとワイヤとの間のボンダビリティの向上を目
的として行われる。また、キャップメタル膜は、ワイヤ
をボンディングする際のボンダー（ワイヤボンディング
装置）の位置検出を行うことを目的として除去される。In the manufacturing process of the semiconductor integrated circuit device, the bonding pad is formed in the same manufacturing step as the laminated wiring and has the same sectional structure. After the bonding opening is formed, the bonding opening is used as a mask for etching. Thus, the upper cap metal film is removed. The removal of the cap metal film is performed for the purpose of improving bondability between the bonding pad and the wire. Further, the cap metal film is removed for the purpose of detecting the position of the bonder (wire bonding device) when bonding the wire.

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、本発明
者は、前記半導体集積回路装置の配線形成技術におい
て、下記の問題点を見出した。However, the present inventor has found the following problems in the wiring forming technique of the semiconductor integrated circuit device.

【０００９】半導体集積回路装置の多層配線構造の最終
配線層にＴｉＷ膜、アルミニウム合金膜、ＴｉＷ膜の夫
々を順次積層した積層配線を配置した場合、アルミニウ
ム合金膜とＴｉＷ膜との間の界面にアルミニウム、Ｔｉ
及びＷの３元化化合物（合金化化合物）が生成される。
特に、ＭＯＳＦＥＴを有する半導体集積回路装置の製造
プロセスにおいては、積層配線、ファイナルパッシベー
ション膜の夫々を順次形成した後、ボンディング開口を
形成する前にアニールが組み込まれ、このアニールに起
因して３元化化合物が生成されやすい。アニールは、Ｍ
ＯＳＦＥＴの電気的特性の安定化を目的として、水素ガ
ス雰囲気中、約４００〔℃〕の温度において行われる。When a laminated wiring in which a TiW film, an aluminum alloy film, and a TiW film are sequentially laminated is arranged in the final wiring layer of the multilayer wiring structure of the semiconductor integrated circuit device, it is arranged at the interface between the aluminum alloy film and the TiW film. Aluminum, Ti
And W ternary compounds (alloying compounds) are generated.
In particular, in the manufacturing process of a semiconductor integrated circuit device having a MOSFET, annealing is incorporated after the laminated wiring and the final passivation film are sequentially formed and before the bonding opening is formed. Compounds are easily generated. Annealing is M
It is performed at a temperature of about 400 [° C.] in a hydrogen gas atmosphere for the purpose of stabilizing the electrical characteristics of the OSFET.

【００１０】このため、ボンディングパッドにおいて
は、ボンディング開口の形成後に上層のキャップメタル
膜を除去しても、３元化化合物のＴｉ、Ｗのいずれかが
残渣としてアルミニウム合金膜の表面に残り、又前記残
渣をマスクとしてアルミニウム合金膜の表面がオーバー
エッチングされる。このアルミニウム合金膜の表面の残
渣又はこの残渣に基づく表面のオーバーエッチングは、
ボンディングパッドの表面においてワイヤをボンディン
グする際にボンダビリティを著しく低下し、又反射率の
減少によりボンダーでの位置検出が不可能になる。本発
明者が行ったボンディングパッドの表面の反射率の測定
結果によれば、室温で堆積した純アルミニウム膜の表面
の反射率、波長４０５〔ｎｍ〕を基準とした場合、反射
率が約６０〔％〕まで減少した。Therefore, in the bonding pad, even if the cap metal film of the upper layer is removed after the formation of the bonding opening, one of Ti and W of the ternary compound remains as a residue on the surface of the aluminum alloy film, or The surface of the aluminum alloy film is over-etched using the residue as a mask. The surface residue of the aluminum alloy film or the surface over-etching based on this residue is
Bondability is significantly reduced when wires are bonded on the surface of the bonding pad, and the decrease in reflectance makes it impossible to detect the position with a bonder. According to the measurement results of the reflectance of the surface of the bonding pad performed by the present inventor, the reflectance of the surface of the pure aluminum film deposited at room temperature, which is about 60 [nm] when the wavelength of 405 [nm] is used as a reference. %].

【００１１】本発明の目的は、積層配線と同一構造で形
成されるボンディングパッドがパッシベーション膜のボ
ンディング開口から露出する半導体集積回路装置におい
て、前記ボンディングパッドの表面のボンダビリティを
向上するとともに、前記ボンディングパッドの表面の反
射率を向上することが可能な技術を提供することにあ
る。An object of the present invention is to improve the bondability of the surface of the bonding pad in the semiconductor integrated circuit device in which the bonding pad formed in the same structure as the laminated wiring is exposed from the bonding opening of the passivation film, and the bonding is performed. It is to provide a technique capable of improving the reflectance of the surface of the pad.

【００１２】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【００１３】[0013]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記のとおりである。Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

【００１４】積層配線を有する半導体集積回路装置の形
成方法において、基板上にアルミニウム膜又はアルミニ
ウム合金膜で形成される積層配線の下層を堆積し、前記
下層の表面上に下層の酸化物層を形成した後に、前記酸
化物層の表面上に２種類の高融点金属で形成される合金
膜又は高融点金属膜又は高融点金属窒化膜で形成された
積層配線の上層を堆積する工程、前記積層配線の上層、
酸化物層、下層の夫々を順次パターンニングし、積層配
線及びこの積層配線に結線されかつ同一の断面構造を有
するボンディングパッドを形成する工程、前記積層配線
上及びボンディングパッド上を含む基板全面にパッシベ
ーション膜を堆積する工程、前記パッシベーション膜の
前記ボンディングパッド上にボンディング開口を形成す
るとともに、前記ボンディングパッドのボンディング開
口から露出する上層、酸化物層の夫々を順次除去し、こ
のボンディングパッドの下層の表面を露出する工程の夫
々の工程を順次備える。In a method of forming a semiconductor integrated circuit device having laminated wiring, a lower layer of laminated wiring formed of an aluminum film or an aluminum alloy film is deposited on a substrate, and a lower oxide layer is formed on the surface of the lower layer. And then depositing an upper layer of a laminated wiring formed of an alloy film, a refractory metal film, or a refractory metal nitride film formed of two kinds of refractory metals on the surface of the oxide layer, the laminated wiring Upper layer,
A step of sequentially patterning each of the oxide layer and the lower layer to form a laminated wiring and a bonding pad connected to the laminated wiring and having the same cross-sectional structure, passivation on the entire surface of the substrate including the laminated wiring and the bonding pad A step of depositing a film, forming a bonding opening on the bonding pad of the passivation film, sequentially removing an upper layer and an oxide layer exposed from the bonding opening of the bonding pad, and a surface of a lower layer of the bonding pad. Each step of exposing the step is sequentially provided.

【００１５】また、前記積層配線の下層、上層の夫々は
いずれも真空系内で行われるスパッタ法において堆積さ
れ、前記下層の表面上の酸化物層は前記真空系内から非
連続的に基板を一度大気中に開放することにより、又酸
化雰囲系内において強制酸化を行うことにより形成され
る。Further, each of the lower layer and the upper layer of the laminated wiring is deposited by a sputtering method performed in a vacuum system, and the oxide layer on the surface of the lower layer discontinuously covers the substrate from the vacuum system. It is formed by once exposing it to the atmosphere and by performing forced oxidation in an oxidizing atmosphere system.

【００１６】[0016]

【作用】上述した手段によれば、前記積層配線の下層を
堆積後、上層を堆積する前に、下層のアルミニウムと上
層の高融点金属との反応を防止するバリア膜としての酸
化物層を形成し、ボンディング開口を形成した後、ボン
ディングパッドの上層を除去するときに併せて酸化物層
を除去し、ボンディングパッドの下層の表面を露出した
ので、前記ボンディングパッドの下層、上層の夫々の間
の界面において化合物の生成を基本的に排除でき、しか
もボンディングパッドの下層の表面からその表面に損傷
を与えずにきれいな状態において酸化物層が除去でき
る。この結果、前記ボンディングパッドの下層の表面に
おいて、ボンダビリティが向上でき、又反射率が向上で
きる。According to the above-mentioned means, after depositing the lower layer of the laminated wiring and before depositing the upper layer, an oxide layer is formed as a barrier film for preventing a reaction between the lower aluminum and the upper refractory metal. Then, after forming the bonding opening, the oxide layer was also removed when the upper layer of the bonding pad was removed, and the surface of the lower layer of the bonding pad was exposed. The formation of compounds at the interface can be essentially eliminated, and the oxide layer can be removed cleanly from the surface of the underlying layer of the bonding pad without damaging the surface. As a result, bondability and reflectance can be improved on the surface of the lower layer of the bonding pad.

【００１７】以下、本発明の構成について、ＭＩＳＦＥ
Ｔを有しかつ２層配線構造を有する半導体集積回路装置
の配線形成技術に本発明を適用した一実施例とともに説
明する。The structure of the present invention will be described below with reference to MISFE.
An example in which the present invention is applied to a wiring forming technique of a semiconductor integrated circuit device having T and having a two-layer wiring structure will be described.

【００１８】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

【００１９】[0019]

【実施例】本発明の一実施例である２層配線構造を採用
する半導体集積回路装置の構成を図１（要部断面図）で
示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a semiconductor integrated circuit device adopting a two-layer wiring structure, which is an embodiment of the present invention, is shown in FIG.

【００２０】図１に示すように、半導体集積回路装置
は、単結晶珪素からなるｐ型半導体基板１を主体に構成
されるとともに、このｐ型半導体基板１の素子形成面
（図１中、上側表面）には２層配線構造を備える。As shown in FIG. 1, the semiconductor integrated circuit device is mainly composed of a p-type semiconductor substrate 1 made of single crystal silicon, and an element formation surface of the p-type semiconductor substrate 1 (upper side in FIG. 1). The surface) has a two-layer wiring structure.

【００２１】前記ｐ型半導体基板１の素子形成面におい
て、非活性領域（図１中、左側）には素子分離絶縁膜
（フィールド酸化珪素膜）２及びｐ型チャネルストッパ
領域３が構成される。また、ｐ型半導体基板１の素子形
成面において、活性領域（図１中、右側）には半導体素
子としてのＭＩＳＦＥＴが構成される。このＭＩＳＦＥ
Ｔは、チャネル形成領域として使用されるｐ型半導体基
板（又はウエル領域）１、ゲート絶縁膜４、ゲート電極
５、ソース領域及びドレイン領域として使用される一対
のｎ型半導体領域６を主体に構成される。On the device forming surface of the p-type semiconductor substrate 1, a device isolation insulating film (field silicon oxide film) 2 and a p-type channel stopper region 3 are formed in a non-active region (left side in FIG. 1). Further, on the element formation surface of the p-type semiconductor substrate 1, a MISFET as a semiconductor element is formed in the active region (right side in FIG. 1). This MISFE
T is mainly composed of a p-type semiconductor substrate (or well region) 1 used as a channel formation region, a gate insulating film 4, a gate electrode 5, and a pair of n-type semiconductor regions 6 used as source and drain regions. To be done.

【００２２】前記ＭＩＳＦＥＴの上部には第１層目の配
線層に配置される積層配線８が構成され、この積層配線
８の上部には第２層目の配線層（最上層の配線層）に配
置される積層配線１０が構成される。A laminated wiring 8 arranged in the first wiring layer is formed above the MISFET, and a second wiring layer (uppermost wiring layer) is formed above the laminated wiring 8. The laminated wiring 10 to be arranged is configured.

【００２３】前記積層配線８は、ＭＩＳＦＥＴ上を含む
基板全面に形成されたパッシベーション膜（層間絶縁
膜）７の表面上に形成され、このパッシベーション膜７
に形成された接続孔７Ｈを通してＭＩＳＦＥＴのｎ型半
導体領域６に接続される。この積層配線８は下層のバリ
アメタル膜８Ａ、中間層のアルミニウム合金膜８Ｂ、上
層のキャップメタル膜８Ｃの夫々を順次積層した３層構
造で構成される。積層配線８のバリアメタル膜８Ａ、キ
ャップメタル膜８Ｃの夫々は本実施例においてはＴｉ、
Ｗの２種類の高融点金属の合金であるＴｉＷ膜が使用さ
れる。また、バリアメタル膜８Ａ、キャップメタル膜８
Ｃの夫々は、ＴｉＷ膜に変えて、高融点金属膜具体的に
はＷ又は高融点金属窒化膜具体的にはＴｉＮ膜を使用し
てもよい。The laminated wiring 8 is formed on the surface of a passivation film (interlayer insulating film) 7 formed on the entire surface of the substrate including the MISFET, and the passivation film 7 is formed.
It is connected to the n-type semiconductor region 6 of the MISFET through the connection hole 7H formed in. The laminated wiring 8 has a three-layer structure in which a lower barrier metal film 8A, an intermediate aluminum alloy film 8B, and an upper cap metal film 8C are sequentially laminated. Each of the barrier metal film 8A and the cap metal film 8C of the laminated wiring 8 is Ti in the present embodiment.
A TiW film which is an alloy of two refractory metals of W is used. In addition, the barrier metal film 8A and the cap metal film 8
Each of C may be replaced with a TiW film, and a refractory metal film, specifically W or a refractory metal nitride film, specifically a TiN film may be used.

【００２４】前記積層配線１０は、積層配線８上を含む
基板全面に形成されたパッシベーション膜９の表面上に
形成され、このパッシベーション膜９に形成された接続
孔９Ｈを通して積層配線８に接続される。この積層配線
１０は基本的には積層配線８の断面構造と同一構造で形
成すなわち下層のバリアメタル膜１０Ａ、中間層のアル
ミニウム合金膜１０Ｂ、上層のキャップメタル膜１０Ｃ
の夫々を順次積層した３層構造で構成される。積層配線
１０のバリアメタル膜１０Ａ、キャップメタル膜１０Ｃ
の夫々は同様にＴｉＷ膜が使用される。The laminated wiring 10 is formed on the surface of a passivation film 9 formed on the entire surface of the substrate including the laminated wiring 8, and is connected to the laminated wiring 8 through a connection hole 9H formed in the passivation film 9. . The laminated wiring 10 is basically formed with the same structure as the sectional structure of the laminated wiring 8, that is, the lower barrier metal film 10A, the intermediate aluminum alloy film 10B, and the upper cap metal film 10C.
Each of them is sequentially laminated to have a three-layer structure. Barrier metal film 10A and cap metal film 10C of the laminated wiring 10
Similarly, a TiW film is used for each of the above.

【００２５】また、前記積層配線１０は、半導体集積回
路装置の製造プロセス中、少なくともボンディングパッ
ド（図１中、左側のワイヤ１３がボンディングされた領
域）において、中間層のアルミニウム合金膜１０Ｂと上
層のキャップメタル膜１０Ｃとの間の界面にアルミニウ
ム合金膜１０Ｂの酸化物層１０Ｄが構成される。つま
り、酸化物層１０Ｄはアルミニウム酸化物（ＡＬ2Ｏ3）
層で構成される。この酸化物層１０Ｄはアルミニウム合
金膜１０Ｂのアルミニウム、キャップメタル膜１０Ｃの
Ｔｉ、Ｗの夫々の３元化化合物（合金化化合物）の生成
を阻止できるバリア層として作用する。In the manufacturing process of the semiconductor integrated circuit device, the laminated wiring 10 has at least the bonding pad (the region where the wire 13 on the left side in FIG. 1 is bonded), which is the intermediate layer of the aluminum alloy film 10B and the upper layer. The oxide layer 10D of the aluminum alloy film 10B is formed at the interface with the cap metal film 10C. That is, the oxide layer 10D is made of aluminum oxide (AL 2 O 3 )
Composed of layers. This oxide layer 10D acts as a barrier layer that can prevent the formation of ternary compounds (alloying compounds) of aluminum of the aluminum alloy film 10B and Ti and W of the cap metal film 10C.

【００２６】前記酸化物層１０Ｄはファイナルパッシベ
ーション膜１１にボンディング開口１１Ｈを形成した後
に除去され、ボンディングパッド（積層配線１０）の表
面は中間層のアルミニウム合金膜１０Ｂの表面が露出さ
れる。The oxide layer 10D is removed after forming the bonding opening 11H in the final passivation film 11, and the surface of the bonding pad (laminated wiring 10) is exposed at the surface of the intermediate aluminum alloy film 10B.

【００２７】前記積層配線１０上を含む基板全面にはフ
ァイナルパッシベーション膜１１、樹脂膜１２の夫々が
順次積層される。ファイナルパッシベーション膜１１
は、外部環境からの保護特に耐湿性を向上する目的で、
例えばプラズマＣＶＤ法で堆積された窒化珪素膜が使用
される。前記樹脂膜１２は、半導体集積回路装置（半導
体ペレット）を封止する樹脂パッケージからの放射線の
遮蔽、前記樹脂パッケージとの密着性の向上を目的とし
て、例えばポリイミド系樹脂膜が使用される。A final passivation film 11 and a resin film 12 are sequentially laminated on the entire surface of the substrate including the laminated wiring 10. Final passivation film 11
Protects from the external environment, especially for the purpose of improving moisture resistance,
For example, a silicon nitride film deposited by the plasma CVD method is used. For the resin film 12, for example, a polyimide resin film is used for the purpose of shielding radiation from a resin package that seals a semiconductor integrated circuit device (semiconductor pellet) and improving adhesion with the resin package.

【００２８】前記ボンディングパッドが配置される領域
において前記樹脂膜１２には開口１２Ｈが形成され、こ
の開口１２Ｈ内において前記ファイナルパッシベーショ
ン膜１１にはボンディング開口１１Ｈが形成される。An opening 12H is formed in the resin film 12 in a region where the bonding pad is arranged, and a bonding opening 11H is formed in the final passivation film 11 in the opening 12H.

【００２９】そして、前記ボンディングパッドの中間層
のアルミニウム合金膜１０Ｂの表面は、前記開口１２
Ｈ、ボンディング開口１１Ｈの夫々を通してワイヤ１３
がボンディングされる。ワイヤ１３は例えばＡｕワイヤ
が使用され、このＡｕワイヤはボンダー（ワイヤボンデ
ィング装置）でボンディングされる。The surface of the aluminum alloy film 10B, which is an intermediate layer of the bonding pad, has the opening 12
Wire 13 through each of H and the bonding opening 11H.
Are bonded. As the wire 13, for example, an Au wire is used, and this Au wire is bonded by a bonder (wire bonding device).

【００３０】次に、前記半導体集積回路装置の形成方法
について、図２乃至図５（各製造工程毎に示す要部断面
図）を使用し、簡単に説明する。Next, a method of forming the semiconductor integrated circuit device will be briefly described with reference to FIGS. 2 to 5 (cross-sectional views of the essential part shown in each manufacturing step).

【００３１】まず、ｐ型半導体基板１の素子形成面の非
活性領域に素子分離絶縁膜２、ｐ型チャネルストッパ領
域３の夫々を形成する。この後、前記ｐ型半導体基板１
の素子形成面の活性領域にＭＩＳＦＥＴを形成する。First, the element isolation insulating film 2 and the p-type channel stopper region 3 are formed in the non-active region of the element formation surface of the p-type semiconductor substrate 1. After this, the p-type semiconductor substrate 1
A MISFET is formed in the active region of the element formation surface.

【００３２】次に、前記ＭＩＳＦＥＴ上を含む基板全面
にパッシベーション膜７を形成する。この後、前記ＭＩ
ＳＦＥＴのｎ型半導体領域６上において、前記パッシベ
ーション膜７に接続孔７Ｈを形成する。Next, a passivation film 7 is formed on the entire surface of the substrate including the MISFET. After this, the MI
A contact hole 7H is formed in the passivation film 7 on the n-type semiconductor region 6 of the SFET.

【００３３】次に、前記パッシベーション膜７の表面上
に、接続孔７Ｈを通してＭＩＳＦＥＴのｎ型半導体領域
６に接続される積層配線８を形成する。この積層配線８
は、後述する積層配線１０を形成する条件と実質的に同
様（酸化物層を除く）であるので詳細な説明は省略する
が、ＴｉＷ膜８Ａ、アルミニウム合金膜８Ｂ、ＴｉＷ膜
８Ｃの夫々を順次積層した３層構造で構成される（図２
参照）。Next, a laminated wiring 8 connected to the n-type semiconductor region 6 of the MISFET through the connection hole 7H is formed on the surface of the passivation film 7. This laminated wiring 8
Is substantially the same as the condition for forming a laminated wiring 10 (excluding an oxide layer) described later, so a detailed description thereof will be omitted, but the TiW film 8A, the aluminum alloy film 8B, and the TiW film 8C are sequentially formed. It is composed of a laminated three-layer structure (Fig. 2
reference).

【００３４】次に、図２に示すように、前記積層配線８
上を含む基板全面にパッシベーション膜９を形成する。
この後、前記積層配線８上において、前記パッシベーシ
ョン膜９に接続孔９Ｈを形成する。Next, as shown in FIG. 2, the laminated wiring 8 is formed.
A passivation film 9 is formed on the entire surface of the substrate including the top.
Then, a connection hole 9H is formed in the passivation film 9 on the laminated wiring 8.

【００３５】次に、図３、図４の夫々に順次示すよう
に、前記パッシベーション膜９の表面上に、接続孔９Ｈ
を通して積層配線８に接続される積層配線１０を形成す
る。すなわち、図３に示すように、まず初めに、パッシ
ベーション膜９の表面上の全面にバリアメタル膜１０Ａ
としてのＴｉＷ膜、主層としてのアルミニウム合金膜１
０Ｂ、酸化物層１０Ｄ、キャップメタル膜１０Ｃとして
のＴｉＷ膜の夫々を順次積層する。Next, as shown in FIG. 3 and FIG. 4 respectively, a connection hole 9H is formed on the surface of the passivation film 9.
A laminated wiring 10 connected to the laminated wiring 8 is formed. That is, as shown in FIG. 3, first, the barrier metal film 10A is formed on the entire surface of the passivation film 9.
Film as a main layer, aluminum alloy film as a main layer 1
0B, the oxide layer 10D, and the TiW film as the cap metal film 10C are sequentially laminated.

【００３６】前記バリアメタル膜１０ＡとしてのＴｉＷ
膜は、スパッタ法で堆積し、例えば１００〜２００〔ｎ
ｍ〕の膜厚で形成する。スパッタターゲットは例えばＷ
−１０〔％〕Ｔｉを使用し、スパッタ温度は１００〜３
００〔℃〕、Ａｒ圧力は０.４〜２.０〔Ｐａ〕の条件に
おいて、前記ＴｉＷ膜が形成される。TiW as the barrier metal film 10A
The film is deposited by a sputtering method, and is, for example, 100 to 200 [n
m]. The sputter target is, for example, W
-10 [%] Ti is used, and the sputtering temperature is 100 to 3
The TiW film is formed under the conditions of 00 [° C.] and Ar pressure of 0.4 to 2.0 [Pa].

【００３７】前記アルミニウム合金膜１０Ｂは、スパッ
タ法で堆積し、例えば４００〜１０００〔ｎｍ〕の膜厚
で形成する。スパッタターゲットは例えばアルミニウム
−０.５〔％〕Ｃｕ−１.０〔％〕Ｓｉ、スパッタ温度は
１００〜３００〔℃〕、Ａｒ圧力は０.４〜２.０〔Ｐ
ａ〕の条件において、前記アルミニウム合金膜１０Ｂが
形成される。The aluminum alloy film 10B is deposited by a sputtering method to have a film thickness of 400 to 1000 [nm], for example. The sputtering target is, for example, aluminum-0.5 [%] Cu-1.0 [%] Si, the sputtering temperature is 100 to 300 [° C.], and the Ar pressure is 0.4 to 2.0 [P].
Under the condition of a], the aluminum alloy film 10B is formed.

【００３８】このアルミニウム合金膜１０Ｂを形成する
工程は前記バリアメタル膜１０ＡとしてのＴｉＷ膜を形
成する工程と同一真空系内（大気中に開放せずに同一の
スパッタ装置内）において連続的に行う。また、ＴｉＷ
膜上に２０〔ｎｍ〕以上の酸化膜ができなければ一度大
気中に開放し、ＴｉＷ膜を形成する工程に対して非連続
的にアルミニウム合金膜１０Ｂを形成する工程を行って
もよい。The step of forming the aluminum alloy film 10B is continuously performed in the same vacuum system (in the same sputtering apparatus without opening to the atmosphere) as the step of forming the TiW film as the barrier metal film 10A. . Also, TiW
If an oxide film having a thickness of 20 nm or more cannot be formed on the film, the step of forming the aluminum alloy film 10B discontinuously with respect to the step of forming the TiW film may be performed by opening the film once into the atmosphere.

【００３９】前記酸化物層１０Ｄはアルミニウム合金膜
１０Ｂの表面上にこのアルミニウム合金膜１０Ｂの表面
を酸化することにより形成される。つまり、酸化物層１
０Ｄは、アルミニウム合金膜１０Ｂの堆積後に真空系内
から一度大気中に開放（例えば約５〔分〕）する、又は
酸化雰囲気中のプロセスチャンバーを通して強制酸化を
行うことにより形成する。この酸化物層１０Ｄは、本発
明者が行ったオージェ分析に基づく測定結果によれば、
１〜５〔ｎｍ〕の膜厚の範囲内が最適である。The oxide layer 10D is formed on the surface of the aluminum alloy film 10B by oxidizing the surface of the aluminum alloy film 10B. That is, the oxide layer 1
OD is formed by once opening the inside of the vacuum system to the atmosphere (for example, about 5 [minutes]) after depositing the aluminum alloy film 10B, or by performing forced oxidation through a process chamber in an oxidizing atmosphere. According to the measurement result based on Auger analysis performed by the present inventor, the oxide layer 10D is
The optimum thickness is in the range of 1 to 5 [nm].

【００４０】前記キャップメタル膜１０ＣとしてのＴｉ
Ｗ膜は、スパッタ法で堆積し、例えば２０〜８０〔ｎ
ｍ〕の膜厚で形成する。このＴｉＷ膜は前記バリアメタ
ル膜１０ＡとしてのＴｉＷ膜と実質的に同一の条件にお
いて堆積される。Ti as the cap metal film 10C
The W film is deposited by the sputtering method, and is, for example, 20 to 80 [n
m]. This TiW film is deposited under substantially the same conditions as the TiW film as the barrier metal film 10A.

【００４１】次に、前記キャップメタル膜１０Ｃとして
のＴｉＷ膜、酸化物層１０Ｄ、アルミニウム合金膜１０
Ｂ、バリアメタル膜１０ＡとしてのＴｉＷ膜の夫々に順
次パターンニングを施し、図４に示すように、積層配線
１０（図４中、左側）及びこの積層配線１０に結線され
かつ同一断面構造を有するボンディングパッド（図４
中、右側）を形成する。前記パターンニングは、フォト
リソグラフィ技術で形成されたフォトレジストマスクを
使用し、ＲＩＥ等の異方性エッチングで行う。Next, the TiW film as the cap metal film 10C, the oxide layer 10D, and the aluminum alloy film 10 are formed.
B, the TiW film as the barrier metal film 10A is sequentially patterned, and as shown in FIG. 4, the laminated wiring 10 (left side in FIG. 4) and the laminated wiring 10 are connected and have the same sectional structure. Bonding pad (Fig. 4
Middle, right side). The patterning is performed by anisotropic etching such as RIE using a photoresist mask formed by a photolithography technique.

【００４２】次に、前記積層配線１０上及びボンディン
グパッド上を含む基板全面にファイナルパッシベーショ
ン膜１１を堆積する。このファイナルパッシベーション
膜１１は例えばプラズマＣＶＤ法で堆積した窒化珪素膜
が使用される。Next, a final passivation film 11 is deposited on the entire surface of the substrate including the laminated wiring 10 and the bonding pads. As the final passivation film 11, for example, a silicon nitride film deposited by a plasma CVD method is used.

【００４３】次に、デバイス安定化特にＭＩＳＦＥＴの
電気的特性の安定化を目的として水素アニール処理を行
う。この水素アニール処理は、例えば４００〔℃〕の温
度において、約３０〔分〕行なう。Next, a hydrogen annealing process is performed for the purpose of device stabilization, especially for stabilizing the electrical characteristics of the MISFET. This hydrogen annealing treatment is performed at a temperature of 400 ° C. for about 30 minutes, for example.

【００４４】次に、前記ファイナルパッシベーション膜
１１上を含む基板全面に樹脂膜１２を形成する。この樹
脂膜１２は、前述のようにポリイミド系樹脂膜が使用さ
れ、２〜１０〔μｍ〕の膜厚で形成する。Next, a resin film 12 is formed on the entire surface of the substrate including the final passivation film 11. The resin film 12 is a polyimide resin film as described above, and is formed to have a film thickness of 2 to 10 [μm].

【００４５】次に、前記樹脂膜１２にパターンニングを
施し、前記ボンディングパッドの領域において、前記樹
脂膜１２に開口１２Ｈを形成する。この後、前記開口１
２Ｈ内において露出するファイナルパッシベーション膜
１１にパターンニングを施し、前記ファイナルパッシベ
ーション膜１１にボンディング開口１１Ｈを形成する。Next, the resin film 12 is patterned to form an opening 12H in the resin film 12 in the region of the bonding pad. After this, the opening 1
The final passivation film 11 exposed in 2H is patterned to form a bonding opening 11H in the final passivation film 11.

【００４６】そして、図５に示すように、前記ボンディ
ング開口１１Ｈから露出するボンディングパッド（積層
配線１０）の上層のキャップメタル膜１０ＣとしてのＴ
ｉＷ膜、酸化物層１０Ｄの夫々を順次エッチングにより
除去する。このエッチングは例えばＣＦ4 ガスを使用す
るプラズマエッチングで行う。Then, as shown in FIG. 5, T serving as the cap metal film 10C on the upper layer of the bonding pad (laminated wiring 10) exposed from the bonding opening 11H.
The iW film and the oxide layer 10D are sequentially removed by etching. This etching is performed by plasma etching using CF 4 gas, for example.

【００４７】このように、積層配線１０を有する半導体
集積回路装置の形成方法において、半導体基板上にアル
ミニウム合金膜１０Ｂで形成される積層配線１０の下層
を堆積し、前記下層の表面上に下層の酸化物層１０Ｄを
形成した後に、前記酸化物層１０Ｄの表面上にキャップ
メタル膜１０ＣとしてのＴｉＷ膜（又はＷ膜又はＴｉＮ
膜）で形成された積層配線１０の上層を堆積する工程、
前記積層配線１０の上層（１０Ｂ）、酸化物層１０Ｄ、
下層（１０Ｃ）の夫々を順次パターンニングし、積層配
線１０及びこの積層配線１０に結線されかつ同一の断面
構造を有するボンディングパッドを形成する工程、前記
積層配線１０上及びボンディングパッド上を含む基板全
面にパッシベーション膜１１を堆積する工程、前記パッ
シベーション膜１１の前記ボンディングパッド上にボン
ディング開口１１Ｈを形成するとともに、前記ボンディ
ングパッドのボンディング開口１１Ｈから露出する上層
（１０Ｃ）、酸化物層１０Ｄの夫々を順次除去し、この
ボンディングパッドの下層（１０Ｂ）の表面を露出する
工程の夫々の工程を順次備える。As described above, in the method of forming the semiconductor integrated circuit device having the laminated wiring 10, the lower layer of the laminated wiring 10 formed of the aluminum alloy film 10B is deposited on the semiconductor substrate, and the lower layer is formed on the surface of the lower layer. After forming the oxide layer 10D, a TiW film (or a W film or a TiN film) as a cap metal film 10C is formed on the surface of the oxide layer 10D.
A step of depositing an upper layer of the laminated wiring 10 formed of a film,
An upper layer (10B) of the laminated wiring 10, an oxide layer 10D,
A step of sequentially patterning each of the lower layers (10C) to form a laminated wiring 10 and a bonding pad connected to the laminated wiring 10 and having the same sectional structure, the entire surface of the substrate including the laminated wiring 10 and the bonding pad A step of depositing a passivation film 11 on the bonding pad, forming a bonding opening 11H on the bonding pad of the passivation film 11, and sequentially forming an upper layer (10C) exposed from the bonding opening 11H of the bonding pad and an oxide layer 10D. Each step of removing and exposing the surface of the lower layer (10B) of this bonding pad is sequentially provided.

【００４８】この構成により、前記積層配線１０の下層
（１０Ｂ）を堆積後、上層（１０Ｃ）を堆積する前に、
下層のアルミニウムと上層の高融点金属との反応を防止
するバリア膜としての酸化物層１０Ｄを形成し、ボンデ
ィング開口１１Ｈを形成した後、ボンディングパッドの
上層を除去するときに併せて酸化物層１０Ｄを除去し、
ボンディングパッドの下層の表面を露出したので、前記
ボンディングパッドの下層、上層の夫々の間の界面にお
いて化合物の生成を基本的に排除でき、しかもボンディ
ングパッドの下層の表面からその表面に損傷を与えずに
きれいな状態において酸化物層１０Ｄが除去できる。こ
の結果、前記ボンディングパッドの下層の表面におい
て、ボンダビリティが向上でき又反射率が向上できる。
本発明によれば、ボンディングパッドの下層の表面の反
射率は約９５〔％〕まで回復した。With this structure, after the lower layer (10B) of the laminated wiring 10 is deposited and before the upper layer (10C) is deposited,
After forming the oxide layer 10D as a barrier film for preventing the reaction between the lower layer aluminum and the upper refractory metal and forming the bonding opening 11H, the oxide layer 10D is also removed when the upper layer of the bonding pad is removed. Removed,
Since the surface of the lower layer of the bonding pad is exposed, the formation of compounds at the interface between the lower layer and the upper layer of the bonding pad can be basically eliminated, and the surface of the lower layer of the bonding pad does not damage the surface. The oxide layer 10D can be removed in a very clean state. As a result, bondability and reflectance can be improved on the surface of the lower layer of the bonding pad.
According to the present invention, the reflectance of the surface of the lower layer of the bonding pad has been restored to about 95%.

【００４９】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【００５０】例えば、本発明は、前記積層配線１０のア
ルミニウム合金配線１０Ｂに変えてアルミニウムを使用
してもよい。For example, in the present invention, aluminum may be used instead of the aluminum alloy wiring 10B of the laminated wiring 10.

【００５１】また、本発明は、単層構造若しくは３層構
造以上の配線層数を有する半導体集積回路装置に適用で
きる。Further, the present invention can be applied to a semiconductor integrated circuit device having a number of wiring layers having a single-layer structure or a three-layer structure or more.

【００５２】[0052]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【００５３】積層配線と同一構造で形成されるボンディ
ングパッドがパッシベーション膜のボンディング開口か
ら露出する半導体集積回路装置において、前記ボンディ
ングパッドの表面のボンダビリティを向上でき、しかも
前記ボンディングパッドの表面の反射率を向上できる。In the semiconductor integrated circuit device in which the bonding pad formed in the same structure as the laminated wiring is exposed from the bonding opening of the passivation film, the bondability of the surface of the bonding pad can be improved and the reflectance of the surface of the bonding pad can be improved. Can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の一実施例である半導体集積回路装置
の要部断面図。FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit device that is an embodiment of the present invention.

【図２】 前記半導体集積回路装置の製造プロセスの第
１工程での要部断面図。FIG. 2 is a sectional view of an essential part in a first step of a manufacturing process of the semiconductor integrated circuit device.

【図３】 第２工程での要部断面図。FIG. 3 is a sectional view of an essential part in a second step.

【図４】 第３工程での要部断面図。FIG. 4 is a sectional view of an essential part in a third step.

【図５】 第４工程での要部断面図。FIG. 5 is a sectional view of an essential part in a fourth step.

【符号の説明】[Explanation of symbols]

１…半導体基板、８，１０…積層配線、８Ａ，１０Ａ…
バリアメタル膜（ＴｉＷ膜）、８Ｂ，１０Ｂ…アルミニ
ウム合金膜、８Ｃ，１０Ｃ…キャップメタル膜（ＴｉＷ
膜）、１０Ｄ…酸化物層、１１…パッシベーション膜、
１１Ｈ…ボンディング開口。1 ... Semiconductor substrate, 8, 10 ... Laminated wiring, 8A, 10A ...
Barrier metal film (TiW film), 8B, 10B ... Aluminum alloy film, 8C, 10C ... Cap metal film (TiW)
Film), 10D ... oxide layer, 11 ... passivation film,
11H ... Bonding opening.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 谷垣 幸男 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 春田 亮 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 河渕 靖 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Tanigaki 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor Ryo Haruta 5 Sanmizumoto-cho, Kodaira-shi, Tokyo In the Musashi factory, Hitachi 20-21, Ltd. (72) Inventor, Yasushi Kawabuchi, 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Musashi factory, Hitachi, Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 積層配線を有する半導体集積回路装置の
形成方法において、下記の工程（１）乃至工程（４）の
夫々の工程を順次備えたことを特徴とする。 （１）基板上にアルミニウム膜又はアルミニウム合金膜
で形成される積層配線の下層を堆積し、前記下層の表面
上に下層の酸化物層を形成した後に、前記酸化物層の表
面上に２種類の高融点金属で形成される合金膜又は高融
点金属膜又は高融点金属窒化膜で形成された積層配線の
上層を堆積する工程、 （２）前記積層配線の上層、酸化物層、下層の夫々を順
次パターンニングし、積層配線及びこの積層配線に結線
されかつ同一の断面構造を有するボンディングパッドを
形成する工程、 （３）前記積層配線上及びボンディングパッド上を含む
基板全面にパッシベーション膜を堆積する工程、 （４）前記パッシベーション膜の前記ボンディングパッ
ド上にボンディング開口を形成するとともに、前記ボン
ディングパッドのボンディング開口から露出する上層、
酸化物層の夫々を順次除去し、このボンディングパッド
の下層の表面を露出する工程。1. A method for forming a semiconductor integrated circuit device having laminated wiring, comprising the following steps (1) to (4) in sequence. (1) After depositing a lower layer of a laminated wiring formed of an aluminum film or an aluminum alloy film on a substrate and forming a lower oxide layer on the surface of the lower layer, two types are formed on the surface of the oxide layer. A step of depositing an upper layer of a laminated wiring formed of an alloy film, a refractory metal film, or a refractory metal nitride film formed of the refractory metal of (2) each of the upper layer, the oxide layer, and the lower layer of the laminated wiring Sequentially forming a laminated wiring and a bonding pad connected to the laminated wiring and having the same sectional structure, (3) depositing a passivation film on the entire surface of the substrate including the laminated wiring and the bonding pad Step (4) Forming a bonding opening on the bonding pad of the passivation film, and from the bonding opening of the bonding pad Upper layer and out,
Sequentially removing each of the oxide layers to expose the surface of the underlying layer of this bonding pad. 【請求項２】 前記請求項１に記載される積層配線の下
層、上層の夫々はいずれも真空系内で行われるスパッタ
法において堆積され、前記下層の表面上の酸化物層は前
記真空系内から非連続的に基板を一度大気中に開放する
ことにより、又酸化雰囲気系内において強制酸化を行う
ことにより形成されることを特徴とする半導体集積回路
装置の形成方法。2. The lower layer and the upper layer of the laminated wiring according to claim 1 are both deposited by a sputtering method performed in a vacuum system, and the oxide layer on the surface of the lower layer is in the vacuum system. The method for forming a semiconductor integrated circuit device is characterized by discontinuously exposing the substrate to the atmosphere once and performing forced oxidation in an oxidizing atmosphere system.
JP4329104A 1992-12-09 1992-12-09 Formation of semiconductor integrated circuit device Pending JPH06177200A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4329104A JPH06177200A (en) 1992-12-09 1992-12-09 Formation of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4329104A JPH06177200A (en) 1992-12-09 1992-12-09 Formation of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH06177200A true JPH06177200A (en) 1994-06-24

Family

ID=18217660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4329104A Pending JPH06177200A (en) 1992-12-09 1992-12-09 Formation of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH06177200A (en)

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JP2021040168A (en) * 2014-07-11 2021-03-11 ローム株式会社 Electronic apparatus
US10211173B1 (en) 2017-10-25 2019-02-19 Mitsubishi Electric Corporation Semiconductor device and manufacturing method thereof
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