JP2900522B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding the structure of a metal wiring layer used in a semiconductor device, particularly a semiconductor integrated circuit, etc., an Al-Cu-Ti alloy layer is used as a main conductive layer, and stress migration resistance at high temperatures is used. To provide a semiconductor device having a highly reliable metal wiring layer that prevents deterioration of resistance, deterioration of electromigration resistance in a wide wiring width, and an increase in wiring resistance due to high-temperature heat treatment. Containing an alloy layer containing both copper and titanium
It has a configuration including a metal wiring layer having a layer structure.

[Industrial applications]

The present invention relates to a structure of a metal wiring layer used for a semiconductor device, particularly a semiconductor integrated circuit and the like.

In order to achieve high integration of a semiconductor integrated circuit device, in addition to miniaturization of a semiconductor element, the width of an aluminum (including an aluminum alloy) wiring layer used in a circuit configuration is also reduced to 1 μm or less. Need to be done. On the other hand, in the aluminum (Al) wiring layer, when the wiring width is reduced as described above, there is a problem that disconnection failure due to electromigration and stress migration is likely to occur, and the aluminum wiring layer having excellent migration resistance has a problem. Is required.

[Conventional technology]

As a method of improving the resistance to electromigration and stress migration, a method of using an alloy obtained by adding copper (Cu) and titanium (Ti) to Al as an Al wiring layer has been proposed in Japanese Patent Application Laid-Open No. 62-114241. I have. In the configuration of this wiring layer, the addition of a small amount of Cu suppresses the occurrence of migration of Al, and the addition of Ti prevents the growth of crystal grains at the time of forming an Al-Cu alloy layer at a high deposition rate. The suppression effect is more reliable.

However, the wiring layer made of the above-mentioned Cl-Cu-Ti alloy has the following problems.

1) When left at a high temperature of 200 ° C. or more, fracture failure due to stress migration is likely to occur.

2) Breakage due to electromigration is likely to occur in a wiring layer having a wide wiring width.

The above two problems are peculiar to the Al-Cu-Ti alloy and are not recognized in a normal Al-Si alloy or a wiring using the Al-Si-Cu alloy.

Therefore, in order to eliminate the above problem, the above-described Al-Cu-Ti alloy layer is formed on a Ti layer according to Japanese Patent Application No. 2-29595 (filed on Jan. 31, 1990). Two-layer structure
A metal wiring layer having an Al-Cu-Ti / Ti structure has been proposed. With this structure, the occurrence rate of fracture failure due to stress migration during high-temperature storage compared to the Al wiring layer consisting of the Al-Cu-Ti alloy layer single layer is reduced. This has been greatly improved, and a reduction in the average life due to electromigration in a wide wiring layer has been prevented.

[Problems to be solved by the invention]

However, in the above Al-Cu-Ti / Ti laminated wiring layer, Al and Ti react by a heat treatment at about 400 ° C. which is usually used for the growth of an insulating film for coating and the like, and a high-resistance metal is formed in the wiring layer. There is a problem that the generation of the compound Al ₃ Ti increases the sheet resistance (wiring resistance) of the laminated film.

That is, for example, the resistivity of the single-layer wiring layer of the Al-0.1% Cu-0.15% Ti alloy was about 3.4 μΩcm even after the heat treatment at 500 ° C. for 30 minutes. Al
-In the case of the Cu-Ti / Ti laminated wiring layer, the resistivity after the similar heat treatment is about 4.5 µΩcm, and shows a rise of 30% or more.

Therefore, when this Al-Cu-Ti / Ti laminated wiring layer is used in a semiconductor integrated circuit device or the like, the wiring resistance increases due to the increase in the resistances, thereby increasing the RC delay of the wiring and increasing the speed. There was a problem of being hindered.

Therefore, the present invention uses the above Al-Cu-Ti alloy layer as a main conductive layer, and prevents the deterioration of stress migration resistance at high temperature, the deterioration of electromigration resistance over a wide wiring width, and the increase in wiring resistance due to high temperature heat treatment. It is an object of the present invention to provide a semiconductor device having a reliable metal wiring layer.

[Means for solving the problem]

The above object is achieved by a semiconductor device according to the present invention, comprising a two-layer metal wiring layer in which an alloy layer containing aluminum as a main component and both copper and titanium is stacked on a tantalum layer. .

(Operation)

FIG. 1 is a schematic sectional view for explaining the principle of the present invention.
Is a semiconductor substrate, 2 is an interlayer insulating film having a thickness of about 8000 mm, 3 is a metal (Al) wiring layer, 3A is a Ta layer having a thickness of about 200 mm, and 3B is an Al-0.1% Cl-0.15% Ti layer having a thickness of about 5000 mm. The alloy layers 4 and 4 are coating insulating films.

That is, in the metal (Al) wiring layer 3 according to the present invention, as shown in the drawing, an alloy layer containing Al as a main component, for example, Al-Cu-Ti
As a base metal layer of the alloy layer 3B, the reaction rate with Al at a high temperature is extremely slow as compared with that of Ti, and therefore, when a high-temperature heat treatment is performed, a large amount of a high-resistance intermetallic compound is present in the Al-Cu-Ti alloy layer 3B. The low sheet resistance is maintained without generating
The Ta layer 3A was selected because the etching selectivity with the alloy layer, for example, the Al-Cu-Ti alloy layer 3B is small and the patterning can be performed collectively by the same etching process, so that the wiring forming process is not complicated.

Then, the structure of the metal wiring layer is placed on the Ta layer 3A as shown in the figure.
Alloy layer mainly composed of Al, for example, Al-0.1% Cu-0.15% Ti
A two-layer structure (Al-Cu-Ti / Ta) in which an alloy layer was laminated was adopted.

FIG. 2 shows the relationship between the heat treatment time and the sheet resistance in a 450 ° C. heat treatment of a metal wiring layer having the above structure and a conventional metal wiring layer having an Al—Cu—Ti / Ti structure using Ti as a base metal layer. FIG.

From this figure, it can be seen that the Al-Cu of the present invention using Ta as the underlying metal layer
In the -Ti / Ta wiring layer, the sheet resistance hardly increases, and a significant improvement is recognized as compared with the conventional Al-Cu-Ti / Ti wiring using Ti as the base metal layer. In the conventional structure, the thickness of the Ti layer is 200 ° like the Ta layer, and the composition and thickness of the Al—Cu—Ti alloy layer are the same as those of the structure of the present invention.

Further, in the structure of the present invention, the rate of occurrence of disconnection due to stress migration when left at a high temperature of 200 ° C. or more for 2,000 hours is almost 0% as in the conventional structure using Ti for the base metal layer, and is 8 μm. Ambient temperature 250 ° C, current density 2 × 1 when formed in wide wiring width
The electromigration lifetime at 0 ⁶ A / cm ²
As in the case of the conventional structure using Ti as the base metal layer, a value of 3000 hours or more is obtained, which is the same as the case of the wiring width of about 2 μm.

〔Example〕

Hereinafter, the present invention will be specifically described with reference to FIG. 3 for one embodiment.

FIG. 1 shows an Al-Cu-Ti / Ta wiring layer having a two-layer structure having a Ta layer as an underlayer of an Al-Cu-Ti alloy layer according to the present invention; 5 is an example of a MOS semiconductor device used for an upper wiring layer connected to a wiring layer.

In the figure, reference numeral 11 denotes a p ^- type silicon (Si) substrate, 12 denotes an element formation region, 13 denotes a field oxide film, 14 denotes a p-type channel stopper, 15 denotes a gate oxide film, 16 denotes a gate electrode made of poly-Si or the like, 17 Is an n ⁺ -type source region, 18 is an n ⁺ -type drain region, 19 is an oxide film for impurity blocking having a thickness of about 1000 mm, 20 is a first interlayer insulating film made of phosphosilicate glass (PSG) or the like having a thickness of about 8000 mm. , 21A and 21B are substrate contact holes, 22 is a Ti contact layer 22A of about 200 mm thick and 1000 mm thick.
A barrier metal layer composed of a titanium nitride (TiN) non-reactive layer 22B of about 20 nm, a Ta layer 23A having a thickness of about 200 mm and a
1-0.1% Cl-0.15% Ti) Al-Cu-Ti alloy layer 23B having a composition of 23B, a source wiring of a two-layer structure, and 23D is also Ta
A drain wiring having a two-layer structure including a layer 23A and an Al-Cu-Ti alloy layer 23B; 24, a second interlayer insulating film made of PSG or the like having a thickness of about 5000 mm; 25, a contact hole for wiring; About Ta layer 26A and about 5000 mm thick (Al
An upper layer wiring having a two-layer structure including an Al-Cu-Ti alloy layer 26B having a composition of -0.1% Cu-0.15% Ti) is shown.

As shown in this embodiment, an Si substrate 11 (specifically, a source region 17 and a drain region
When forming the lower source wiring 23S and the drain wiring 23D etc. which are in contact with 18), in order to prevent the destruction of the source and drain junctions due to the absorption of Si into the wiring, as shown in FIG. It is desirable to interpose a well-known barrier metal layer 22 composed of a Ti contact layer 22A and a TiN non-reactive layer 22B. Further, in the interlayer connection between the wirings, the barrier metal layer is not necessary. As shown in the drawing, the lower wiring such as the drain wiring 23D is connected via the wiring contact hole 25 of the second interlayer insulating film 24.
The l-Cu-Ti alloy layer 23B and the Ta layer 26A of the upper wiring 26 may be brought into direct contact.

The semiconductor device shown in the above embodiment is formed, for example, by the following method.

That is, in the element forming region 12 defined by the field oxide film 13 and the p-type channel stopper 14 of the p ⁻ type Si substrate 11 according to the normal MOS process, the gate oxide film 15, the gate electrode 16, the n ⁺ type source region 17, After forming a MOS transistor composed of the n ⁺ type drain region 18, the S
i Impurity block oxide film 19 on the exposed surface by thermal oxidation etc.
Then, a first interlayer insulating film 20 made of PSG or the like is formed on the substrate by the CVD method, and the source and drain regions are formed on the interlayer insulating film 20 by ordinary photolithography.
Substrate contact holes 21A and 21B exposing 17 and 18 are formed.

Next, a Ti contact layer 22A is formed on the first interlayer insulating film 20 including the inner surfaces of the contact holes 21A and 21B by argon sputtering, and then a TiN non-reactive layer 22B is formed by reactive sputtering. These become the barrier metal layers 22.

Next, following the formation of the barrier metal layer 22, a Ta layer 23A to be a part of the source and drain wirings is formed on the TiN non-reactive layer 22B by the argon sputtering method, and then the remaining parts of the wirings are also formed by the argon sputtering method. An Al-Cu-Ti alloy layer 23B is formed, and the Al-Cu-Ti alloy layer 23B is formed by ordinary photolithography using a reactive ion etching method using a chlorine (Cl) -based gas as an etching means.
The Cu-Ti alloy layer 23B, the Ta layer 23A, the TiN non-reactive layer 22B, and the Ti contact layer 22A are successively etched, and the TiN non-reactive layer 22B and T
Ta layers 23A and 23A are connected to the source region 17 and the drain region 18 through the barrier metal layer 22 comprising the i-contact layer 12A.
A source wiring 23S and a drain wiring 23D having a laminated structure with the l-Cu-Ti alloy layer 23B are formed.

Next, a second interlayer insulating film 24 made of PSG or the like is formed on the surface on which the source wiring 23S and the drain wiring 23D are formed by the CVD method.
After forming a wiring contact hole 25 by ordinary photolithography, a Ta layer which becomes a part of the upper wiring by argon sputtering is formed on the second interlayer insulating film 24 including the inner surface of the wiring contact hole 25. 26A and the remaining Al-Cu-Ti alloy layer 26B are formed.
The Al-Cu-Ti alloy layer 26B and the Ta layer 26A are successively etched by ordinary photolithography using a reactive ion etching method with a system gas, and are etched through the wiring contact holes 25 of the second interlayer insulating film 24. In the lower wiring, for example, the Al-Cu-Ti alloy layer 23B of the drain wiring 23D,
Ta-layer 26A and Al-Cu-Ti, which are connected by directly contacting Ta-layer 26A
The upper wiring 26 having a laminated structure with the alloy layer 26B is formed. In the metal wiring layer according to the one embodiment formed by such a method, as described in the operation section,
As with the conventional Al-Cu-Ti / Ti wiring layer using Ti as the base metal layer, the disconnection rate due to stress migration at high temperatures is reduced, and the electromigration life when the wiring width is wide is also improved. At the same time as the formation of the high metal wiring, the formation of the high resistance intermetallic compound between the base metal and Al in the high temperature treatment such as the growth of the insulating film almost disappears, and the low resistance metal wiring layer is formed.
The RC delay is reduced, and the speed of the semiconductor device can be increased.

In the metal wiring according to the present invention, the main conductive layer, other than the Al-Cu-Ti alloy layer, Al-Cu alloy layer, Al-Si
An alloy layer or the like can also be applied.

Further, the barrier metal layer interposed in the connection portion with the semiconductor substrate is not limited to the configuration of the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, the resistance to stress migration and the resistance to electromigration of a metal wiring layer can be improved, the wiring resistance can be reduced, the reliability of the metal wiring layer can be improved, and RC can be improved. Delay is reduced.

Therefore, the present invention is effective for improving the reliability and increasing the speed of a highly integrated semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining the principle of the present invention, FIG. 2 is a diagram showing the relationship between heat treatment time and sheet resistance of an Al—Cu—Ti / Ta wiring layer according to the present invention, and FIG. It is a schematic side sectional view of an Example. In the figure, 1 is a semiconductor substrate, 2 is an interlayer insulating film, 3 is a metal (Al) wiring layer, 3A is a Ta layer, 3B is an Al-0.1% Cu-0.15% Ti alloy layer, and 4 is a coating insulating film.

Claims (4)

(57) [Claims] 1. A semiconductor device comprising a two-layer metal wiring layer in which an alloy layer containing aluminum as a main component and both copper and titanium is laminated on a tantalum layer. 2. A semiconductor device according to claim 1, wherein the metal wiring layer having a two-layer structure is electrically connected to a semiconductor base via a barrier metal layer. 3. The semiconductor device according to claim 2, wherein said barrier metal layer comprises a titanium layer and a titanium nitride layer laminated thereon. 4. A semiconductor device according to claim 1, wherein the metal wiring layer having a two-layer structure is directly connected to a lower metal wiring layer via a contact hole.