KR100252915B1 - Metal line of semiconductor device and method for fabricating the same - Google Patents

Metal line of semiconductor device and method for fabricating the same Download PDF

Info

Publication number
KR100252915B1
KR100252915B1 KR1019970072483A KR19970072483A KR100252915B1 KR 100252915 B1 KR100252915 B1 KR 100252915B1 KR 1019970072483 A KR1019970072483 A KR 1019970072483A KR 19970072483 A KR19970072483 A KR 19970072483A KR 100252915 B1 KR100252915 B1 KR 100252915B1
Authority
KR
South Korea
Prior art keywords
layer
thin film
amorphous thin
semiconductor device
substrate
Prior art date
Application number
KR1019970072483A
Other languages
Korean (ko)
Other versions
KR19990052940A (en
Inventor
박종욱
이윤직
서봉석
김정주
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970072483A priority Critical patent/KR100252915B1/en
Publication of KR19990052940A publication Critical patent/KR19990052940A/en
Application granted granted Critical
Publication of KR100252915B1 publication Critical patent/KR100252915B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A wiring structure of a semiconductor device and a forming method thereof are provided to maximize anti-diffusion characteristic and thereby improving reliability of a semiconductor device by inserting TaSi2 between an anti-diffusion film and a silicon. CONSTITUTION: An insulating layer(12) is formed to have a contact hole so that a predetermined portion of a semiconductor substrate(11) should be exposed. A TaSi2 layer(16) is formed on the exposed semiconductor substrate(11) including the insulating layer(12). A Ta-Si-N amorphous thin film(13) is formed on the TaSi2 layer(16) and serve as an anti-diffusion film. A copper wiring layer(14) is formed on the Ta-Si-N amorphous thin film(13). In this case, the TaSi2 layer(16) and the Ta-Si-N amorphous thin film(13) may be deposited in the same chamber. The TaSi2 layer(16) may be formed by co-sputtering Ta and Si, or may be formed through deposition of Ta and then a sintering process.

Description

반도체소자의 배선구조 및 형성방법Wiring Structure and Formation Method of Semiconductor Device

본 발명은 반도체소자에 관한 것으로서, 특히 확산방지막으로 Ta-Si-N 비정질박막을 사용함에 있어서, TaSi2를 콘택층(contact layer)로 사용하여 Ta-Si-N 비정질 확산방지막과 실리콘(Si)과의 반응을 막아주는 동시에 접촉저항을 낮추는 역할을 함으로써, 확산방지막의 성능을 극대화시키는데 적당한 반도체소자의 배선구조 및 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. In particular, in using a Ta-Si-N amorphous thin film as a diffusion barrier, TaSi 2 is used as a contact layer and a Ta-Si-N amorphous diffusion barrier and a silicon (Si) layer. The present invention relates to a wiring structure and a method of forming a semiconductor device suitable for maximizing the performance of a diffusion barrier film by preventing a reaction with the same and lowering a contact resistance.

일반적으로 반도체소자의 고집적화에 따른 금속배선의 폭이 감소함에 따라 배선재료로써 알루미늄보다 비저항이 낮은 구리(Cu)를 사용하고 있다.In general, copper (Cu) having a lower resistivity than aluminum is used as the wiring material as the width of metal wiring decreases due to the high integration of semiconductor devices.

구리를 배선재료로 사용할 경우, 실리콘(Si) 내에서의 확산이 빨라서 실리콘(Si)내로 침투해 들어갈 경우 실리콘 내부의 깊숙한 곳에 불순물층을 형성하여 누설전류를 증가시키게 된다.When copper is used as a wiring material, when diffusion into silicon (Si) is fast and penetrates into silicon (Si), an impurity layer is formed deep inside silicon to increase leakage current.

이로인해 소자의 오동작이 유발시킨다.This causes a malfunction of the device.

따라서, 구리(Cu)와 실리콘(Si)과의 사이에 구리의 확산을 방지하기 위한 확산방지막이 필요하게 되며, 종래에 사용하던 티타늄 나이트라이드(TiN)외에도 새로운 물질들이 연구되도 있다.Therefore, a diffusion barrier layer for preventing the diffusion of copper between copper (Cu) and silicon (Si) is required, and new materials have been studied in addition to titanium nitride (TiN).

최근에는 고온까지 안정한 삼원계 비정질 확산방지막이 주목을 받고 있는데 특히, Ta-Si-N 비정질박막은 비저항이 낮고 비교적 고온까지 안정하여 현재까지 가장 널리 사용되고 있다.Recently, ternary amorphous diffusion barrier films that are stable up to high temperatures have been attracting attention. In particular, Ta-Si-N amorphous thin films have a low specific resistance and are stable to relatively high temperatures and are most widely used to date.

이하, 종래 반도체소자의 배선구조를 설명하기로 한다.Hereinafter, a wiring structure of a conventional semiconductor device will be described.

도 1은 종래 제 1 실시예에 따른 반도체소자의 배선구조를 설명하기 위한 단면도이다.1 is a cross-sectional view for describing a wiring structure of a semiconductor device according to a first embodiment of the present invention.

도 1에 도시한 바와같이, 기판(11)과, 상기 기판(11)의 소정부분이 노출되도록 콘택홀을 갖는 절연층(12)과, 상기 콘택홀을 통해 상기 노출된 기판(11)과 연결되는 Ta-Si-N 비정질박막(13)과, 상기 Ta-Si-N 비정질박막(13)상에 형성된 배선층(14)으로 구성된다.As shown in FIG. 1, a substrate 11, an insulating layer 12 having a contact hole so that a predetermined portion of the substrate 11 is exposed, and a connection with the exposed substrate 11 through the contact hole are provided. The Ta-Si-N amorphous thin film 13 is formed and the wiring layer 14 formed on the Ta-Si-N amorphous thin film 13.

여기서, 상기 Ta-Si-N 비정질박막(13)은 확산방지막으로써, 상기 배선층(14)으로 사용되는 구리(Cu)로부터 불순물이 기판(11)으로 확산되는 것을 방지하는 역할을 한다.Here, the Ta-Si-N amorphous thin film 13 is a diffusion preventing film, and serves to prevent diffusion of impurities from the copper (Cu) used as the wiring layer 14 to the substrate 11.

이어, 도 2는 종래 제 2 실시예에 따른 반도체소자의 배선구조를 도시한 단면도이다.2 is a cross-sectional view illustrating a wiring structure of a semiconductor device according to a second embodiment of the present invention.

도 2에 도시한 바와같이, 기판(11)과, 상기 기판(11)의 소정부분이 노출되도록 콘택홀을 갖는 절연층(12)과, 상기 절연층(12)을 포함하여 노출된 기판(11)상에 형성되는 콘택층(15)과, 상기 콘택층(15)상에 형성된 확산방지막(13)과, 상기 Ta-Si-N 비정질박막(13)상에 형성된 배선층(14)으로 구성된다.As shown in FIG. 2, the substrate 11, the insulating layer 12 having contact holes to expose a predetermined portion of the substrate 11, and the exposed substrate 11 including the insulating layer 12. The contact layer 15 formed on the top layer, the diffusion barrier film 13 formed on the contact layer 15, and the wiring layer 14 formed on the Ta-Si-N amorphous thin film 13 are formed.

여기서, 상기 배선층(14)의 물질은 구리이며, 상기 콘택층(15)은 TiSi2이다.Here, the material of the wiring layer 14 is copper, and the contact layer 15 is TiSi 2 .

상기 Ti-Si2층(15)은 확산방지막으로 사용되는 Ti-Si-N 비정질박막(13)과 기판(11)과의 접합면에서의 접촉저항을 감소시키기 위해 사용한다.The Ti-Si 2 layer 15 is used to reduce the contact resistance at the bonding surface between the Ti-Si-N amorphous thin film 13 used as the diffusion barrier and the substrate 11.

이와같이, Ti-Si2/Ta-Si-N/Cu의 구조는 Ta-Si-N/Cu구조보다 확산방지특성이 더 우수하다.As such, the structure of Ti-Si 2 / Ta-Si-N / Cu has better diffusion preventing characteristics than the structure of Ta-Si-N / Cu.

그러나 상기와 같은 종래 반도체소자 배선구조는 Ta-Si-N 비정질박막이 실리콘과 직접 접촉시 열역학적으로 불안정하여 후속 열처리 과정에서 확산방지특성의 열하를 초래하여 소자의 신뢰성을 저하시키는 요인으로 작용하는 문제점이 있었다.However, the conventional semiconductor device wiring structure as described above has a problem that Ta-Si-N amorphous thin film is thermodynamically unstable in direct contact with silicon, causing deterioration of diffusion preventing properties during subsequent heat treatment, thereby degrading device reliability. There was this.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로써, Ta-Si-N비정질 박막과 실리콘과의 반응성을 열역학적인 계산을 통하여 예측하고, 이를 바탕으로 열처리시 반응을 억제할 수 있는 TaSi2를 확산방지막과 실리콘 사이에 삽입함으로써, 확산방지특성을 극대화시켜 소자의 신뢰성을 향상시키기 위한 반도체소자의 배선구조를 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and predicted the reactivity of Ta-Si-N amorphous thin film with silicon through thermodynamic calculation, based on the TaSi 2 which can suppress the reaction during heat treatment It is an object of the present invention to provide a wiring structure of a semiconductor device for improving the reliability of the device by maximizing the diffusion prevention characteristics by interposed between the diffusion barrier film and the silicon.

도 1는 종래 제 1 실시예에 따른 반도체소자의 배선구조를 설명하기 위한 단면도1 is a cross-sectional view illustrating a wiring structure of a semiconductor device according to a first embodiment of the present invention.

도 2는 종래 제 2 실시예에 따른 반도체소자 배선구조를 설명하기 위한 단면도2 is a cross-sectional view for describing a semiconductor device wiring structure according to a second embodiment of the present invention.

도 3은 본 발명의 반도체소자 배선구조를 설명하기 위한 단면도3 is a cross-sectional view illustrating a semiconductor device wiring structure of the present invention.

도 4a 내지 4c는 본 발명의 반도체소자의 배선형성방법을 설명하기 위한 공정단면도4A through 4C are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

11 : 반도체기판 12 : 절연층11 semiconductor substrate 12 insulating layer

13 : Ta-Si-N 비정질박막 14 : 배선층13: Ta-Si-N amorphous thin film 14: wiring layer

15 : TiSi2층 16 : TaSi2층15: TiSi 2 layer 16: TaSi 2 layer

17 : 포토레지스트 18 : 콘택홀17 photoresist 18 contact hole

상기의 목적을 달성하기 위한 본 발명의 반도체소자의 배선구조는 기판과, 상기 기판의 표면이 소정부분 노출되도록 콘택홀을 갖는 절연층과, 상기 절연층을 포함한 노출된 기판상에 형성된 TaSi2층과, 상기 TaSi2층상에서 확산방지막으로 사용되는 Ta-Si-N 비정질박막과, 상기 Ta-Si-N 비정질박막상에서 배선으로 사용되는 구리층을 포함하여 구성되고, 기판의 소정부분이 노출되도록 콘택홀을 갖는 절연층을 형성하는 공정과, 상기 노출된 기판을 포함한 절연층상에 TaSi2층을 형성하는 공정과, 상기 TaSi2층상에 확산방지막으로 사용될 Ta-Si-N 비정질박막을 형성하는 공정과, 열처리를 실시한 후, 상기 Ta-Si-N 비정질박막상에 배선으로 사용될 구리층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.A wiring structure of a semiconductor device of the present invention for achieving the above object is a TaSi 2 layer formed on a substrate, an insulating layer having a contact hole to expose a predetermined portion of the surface of the substrate, and an exposed substrate including the insulating layer And a Ta-Si-N amorphous thin film used as a diffusion barrier on the TaSi 2 layer, and a copper layer used as a wiring on the Ta-Si-N amorphous thin film, wherein the contact is exposed so that a predetermined portion of the substrate is exposed. Forming an insulating layer having holes, forming a TaSi 2 layer on the exposed layer including the exposed substrate, and forming a Ta-Si-N amorphous thin film to be used as a diffusion barrier on the TaSi 2 layer; After the heat treatment, a step of forming a copper layer to be used as a wiring on the Ta-Si-N amorphous thin film.

이하, 본 발명에 따른 반도체소자의 배선구조를 첨부도면을 참조하여 설명하기로 한다.Hereinafter, a wiring structure of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

먼저, 본 발명은 삼원계 상태도상에서 Ta-Si-N 비정질박막의 조성과 실리콘(Si)사이에는 타이라인(tie line)이 존재할 수 없으므로 상기 두 물질은 열역학적으로 안정하지 못하다.First, in the present invention, since the tie line cannot exist between the composition of the Ta-Si-N amorphous thin film and the silicon (Si) in the ternary state diagram, the two materials are not thermodynamically stable.

따라서, 후속 열처리 과정중에 반응하여 결점을 유발시키게 되는데 본 발명에 따른 TaSi2와 실리콘과의 사이에는 타이라인(tie line)이 존재하게 된다.Therefore, it causes a defect by reacting during the subsequent heat treatment process, and there is a tie line between TaSi 2 and silicon according to the present invention.

따라서, 열적으로 안정하며, 또, 실리사이드이므로 접촉저항도 우수하다.Therefore, it is thermally stable and is excellent in contact resistance because it is silicide.

도 3은 본 발명의 반도체소자 배선구조를 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a semiconductor device wiring structure of the present invention.

도 3에 도시한 바와같이, 반도체기판(11)과, 상기 반도체기판(11)의 표면이 소정부분 노출되도록 콘택홀을 갖는 절연층(12)과, 상기 절연층(12)을 포함한 노출된 기판(11)상에 형성된 TaSi2층(16)과, 상기 TaSi2층(16)상에 형성되어 확산방지층으로 사용되는 Ta-Si-N 비정질박막(13)과, 상기 Ta-Si-N 비정질박막(13)상에 형성된 배선층(Cu)(14)을 포함하여 구성된다.As shown in FIG. 3, an exposed substrate including a semiconductor substrate 11, an insulating layer 12 having contact holes to expose a predetermined portion of the surface of the semiconductor substrate 11, and the insulating layer 12. TaSi 2 layer 16 formed on (11), Ta-Si-N amorphous thin film 13 formed on said TaSi 2 layer 16 and used as a diffusion barrier layer, and said Ta-Si-N amorphous thin film The wiring layer (Cu) 14 formed on 13 is comprised.

여기서, 상기 TaSi2층(16)은 확산방지막으로 사용되는 Ta-Si-N 비정질 박막(13)과 동일한 챔버내에서 증착할 수 있다.Here, the TaSi 2 layer 16 may be deposited in the same chamber as the Ta-Si-N amorphous thin film 13 used as the diffusion barrier.

여기서, 상기 TaSi2층(16)은 Ta와 Si를 Co-스퍼터(sputter)하거나 또는 Ta를 증착한 후, 신터링(sintering)공정을 통해 형성할 수 있다.Here, the TaSi 2 layer 16 may be formed through a sintering process after Co-sputtering Ta and Si or depositing Ta.

상기와 같이 구성된 본 발명의 반도체소자 배선형성방법을 첨부된 도면을 참조하여 설명하기로 한다.The semiconductor device wiring forming method of the present invention configured as described above will be described with reference to the accompanying drawings.

도 4a 내지 4c는 본 발명에 따른 반도체소자 배선형성방법을 설명하기 위한 공정단면도이다.4A through 4C are cross-sectional views illustrating a method of forming a semiconductor device wiring in accordance with the present invention.

도 4a에 도시한 바와같이 반도체기판(11)상에 절연층(12)을 형성한다.As shown in FIG. 4A, an insulating layer 12 is formed on the semiconductor substrate 11.

상기 절연층(12)상에 포토레지스트(17)를 도포한 후, 노광 및 현상공정으로 상기 포토레지스트(17)를 패터닝한다.After the photoresist 17 is applied on the insulating layer 12, the photoresist 17 is patterned by an exposure and development process.

이후, 패터닝된 포토레지스트(17)를 마스크로 이용한 식각공정으로 상기 절연층(12)을 선택적으로 제거하여 반도체기판(11)의 표면이 소정부분 노출되도록 콘택홀(18)을 형성한다.Thereafter, the insulating layer 12 is selectively removed by an etching process using the patterned photoresist 17 as a mask to form a contact hole 18 to expose a portion of the surface of the semiconductor substrate 11.

도 4b에 도시한 바와같이, 상기 포토레지스트(17)를 제거한 후, 절연층(12)을 포함한 노출된 기판(11)상에 TaSi2층(16)을 형성한 후, 패터닝한다.As shown in FIG. 4B, after removing the photoresist 17, a TaSi 2 layer 16 is formed on the exposed substrate 11 including the insulating layer 12 and then patterned.

이후, 상기 TaSi2층(16)을 증착한 챔버내에서 확산방지막으로 사용되는 Ta-Si-N 비정질박막(13)을 증착한다.Thereafter, in the chamber in which the TaSi 2 layer 16 is deposited, a Ta-Si-N amorphous thin film 13 used as a diffusion barrier is deposited.

그리고 열처리 공정을 수행한 다음, 도 4c에 도시한 바와같이, 배선층(14)을 형성한다.After performing the heat treatment process, as shown in FIG. 4C, the wiring layer 14 is formed.

여기서, 상기 Ta-Si-N 비정질박막(13) 대신에 W-Si-N, Ti-Si-N 비정질박막을 형성할 수 있으며, 상기와 같은 비정질박막을 형성하는 경우에도 각각의 비정질박막에 대한 삼원계 상태도를 예측하여 기판(11)과 확산방지막 사이에 형성되는 콘택층을 결정한다.Here, instead of the Ta-Si-N amorphous thin film 13, it is possible to form a W-Si-N, Ti-Si-N amorphous thin film, even in the case of forming the amorphous thin film as described above for each amorphous thin film The contact layer formed between the substrate 11 and the diffusion barrier layer is determined by predicting the ternary state diagram.

이상 상술한 바와같이, 본 발명의 반도체소자 배선구조 및 제조방법은 동일챔버내에서 연속증착하므로 공정을 보다 간략화하고, 확산방지막의 특성을 개선시키고, 기판과의 접촉저항을 감소시키므로 자의 신뢰성을 향상시키는 효과가 있다.As described above, the semiconductor device wiring structure and manufacturing method of the present invention continuously deposit within the same chamber, thereby simplifying the process, improving the characteristics of the diffusion barrier film, and reducing the contact resistance with the substrate, thereby improving self-reliability. It is effective to let.

Claims (5)

기판과,Substrate, 상기 기판의 표면이 소정부분 노출되도록 콘택홀을 갖는 절연층과,An insulating layer having contact holes to expose a predetermined portion of the surface of the substrate; 상기 절연층을 포함한 노출된 기판상에 형성된 TaSi2층과,A TaSi 2 layer formed on the exposed substrate including the insulating layer, 상기 TaSi2층상에서 확산방지막으로 사용되는 Ta-Si-N 비정질박막과,Ta-Si-N amorphous thin film used as the diffusion barrier film on the TaSi 2 layer, 상기 Ta-Si-N 비정질박막상에서 배선으로 사용되는 구리층을 포함하여 구성되는 것을 특징으로 하는 반도체소자의 배선구조.And a copper layer which is used as a wiring on the Ta-Si-N amorphous thin film. 제 1 항에 있어서,The method of claim 1, 상기 Ta-Si-N 비정질박막 대신에 W-Si-N, Ti-Si-N 비정질박막을 적용가능한 것을 특징으로 하는 반도체소자의 배선구조.The W-Si-N, Ti-Si-N amorphous thin film can be applied in place of the Ta-Si-N amorphous thin film. 제 2 항에 있어서,The method of claim 2, 상기 Ta-Si-N, W-Si-N, Ti-Si-N 비정질박막에 대한 각각의 삼원계 상태도를 예측하여 그 하부층의 종류를 결정하는 것을 특징으로 하는 반도체소자의 배선구조.And predicting the ternary state diagrams for the Ta-Si-N, W-Si-N, and Ti-Si-N amorphous thin films to determine the type of the underlying layer. 기판의 소정부분이 노출되도록 콘택홀을 갖는 절연층을 형성하는 공정과,Forming an insulating layer having a contact hole so that a predetermined portion of the substrate is exposed; 상기 노출된 기판을 포함한 절연층상에 TaSi2층을 형성하는 공정과,Forming a TaSi 2 layer on the insulating layer including the exposed substrate, 상기 TaSi2층상에 확산방지막으로 사용될 Ta-Si-N 비정질박막을 형성하는 공정과,Forming a Ta-Si-N amorphous thin film to be used as a diffusion barrier on the TaSi 2 layer; 열처리를 실시한 후, 상기 Ta-Si-N 비정질박막상에 배선으로 사용될 구리층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 배선형성방법.And forming a copper layer to be used as a wiring on the Ta-Si-N amorphous thin film after the heat treatment. 제 4 항에 있어서,The method of claim 4, wherein 상기 TaSi2층과, Ta-Si-N 비정질박막은 동일한 챔버내에서 형성되는 것을 특징으로 하는 반도체소자의 배선형성방법.And wherein the TaSi 2 layer and the Ta-Si-N amorphous thin film are formed in the same chamber.
KR1019970072483A 1997-12-23 1997-12-23 Metal line of semiconductor device and method for fabricating the same KR100252915B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970072483A KR100252915B1 (en) 1997-12-23 1997-12-23 Metal line of semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970072483A KR100252915B1 (en) 1997-12-23 1997-12-23 Metal line of semiconductor device and method for fabricating the same

Publications (2)

Publication Number Publication Date
KR19990052940A KR19990052940A (en) 1999-07-15
KR100252915B1 true KR100252915B1 (en) 2000-05-01

Family

ID=19528303

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970072483A KR100252915B1 (en) 1997-12-23 1997-12-23 Metal line of semiconductor device and method for fabricating the same

Country Status (1)

Country Link
KR (1) KR100252915B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100762863B1 (en) * 2000-06-30 2007-10-08 주식회사 하이닉스반도체 METHOD OF FABRICATING COPPER-LINE UTILIZED Ti-Si-N FILM FOR PREVENTING DIFFUSION

Also Published As

Publication number Publication date
KR19990052940A (en) 1999-07-15

Similar Documents

Publication Publication Date Title
US5656860A (en) Wiring structure for semiconductor device and fabrication method therefor
US5475267A (en) Multilayer interconnection structure for a semiconductor device
JPS63205951A (en) Stable low resistance contact
US5801444A (en) Multilevel electronic structures containing copper layer and copper-semiconductor layers
US6156644A (en) Method for forming interconnects for semiconductor devices using reaction control layers, and interconnects formed thereby
US5846877A (en) Method for fabricating an Al-Ge alloy wiring of semiconductor device
US5851920A (en) Method of fabrication of metallization system
KR19980070785A (en) Semiconductor device and manufacturing method thereof
KR100252915B1 (en) Metal line of semiconductor device and method for fabricating the same
JPH0283978A (en) Semiconductor device
KR20040077421A (en) Method for forming metal wiring in semiconductor device
KR100399066B1 (en) Method for aluminium-alloy in semiconductor device
JP3085745B2 (en) Method for manufacturing semiconductor device
KR0156126B1 (en) Formation method of contact hole in semiconductor device
KR100443363B1 (en) Method of forming metal interconnection in semiconductor device
KR0139599B1 (en) Mechod of forming metal wiring in semiconducotr device
KR100431309B1 (en) Method for forming metal interconnection in semiconductor device
KR100247643B1 (en) A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same
KR20000043055A (en) Method for creating bit line of semiconductor device
KR100252764B1 (en) Method for fabricating multi-layer metallization in semiconductor device
KR100415095B1 (en) Method for manufacturing semiconductor device
US6214723B1 (en) Method of manufacturing a semiconductor device
KR930001896B1 (en) Metal line structure of semiconductor apparatus and building method thereof
KR100338114B1 (en) Method for forming metal film in semiconductor device
JPH11238800A (en) Manufacture of element with multilayer wiring

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091222

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee