JPH03250627A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve electromigration resistance and stress migration resistance by providing metal interconnections of a 2-layer structure in which an aluminum alloy layer containing titanium and copper is laminated on a titanium layer. CONSTITUTION:Metal interconnections 13S, 13D of a 2-layer structure in which an aluminum alloy layer 13b containing titanium and copper is laminated on a titanium layer 13A are provided. Metal interconnection 20 of a structure in which an aluminum layer 18 containing copper is laminated on a titanium layer 17 through aluminum alloy layer 19 containing titanium and copper is provided. After the layer 18 is deposited on the layer 17, it is heat treated, and a step of forming the layer 19 containing the titanium and copper to be sequentially transited to an aluminum alloy composition containing copper from titanium composition by reaction in a boundary of the layer 18 containing the copper to the layer 17 is provided, and the interconnection 20 made of the layer 17, the layer 19 containing the titanium and aluminum and the layer 18 containing the copper is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to semiconductor devices and methods of manufacturing the same, and particularly to improvements in the structure of metal wiring used in semiconductor integrated circuits.

In order to improve the reliability of semiconductor devices by further increasing the electromigration resistance and stress migration resistance of metal wiring, we have developed a two-layer metal wiring structure in which an aluminum alloy layer containing titanium and copper is laminated on a titanium layer. It is constituted by a semiconductor device provided.

Further, the semiconductor device includes a metal wiring having a structure in which an aluminum alloy layer containing copper is laminated on a titanium layer via an aluminum alloy layer containing titanium and copper.

In addition, after depositing an aluminum alloy layer containing copper on the titanium layer, heat treatment is performed, and titanium composition is gradually transitioned from a titanium composition to an aluminum alloy composition containing copper by a 9 reaction at the boundary between the titanium layer and the aluminum alloy layer containing the previous recording. and a step of forming an aluminum alloy layer containing copper, and forming a metal wiring comprising the titanium layer, the aluminum alloy layer containing titanium and copper, and the aluminum alloy layer containing the prerecording. Configure.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same.

In particular, it relates to improvements in the structure of metal wiring used in semiconductor integrated circuits and the like.

2. Description of the Related Art Conventionally, so-called aluminum wiring made of simple aluminum or an alloy mainly composed of aluminum, which has a low specific resistance, has been often used for internal wiring of semiconductor integrated circuit devices.

On the other hand, in order to achieve higher integration of semiconductor integrated circuit devices,
With the continued miniaturization of semiconductor devices, the width of aluminum wiring must also be miniaturized to 1 μm or less, and as a result, disconnections due to electromigration and stress migration are becoming more common. In order to improve the reliability of semiconductor integrated circuits and the like, aluminum wiring with excellent migration resistance is desired.

[Conventional technology]

As a method to improve electromigration resistance and stress migration resistance, aluminum (A
A method has been proposed in which an A1 alloy containing A1 as a main component and to which copper (Cu) and titanium (Ti) are added is used for wiring. In this A1 alloy, when a wiring layer is formed by sputtering, the crystal grains of AI are kept small by the action of TI, and the grain boundaries are filled with Cu, which improves migration resistance when forming fine wiring ( (See Jikai Showa 62114241).

However, it was discovered that this method has the following problems.

(1) If the wire is left at high temperatures of 200°C or higher, it is more likely to cause wire breakage due to stress micration. Figure 3 shows the occurrence of this disconnection failure under stress with respect to the standing time using the leaving temperature as a parameter in an accelerated test conducted on a special test sample with a wiring width D of 8 μm, a wiring thickness D of 7 μm, and a wiring length of 15 m. This is a relational diagram of the microcrash breakage failure rate. From this figure, it can be seen that the rate of breakage failures increases rapidly when left at a high temperature of 200'Cpl.

(2) If the wiring is wide or the electromic is used, disconnection due to noise is likely to occur. Figure 4 shows pure AI wiring and At
-0,1%Cu-0,15%TI alloy wiring with wiring width of 1
The average life in electromigration accelerated tests when changing from μm to 8 μm is pure A with the same wiring width.
It is expressed as a ratio to the average lifespan of I wiring. The test conditions were: storage temperature: 200'C, current density: 3 x 10
'A/cm2. From the results in this figure, the wiring width is 1 to 4.
When the wiring width is 8 μm, the life of Al-0,1%Cu-0,15%T alloy wiring is more than 50 times that of pure AI wiring, or when the wiring width is 8 μm, the lifespan is shorter than that of pure AI. I understand.

[Invention or problem to be solved]

As mentioned above, At-0 is said to have electromigration resistance and stress migration resistance.
, 1% Cu-0, 15% TI alloy also tends to cause disconnection defects due to stress migration when left at high temperatures of 200°C or higher when wiring is constructed using only a single layer of this alloy layer. If the wiring is too wide, there is a problem in that wire breakage is more likely to occur due to electromigration.

Therefore, the present invention provides a metal interconnection that uses an Al-Cu-Ti alloy layer as a main conductive layer and has better electromicrition resistance and stress migration resistance than before, and a method for manufacturing the same, thereby improving the reliability of semiconductor devices. The purpose is to

[Means to solve the problem]

The above problem is solved by a semiconductor device including metal wirings 13S and 13D having a two-layer structure in which an aluminum alloy layer 13B containing titanium and copper is laminated on a titanium layer 1.3A.

Further, the problem is solved by a semiconductor device having a metal wiring 20 having a structure in which an aluminum alloy layer 18 containing copper is laminated on a titanium layer 17 via an aluminum alloy layer 19 containing titanium and copper.

In addition, aluminum alloy layer 1 containing copper on titanium layer F
8 is heat-treated, and an aluminum alloy layer 19 containing titanium and copper is formed at the boundary between the titanium layer 17 and the aluminum alloy layer I8 containing copper, which gradually transitions from a titanium composition to an aluminum alloy composition containing copper by one reaction. The problem is solved by a method for manufacturing a semiconductor device, which includes a step of forming a metal wiring 20 including the titanium layer 17, the aluminum alloy layer 19 containing titanium and copper, and the aluminum alloy layer 18 containing copper.

[Effect]

Table 1 shows the wiring of the Al-Cu-Ti alloy single layer structure and the T
The results of stress migration tests are shown for wiring having a two-layer structure in which an i-layer and an Al-Cu-Ti alloy layer are laminated. The test conditions were a storage temperature of 150°C, 200°C and 125°C.
0°C9 wiring width D is 8 μm, wiring thickness D is 7 μm, and wiring length is 15 m. In addition, the thickness of the T1 layer is 200 to 300
It is about the size of a person.

As shown in this table, in the case of the Al-Cu-Ti alloy single-layer wiring, considerable disconnection failures occurred at the storage temperature of 200°C or higher, whereas the 11-layer and Al-Cu-Ti alloy
In the laminated wiring of the i-alloy layer, no disconnection failure occurred even at a temperature of 200° C. or more. This indicates that stress migration resistance has been significantly improved.

Table 1: Leaving temperature Ti layer Cumulative defective rate (%) ('C)
Leave for 360 hours Leave for 2000 hours 150
Yes 00 150 No 1.2 12.
0200 Yes 00 200 No 7.7 23.
6250 Yes 00 250 No 50 or more 50 or more -F.

Table 2 shows the relationship between the average lifespan due to electromigration and the wiring width for a conventional Al-Cu-Ti alloy single-layer wiring and for a laminated structure of a Ti layer and an Al-Cu-Ti alloy layer according to the present invention. These are the results of an electromigration test shown for metal wiring.

According to this table, if the wiring width is 2 μm, there is no big difference in the electromigration life between the two, but if the wiring width is 8 μm, the average life of conventional Al-CuTi alloy single layer wiring will be significantly reduced. On the other hand, in the laminated wiring structure of the T1 layer and the Al--Cu--Ti alloy layer according to the present invention, there is no decrease in the total thermal life expectancy.

2nd table wiring width Ti layer Test temperature (μm) ('C) 2 Yes 250 2 No 250 8 Yes 250 8 No 250 Current density Average life (A/crn-2) ()I) 2 X 10' 3000 2 X 10' 2500 2 x 1.0' 4000 2

In the present invention, based on the above test results.

The metal wiring is constructed with a laminated structure of a Ti layer and an Al-Cu-Ti alloy layer.
The stress migration resistance and electromigration resistance are significantly improved compared to interconnects having a single-layer alloy structure, and the reliability of semiconductor devices is further improved.

Note that the Al-Cu-Ti alloy layer in the above test sample has a composition of Al-0.1% Cu-0.15% Ti.

Furthermore, instead of the laminated structure of the T1 layer and the Al-Cu-Ti alloy layer, a Ti layer, an Al-Cu-Ti alloy layer and an Al-
It has been shown that stress migration resistance and electromigration resistance can be improved even when the Cu alloy layer is laminated in this order.

In such a structure, an Al-Cu alloy layer is deposited on the Ti layer and then heat-treated, and the Al-Cu alloy gradually changes from the Ti composition to the AI-Cu composition by diffusion at the boundary between the Ti layer and the AI-Cu alloy layer. This can be realized by forming a -Ti alloy layer.

[Embodiment] Two embodiments of the present invention will be specifically described below with reference to FIG.

FIG. 1 shows a metal wiring having a two-layer structure of a Ti layer and an Al-Cu-Ti alloy layer according to the present invention, with a lower layer wiring connected to a semiconductor substrate and an upper layer wiring connected to the lower layer wiring. This is an example of the MO3 type semiconductor device used.

In fig.

l is, for example, a p-type silicon (Sl) substrate.

2 is an element forming area.

3 is a field oxide film.

4 p-type channel stopper.

5 is a gate oxide film.

6. Gate electrode made of poly-Si or the like.

7 is an n++ source region.

8 is an n+ type drain region 9. Oxide film for blocking impurities.

10 is made of phosphosilicate glass (PSG) and has a thickness of 8000 mm.
The first interlayer insulating film is approximately zero.

11A and IIB are the first contact windows.

12 is a Ti contact layer 12A with a thickness of about 200 mm and a titanium nitride (TiN) barrier layer 12 with a thickness of about 1000 mm.
A barrier metal layer consisting of B.

13 is the lower layer wiring.

13S has a two-layer structure consisting of a Ti layer with a thickness of approximately 250 mm and an Al-Cu-Ti alloy layer 13B having a thickness of approximately 5000 mm with a composition of 0Al-0.1% Cu-0.1.5% Ti. The source wiring 130 is the same <Ti layer 13A and Al-Cu-
The drain wiring has a two-layer structure including a Ti alloy layer 13B.

14 is a second interlayer insulating film made of PSG or the like and having a thickness of about 8,000.

I5 is the wiring contact window.

16 is a Ti layer 16A with a thickness of about 250 mm and a thickness of 5000 mm.
The upper layer wiring has a two-layer structure consisting of an AI-Cu-Ti alloy layer 16B having a composition of about 0Al-0.1% Cu-0.15% Ti.

As shown in this embodiment, a Si substrate 1 (specifically, a source region 7 and a drain region 8
) When forming the lower layer source wiring 13S and drain wiring 13D in contact with 81, in order to prevent destruction of the source/drain junction due to suction of 81 into the wiring, 1, for example, is added to the contact portion as shown in the figure. It is desirable to interpose a well-known barrier metal layer 12 consisting of a T1 contact layer 12A and a TiN burr layer 12B.

In addition, in the interlayer connection between wirings, there is no need for the barrier metal layer, and as shown in the figure, the lower wiring 13 is formed through the wiring contact window 15 of the nine interlayer insulating film 14.
The Ti layer 16A of the upper layer wiring 16 may be brought into direct contact with the Al-Cu-Ti alloy layer 13B of the rain wiring 13D.

The semiconductor device shown in the above embodiment is formed by, for example, the following method.

That is, 2 p-type S1 substrate 1 according to the normal MOS process.
to an element formation region 2 defined by a field oxide film 3 and a p-type channel stopper 4.

Gate oxide film 5. Gate electrode6. After forming a MOS transistor consisting of an n-type source region 7 and an n-type drain region 8, an impurity blocking oxide film 9 is formed on the surface of the transistor by thermal oxidation or the like, and then a CVD method is applied to the substrate. A first interlayer insulating film 10 made of PSG or the like is formed, and contact windows 11A and IIB exposing the source region 7 and drain region 8 are formed in this interlayer insulating film 10 by ordinary photolithography.

Next, on the first interlayer insulating film 10 including the inner surfaces of the contact windows 11A and IIB, a Ti contact layer 12A is formed by argon sputtering, and then a TiN897 layer 12B is formed by reactive sputtering.

These become the barrier metal layer 12.

Next, following the formation of the barrier metal layer 12, a Ti layer 13A, which will become part of the source and drain wiring, is formed on the TiN897 layer 12B by argon sputtering. forming an Al-Cu-Ti alloy layer 13B;
The Al-Cu-Ti alloy layers 13B, T
The i layer 13A, the TiN897 layer 12B, and the Ti contact layer 12A are successively patterned, and a TiN layer is formed at the bottom.
The Ti layer 1 has a barrier metal layer 12 consisting of an 897 layer 12B and a Ti contact layer 12A, and is connected to the source region 7 and drain region 8 via this barrier metal layer 12.
3A, a source wiring 13S and a drain wiring 13D having a laminated structure of an Al-Cu-Ti alloy layer 13B are formed.

Next, a second interlayer insulating film 14 made of PSG or the like is formed by CVD on the surface where the source wiring 13s and drain wiring 13D are formed, and a wiring contact window 15 is formed by ordinary photolithography.

On the second interlayer insulating film 14 including the inner surface of the wiring contact window 15, a 71 layer 16A, which will become a part of the upper layer wiring, and an Al-Cu-Ti alloy layer 16B, which will be the remaining part, are formed by argon sputtering, and etching means is applied. The Al-Cu-Ti alloy layer 16B is etched by ordinary photolithography using a reactive ion etching method using a C1-based gas.
, Continuously buttering 71 layers 16A.

Through the wiring contact window 15 of the second interlayer insulating film 14.

For example, the Al-
On the Cu-Ti alloy layer 13B, an upper layer wiring 16 having a laminated structure of Ti#16A and Al-Cu-Ti alloy layer 16B is formed, which connects the 71 layer 16A by directly contacting it.

In the metal wiring according to the above embodiment formed by such a method, as shown in the above-mentioned test results, the function of the lower TI layers 13A and 1.6A allows the upper Al- Cu-Ti alloy layer 1.3B
, 16B due to stress migration or electromigration is prevented.

In addition, the contents of Cu and Ti in the Al-Cu-Ti alloy layer are as follows.

The values are not limited to those in the above embodiments.

FIGS. 2(a) to 2(e) are process-order sectional views showing another embodiment, and these figures will be referred to below.

The process of forming metal wiring on a Si substrate will be explained.

Refer to FIG. 2(a) A thickness 8 made of PSG or the like is formed by CVD on a Si substrate 1.
000 interlayer insulating film lO is formed, and this interlayer insulating film 1
A contact window 11 exposing a region in which wiring to be connected to the substrate 1 is to be formed is formed by normal photolithography on the substrate 1.

Refer to FIG. 2(b) A Ti contact layer with a thickness of 200 layers is formed on the glabella insulating film 10 including the inner surface of the contact window 11 by argon sputtering! 2A is formed, and then a TiN897 layer 12B with a thickness of 1000 layers is formed by reactive sputtering. These become the barrier metal layer 12.

Refer to FIG. 2(c). On the TiN897 layer 12B, a Ti layer 17 with a thickness of 500 layers, which will become a part of the wiring, is formed by argon sputtering. Then, by the same argon sputtering method, a Ti layer 17 of 500 thickness, which will become the remaining part of the wiring, is formed. % Cu is formed to a thickness of 5,000 to 10,000 wafers.

450° in a nitrogen atmosphere or a mixed atmosphere of nitrogen and hydrogen (see Figure 2(d))
Heat treatment is performed for C930 minutes. This heat treatment must be performed at 500° C. or lower so as not to have any adverse effects on the Al-Cu alloy layer 18.

Through this heat treatment, TiJif17 and Al-Cu alloy layer 1
Interdiffusion occurs at the boundary of 8, and the Ti composition changes to AI
An Al-Cu-Ti alloy layer 19 is formed which gradually changes to a -Cu alloy composition.

Refer to FIG. 2(e) The above AI-C was etched by ordinary photolithography using a reactive ion etching method using chlorine-based gas
u alloy layer 18. Al-Cu-Ti alloy layer 19. Ti
The layer 17, the TiN barrier layer 12B, and the Ti contact layer 12A are successively patterned to form a barrier metal layer 12 consisting of the T1 contact layer 12A and the TiN barrier layer 12B at the bottom. Layer 17. Al-Cu-Ti alloy layer 19. Al-
Metal wiring 2 having a laminated structure consisting of a Cu alloy layer 18
form 0.

In this way, metal wiring connected to the SL board j is realized.

Note that when this metal wiring is used as a lower layer wiring and an upper layer wiring is formed on it, there is no need for a barrier metal layer, and a second interlayer insulating film such as a PSG film is formed on the lower layer wiring. After opening the contact window, a Ti layer 17. is formed directly on the lower wiring. AI-Cu-Ti alloy layer 19. A
The upper layer wiring having a laminated structure including the l-Cu alloy layer 18 may be formed by the method described above.

Even in metal wiring formed by such a method,
Lower T1 layer 17. Intermediate Al-Cu-Ti alloy layer 1
9, the upper layer Al-Cu, which is the main conductive layer,
Disconnection due to stress migration or electromigration occurring in the alloy layer 20 is prevented.

Note that the Cu content of the Al--Cu alloy layer 18 is not limited to the value D, 1%, shown in the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, disconnection due to stress migration or electromigration of metal wiring included in a semiconductor device is prevented, so that reliability of semiconductor integrated circuits and the like can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of an embodiment of the present invention. FIGS. 2(a) to 2(e) are process-order sectional views showing another embodiment. FIG. 3 is a diagram showing the relationship between the disconnection defect rate and the leaving time using the leaving temperature of the Al-Cu-Ti alloy wiring as a parameter. FIG. 4 shows the electromigration life of the Al-Cu-Ti alloy wiring. In fig. 1 is a semiconductor substrate, which is a Si substrate, and a p-type Si substrate 2 is an element forming region. 3. Field oxide film. 4, p-type channel stopper 5 is a gate oxide film. 6 is a gate electrode. Reference numeral 7 indicates a semiconductor substrate, which is an n" type source region. Reference numeral 8 indicates a semiconductor substrate, and an n" type drain region 9 is an oxide film for impurity blocking. 10 is a first glabellar insulating film. 11 is the contact window. IA and 11B are the first contact windows. 2 is the barrier metal layer. 2A is a Ti layer, which is a TI contact layer. 2B is a TiN layer and is a TiN barrier layer. 3 is metal wiring, which is lower layer wiring. 3A is a Ti layer. 13B is an Al-Cu-Ti alloy layer. 13s is a metal wiring and is a source wiring. 13D is a metal wiring, which is a drain wiring. 14 is an interlayer insulating film, and a second interlayer insulating film 15 is a wiring contact window. 16 is a metal wiring, which is an upper layer wiring. 16A is a Ti layer. 16B is an Al-Cu-Ti alloy layer. 17 is a Ti layer. 18 is an Al-Cu alloy layer. 19 is A1. -Cu-T1 alloy layer. 20 is a metal wiring tree in August's sharp-throated threat (i9゛゛廖m 連 Ｇ Ｇ Ｇ t')'! '7E 9・l 2 x
”(L 7L 'ifl 'Jff 7'!
Diagram

Claims (1)

[Claims] [1] A metal wiring (13S, 13D) having a two-layer structure in which an aluminum alloy layer (13B) containing titanium and copper is laminated on a titanium layer (13A). semiconductor devices. [2] A metal wiring (20) having a structure in which an aluminum alloy layer (18) containing copper is laminated on a titanium layer (17) via an aluminum alloy layer (19) containing titanium and copper. Characteristic semiconductor devices. [3] Metal wiring according to claim 1 or claim 2 (13S
, 13D, 20) or a semiconductor substrate (7, 8, 1) via a barrier metal layer (12). [4] The barrier metal layer (12) is a titanium layer (12A
) and a titanium nitride layer (12B) laminated thereon. [5] A semiconductor device characterized in that the metal wiring according to claim 1 or 2 is directly connected to the underlying metal wiring (13) via a contact window (15). [6] After depositing the copper-containing aluminum alloy layer (18) on the titanium layer (17), heat treatment is performed to form the titanium layer (17).
) and the aluminum alloy layer (18) containing copper, forming an aluminum alloy layer (19) containing titanium and copper that gradually transitions from a titanium composition to an aluminum alloy composition containing copper by reaction, The titanium layer (17
) and the aluminum alloy layer (19) containing titanium and copper.
and the copper-containing aluminum alloy layer (18).