JP2554347B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device (LSI) and a method for manufacturing the same, and is particularly effective when applied to a semiconductor integrated circuit device having copper wiring and its manufacture. It is about technology.

[Prior art]

Along with the increase in the speed and integration of LSIs, wiring materials with lower resistance and higher reliability than aluminum used conventionally are required. In recent years, copper (specific resistance 1.56 uΩ-cm) has been attracting attention as a wiring material satisfying these requirements. Proceedings of the 47th JSAP Academic Lecture, Paper No. 30
p-N-12, p. 513, September 1986, discusses how to form this copper interconnect. According to this,
After forming a copper film on the titanium nitride (TiN) film formed in advance, and further forming a TiN film on this copper film,
A photoresist pattern having a predetermined shape is formed on this TiN film. Next, the TiN film is etched by reactive ion etching (RIE) using the photoresist pattern as a mask, and then the photoresist pattern is removed. Next, the copper film is formed by etching the copper film by ion milling using the etched TiN film as a mask.

[Problems to be solved by the invention]

However, according to the study by the present inventor, when the photoresist pattern is removed by oxygen plasma treatment, the copper film is oxidized to the lower side of the mask, which makes it difficult to form a copper wiring having a low resistance. was there.

Also, ion milling is physical etching,
Since the selectivity of the etching mask to copper is close to “1”, the etching mask itself is etched and recedes, and the wiring width is reduced. Therefore, fine wiring (1μm-0.1μ
Since the process of m) cannot be performed, there is a problem that the degree of integration is limited.

Also, since the selection ratio of copper to the base is close to "1" as in the above case, a considerable amount of base (1000
(Å or more) Since it is dug, there is a problem that reliability is reduced.

An object of the present invention is to provide a technique capable of improving the speedup and the degree of integration of LSI.

Another object of the present invention is to provide a technique capable of preventing the copper film from being oxidized when the photoresist pattern is removed by the oxygen plasma treatment.

Another object of the present invention is that the line width of the copper wiring is 1 μm to 0.1 μm and its cross section is substantially rectangular, and the wiring interval of the copper wiring is 1 μm.
It is to provide an LSI having a copper wiring of 0.1 μm.

Another object of the present invention is to provide an LSI in which the amount of abrasion due to over-etching of the copper wiring base is almost zero.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of the present invention and the accompanying drawings.

[Means for solving problems]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, a step of forming an anti-oxidation film on a copper film, a step of forming a film for forming an etching mask of the anti-oxidation film on the anti-oxidation film, and a predetermined shape on the film for forming an etching mask. Forming a photoresist pattern, the step of forming an etching mask by etching the film for forming the etching mask using the photoresist pattern as a mask, a step of removing the photoresist pattern by oxygen plasma treatment,
A step of etching the antioxidant film using the etching mask, and a step of anisotropically forming a copper chloride portion by a chlorine (Cl) -based gas plasma in the copper film using the etched antioxidant film as a mask, Forming the copper wiring by evaporating copper chloride by heating the lamp. That is, a copper wiring is formed by reactive ion etching of a copper film at a temperature of 200 to 500 ° C. using a chlorine (Cl) -based etching gas such as Cl ₂ , BCl ₃ , and CCl ₄ .

An LSI having copper wiring, wherein the copper wiring has a line width of 1 μm to 0.1 μm and a cross section of a substantially rectangular shape, and the wiring interval of the copper wiring is 1 μm to 0.1 μm.

In addition, the amount of abrasion due to over-etching of the copper wiring base is almost zero (the amount of abrasion is 1000Å or less).

[Action]

According to the above-mentioned means, since the surface of the copper film is covered with the antioxidant film when the photoresist pattern is removed, the copper wiring is prevented from being oxidized when the photoresist pattern is removed by the oxygen plasma treatment. be able to.

In addition, the copper film, for example, at a temperature of 200 ~ 500 ℃ Cl ₂ , BCl ₃ , C
Since the copper wiring is formed by reactive ion etching using a chlorine-based etching gas such as Cl _{4, the} selectivity to the etching mask is "2" or more, and the receding amount of the etching mask is reduced, resulting in a fine (1 μm ~ 0.1 μm)
Wiring width and spacing are possible.

In addition, the selection ratio of the copper wiring to the base becomes "5" or more, and the amount of the base ground can be reduced to 1000 Å or less.

As a result, the speed and integration of the LSI can be improved and the reliability can be maintained.

〔Example〕

An embodiment in which the present invention is applied to a bipolar LSI will be specifically described below with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

First, the structure of the bipolar LSI according to this embodiment will be described.

FIG. 1 is a sectional view showing a main part of a bipolar LSI according to an embodiment of the present invention.

As shown in FIG. 1, a bipolar LSI according to this embodiment.
2, an n ⁺ type buried layer 2 is provided on the surface of a semiconductor substrate 1 such as ap ⁻ type silicon substrate, and an epitaxial layer 3 of n type silicon is provided on the semiconductor substrate 1. A field insulating film 4 such as a SiO ₂ film is provided on a predetermined portion of the epitaxial layer 3 to separate elements and elements. Below the field insulating film 4, for example, a p ⁺ type channel stopper region 5 is provided. Further, in the portion of the epitaxial layer 3 surrounded by the field insulating film 4, for example, a p-type intrinsic base region 6 and, for example, a p ⁺ -type graft base region 7 are provided. For example, an n ⁺ type emitter region 8 is provided. The emitter region 8, the intrinsic base region 6, and the collector region composed of the epitaxial layer 3 and the buried layer 2 below the intrinsic base region 6 form an npn-type bipolar transistor.

Reference numeral 9 is an n ⁺ -type collector extraction region connected to the buried layer 2. Reference numeral 10 is an insulating film such as, for example, a SiO ₂ film which is provided so as to be continuous with the field insulating film 4. Further, reference numeral 11 is an insulating film such as a Si ₃ N ₄ film. These insulating films 10 and 11 are provided with openings 12a and 12b corresponding to the graft base region 7 and the emitter region 8, respectively. And
A base lead electrode 13 made of a polycrystalline silicon film is connected to the graft base region 7 through the opening 12a, and the emitter region 8 is connected through the opening 12b.
A polycrystalline silicon emitter electrode 14 doped with an n-type impurity such as arsenic is provided thereon. Further, reference numerals 15, 16 and 17 are insulating films such as SiO ₂ film, reference numeral 18 is an insulating film such as Si ₃ N ₄ film, and reference numeral 19 is an insulating film such as PSG film. is there.

Reference numerals 20a, 20b, and 20c are, for example, platinum silicide films (PtS
i ₂ ) a metal silicide film such as the above-mentioned insulating film
The base extraction electrode 13 and the polycrystalline silicon emitter electrode in the openings 21a, 21b, and 21c provided in 17, 18
14 and above the collector take-out region 9. Reference numerals 22a, 22b and 22c are, for example, TiN films.
Then, the first-layer copper wirings 23a, 23b, 23c are provided on the TiN films 22a, 22b, 22c. The metal silicide films 20a, 20b, 20c and the TiN films 22a, 22b, 22c react with the base lead electrode 13, the polycrystalline silicon emitter electrode 14, the collector lead-out region 9 and the copper wirings 23a, 23b, 23c. Can be prevented.
Further, these TiN films 22a, 22b, 22c can improve the adhesion of the copper wirings 23a, 23b, 23c to the underlying insulating film 19. Further, the copper wiring 23a, 23b,
It is known that 23c has an increased resistance due to the diffusion of impurities such as phosphorus (P) and boron (B) from the outside. The TiN films 22a, 22b and 22c prevent diffusion of these impurities. Therefore, it is possible to prevent an increase in wiring resistance due to diffusion of impurities in the underlying insulating film 19 into the copper wirings 23a, 23b, 23c during heat treatment.

Reference numerals 24a, 24b, and 24c are antioxidant films such as TiN films. Further, reference numeral 25 is an impurity diffusion preventing film, which is silicon nitride (SiN) formed by plasma CVD.
Film, SiO film formed by plasma CVD, alumina (Al
₂ O ₃ ) An insulating film such as a film. The TiN films 22a, 22b, 22c
Similarly, the diffusion prevention film 25 allows impurities in the interlayer insulating film 26, which will be described later, to be removed from the copper wirings 23a, 23b and 23c during heat treatment.
It is possible to prevent an increase in wiring resistance due to diffusion into the inside.

Reference numeral 26 is, for example, a first-layer interlayer insulating film such as SiO ₂ film formed by the bias sputtering SiO _2. A TiN film 27, for example, is provided on the interlayer insulating film 26.
A second layer copper wiring 28 is provided on the film 27. The TiN
Similar to the films 22a, 22b and 22c, the TiN film 27 can improve the adhesion of the copper wiring 28 to the underlying interlayer insulating film 26. The copper wiring 28 is the interlayer insulating film 26.
Is connected to the copper wiring 23c through a through hole 26a provided in the. The through hole 26a has a stepwise shape, which can improve the step coverage of the copper wiring 28 in the through hole 26a. Further, reference numeral 29 is an antioxidant film such as a TiN film.

Reference numeral 30 is a second interlayer insulating film composed of, for example, an SiO film formed by plasma CVD, a spin-on-glass (SOG) film, and an SiO film formed by plasma CVD. A TiN film 31, for example, is provided on the interlayer insulating film 30.
A third-layer copper wiring 32 is provided on the iN film 31. This Ti
The N film 31 can improve the adhesion of the copper wiring 32 to the underlying interlayer insulating film 30. This copper wiring 32
Are connected to the copper wiring 28 through through holes 30a provided in the interlayer insulating film 30. The through hole 30a has a step-like shape like the through hole 26a, so that the step coverage of the copper wiring 32 in the through hole 30a can be improved. Further, reference numeral 33 is an antioxidant film such as a TiN film.

Reference numeral 34 is an interlayer insulating film having the same structure as the interlayer insulating film 30. For example, a TiN film 35 is provided on the interlayer insulating film 34, and a fourth-layer copper wiring 36 is provided on the TiN film 35. The TiN film 35 can improve the adhesion of the copper wiring 36 to the underlying interlayer insulating film 34. The copper wiring 36 is connected to the copper wiring 32 through a through hole 34a provided in the interlayer insulating film 34. The through hole 34a is the through hole 26.
Similar to a and 30a, it has a stepwise shape, which can improve the step coverage of the copper wiring 36 in the through hole 34a. Further, the reference numeral 37 is, for example,
It is an antioxidant film such as a TiN film.

Further, reference numeral 38 is a protective film made of, for example, a SiO ₂ film.
An opening 38a is provided in the protective film 38, and, for example, a Cr film 39 is provided on the copper wiring 36 through the opening 38a.
Then, for example, copper (Cu) -tin (Sn) is formed on the Cr film 39.
Bumps 41 made of, for example, lead (Pb) -Sn alloy-based solder are provided via the intermetallic compound layer 40.

The copper wirings 23a, 23b, 23c, the copper wiring 28, the copper wiring 32, and the copper wiring 36 each have a fine wiring width (for example, 1
μm to 0.1 μm) and minute intervals (for example, 1 μm to 0.1 μm)
m).

Further, the cross section of the copper wiring is almost rectangular, and both end portions thereof are corrugated, and the amount of scraping of the base is 1000 Å or less.

By doing so, high integration of the bipolar LSI can be improved and reliability can be maintained.

Moreover, as shown in FIG. 2 (characteristic curve showing temperature dependence of electrical resistance) and FIG. 3 (diagram showing experimental results of electromigration life of Cu wiring, Al wiring, and Al / Cu / Si alloy wiring). In addition, there was a problem with conventional Al wiring or Al / Cu / Si alloy wiring (a) Large electrical resistance, (b)
Since problems such as short electromigration life can be solved, it is possible to improve the speedup of the bipolar LSI and to extend the life.

Next, a method of manufacturing the bipolar LSI configured as described above will be described.

4 to 7 are sectional views for explaining a method of manufacturing a bipolar LSI according to an embodiment of the present invention in the order of steps.

First, the insulating film 19 shown in FIG. 4 is processed by proceeding in the same manner as the manufacturing method described in, for example, Japanese Patent Publication No. 55-27469.
And openings 21a, 21b, and 21c are formed. Next, the opening 2
After forming the metal silicide films 20a, 20b, 20c on the base extraction electrode 13, the polycrystalline silicon emitter electrode 14 and the collector extraction region 9 in 1a, 21b, 21c, respectively, and then, for example, by reactive sputtering, a film thickness of 1000
A TiN film 22 having a thickness of about 2000 Å is formed. Next, this TiN film 22
After forming a copper film 42 having a film thickness of 1 μm, for example, by sputtering, an antioxidant film 24 such as a TiN film having a film thickness of 5000 Å is formed on the copper film 42. As the antioxidant film 24, for example, a boride film of Ti may be used.
Next, a film 43 for forming an etching mask, such as an aluminum (Al) film, which can be selectively etched with respect to the antioxidant film 24, is formed by, eg, sputtering. This membrane
The film thickness of 43 is, for example, 1000Å. The film 43 includes molybdenum (Mo), MoSi ₂ , tungsten (W), W
A film such as Si ₂ or SiO ₂ can also be used. Then, a photoresist pattern 44 having a predetermined shape is formed on the film 43 by photolithography.

Next, for example, chlorine (Cl) -based etching gas (Cl ₂ , B
Cl _3, reactive ion etching using CCl _4, etc.) (RIE)
Thus, the film 43 is etched using the photoresist pattern 44 as a mask. As a result, etching masks 45a, 45b and 45c are formed as shown in FIG.

Next, the photoresist pattern 44 is removed by oxygen plasma treatment to obtain the state shown in FIG. During the oxygen plasma treatment, the surface of the copper film 42 is completely covered with the antioxidant film 24, so that the copper film 42 can be effectively prevented from being oxidized. by this,
Low-resistance copper wirings 23a, 23b, and 23c can be formed as described later.

Next, using the etching masks 45a, 45b, and 45c, for example, a fluorine (F) -based etching gas (CF ₄ , CHF
₃ , the NF ₃ etc.) is used to etch the antioxidant film 24 by reactive ion etching (RIE). As a result, as shown in FIG. 7, the antioxidant films 24a, 24a having a predetermined shape are formed.
4b and 24c are formed.

Next, using these antioxidant films 24a, 24b, and 24c as etching masks, for example, using a Cl-based etching gas (for example, Cl ₂ , BCl ₃ , CCl _4, etc.), the surface layer of copper other than under the mask is chlorided. And The wafer temperature at this time is set to 100 ° C. or lower. Then heat the lamp (about 4kw / wafer per 10
The wafer surface temperature is set to 200 to 500 ° C. to evaporate the copper chloride layer. By repeating this, copper wiring is formed. If the device has sufficient heat resistance (especially for the electrodes), keep the wafer temperature at 200-500 ℃ and continuously
Reactive ion etching may be performed with a system etching gas. Also, except for under the mask, copper is made chloride,
This can be achieved not only by treatment with Cl-based etching gas, but also by implanting Cl with implanter.

During this etching, the etching mask 45
The a, 45b and 45c are also removed by etching. Next, copper wiring 23
Using the a, 23b, and 23c as etching masks, the TiN film 22 is etched by reactive ion etching using, for example, a fluorine (F) -based etching gas to form TiN films 22a, 22b, and 22c having a predetermined shape. To do.

Next, as shown in FIG. 1, a diffusion preventing film 25 and an interlayer insulating film 26 are formed on the entire surface, and then predetermined portions of these are removed by etching to form a through hole 26a. Next, after forming the TiN film 27, the copper film and the anti-oxidation film 29 on the entire surface, these are etched by the same method as the formation of the first-layer copper wirings 23a, 23b, 23c, and the second-layer copper wiring Forming 28. Next, after forming the second-layer interlayer insulating film 30,
A through hole 30a is formed by removing the predetermined portion by etching. Next, after forming a TiN film 31, a copper film and an anti-oxidation film 33 on the entire surface, these are etched by the same method as described above to form a third layer copper wiring 32. Next, after forming the third-layer interlayer insulating film 34, a through hole 34a is formed by etching away a predetermined portion thereof. Next, a TiN film 35, a copper film and an antioxidant film 37 are formed on the entire surface.
Then, these are etched by the same method as described above to form the copper wiring 36 of the fourth layer.

Next, after forming the protective film 38, a predetermined portion thereof is removed by etching to form an opening 38a and the surface of the wiring 36 is exposed at this portion. Next, in this state, a Cr film 39, a Cu film (not shown) and an Au film (not shown) are sequentially formed on the entire surface by, for example, vapor deposition, and then these Au film, Cu film and Cr film are formed.
The film 40 is patterned into a predetermined shape by etching. In this case, the Au film is for preventing oxidation of the Cu film, and the Cu film is for ensuring wettability with the base of the solder bump 41. Incidentally, the Au film,
The Cu film and the Cr film 39 are usually formed by BLM (Ball Limiting Metaliz
ation) is called. Next, a Pb film and a Sn film (not shown) having a predetermined shape are formed so as to cover the Au film, the Cu film, and the Cr film 39 by a lift-off method, for example, and then heat treatment is performed at a predetermined temperature. As a result, the Pb film and Sn film are alloyed to form a substantially spherical Pb-Sn alloy solder bump.
41 is formed. During this alloying, the Sn in the Sn film is
By alloying with Cu in the Cu film, a Cu-Sn-based intermetallic compound layer between the solder bump 41 and the Cr film 39.
40 are formed. In this way, the target bipolar LSI is completed.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various modifications can be made without departing from the spirit of the invention.

For example, as the antioxidant film, a film of a nitride or boride of a metal such as zirconium (Zr), vanadium (V), tantalum (Ta), niobium (Nb) or Cr may be used instead of the TiN film. In this case, Zr and V are used as etching gases for etching these nitride and boride films.
Cl ₂ is the nitride or boride, BCl _3, and CCl ₄ and the like, CF ₄ for nitrides or borides of Ta and Nb, CHF
₃ , SF ₆ , NF _3, etc. are used as C for nitrides or borides of Cr.
O ₂ , CO, Cl ₂ , BCl ₃ , CCl ₄ or the like can be used. Further, as etching masks for these nitride or boride films, Mo, MoSi ₂ , W, WSi ₂ , SiO _2, etc. can be used for Zr, V and Cr nitrides or borides, and Ta and Nb. Al, Si, gallium (Ga), Sn or the like can be used for the nitride or boride of.

Further, as shown in FIG. 5, the antioxidant films 24a, 24b, 24
After forming c, an anti-oxidation film such as TiN film is formed on the entire surface.
By further forming 46 and anisotropically etching this antioxidant film 46 by, for example, reactive ion etching, the side surfaces of the copper wirings 23a, 23b, 23c can be covered with this antioxidant film 46. As a result, the copper wirings 23a, 23b, 23c can be completely covered with the antioxidant films 24a, 24b, 24c, 47, so that the copper wirings 23a, 23b, 23c in the subsequent manufacturing process can be
Can be prevented. Furthermore, in the above-described embodiments, the case where the present invention is applied to an LSI having four layers of copper wiring has been described, but the present invention can be applied regardless of the number of layers of copper wiring. Furthermore, the present invention can be applied to various semiconductor integrated circuit devices having copper wiring other than the bipolar LSI.

[Effects of the Invention] The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to prevent the copper film from being oxidized when the photoresist pattern is removed by the oxygen plasma treatment.

Further, it is possible to reduce the electric resistance and prolong the electromigration life. This allows
The speed and integration of the LSI can be improved, and the reliability can be maintained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a bipolar LSI according to an embodiment of the present invention, FIG. 2 is a characteristic curve diagram showing temperature dependence of electric resistance of wiring, and FIG. 3 is Cu wiring, Al. FIG. 4 is a diagram showing experimental results of electromigration life of wiring and Al / Cu / Si alloy wiring, and FIGS. 4 to 7 are bipolar circuits according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining the method for manufacturing the LSI in the order of steps. In the figure, 1 ... Semiconductor substrate, 6 ... Intrinsic base region, 8 ...
… Emitter region, 13 …… Base extraction electrode, 23a, 23
b, 23c, 28, 32, 36 ... Copper wiring, 24, 24a, 24b, 24c, 2
9, 33, 37, 46 …… Antioxidant film, 41 …… Bump, 42 ……
Copper film, 43 ... Film for forming etching mask, 44 ... Photoresist pattern, 45a, 45b, 45c ... Etching mask.

Claims (20)

(57) [Claims] 1. A semiconductor integrated circuit device having copper wiring, wherein the copper wiring has a line width of 1 .mu.m to 0.1 .mu.m and a cross section of a substantially rectangular shape, and the copper wiring has an interval between 1 .mu.m to 0.1 .mu.m.
A semiconductor integrated circuit device having a thickness of μm. 2. A semiconductor integrated circuit device having copper wiring, wherein the copper wiring has a line width of 1 μm to 0.1 μm and a cross section of a substantially rectangular shape, and the copper wiring has a wiring interval of 1 μm to 0.1 μm.
The semiconductor integrated circuit device is characterized in that it has a thickness of μm and there is almost no amount of abrasion due to over-etching of the copper wiring base. 3. The semiconductor integrated circuit device according to claim 2, wherein the amount of abrasion is 1000 Å or less. 4. The semiconductor integrated circuit device according to claim 1, wherein both end portions of the copper wiring are wavy. 5. The semiconductor integrated circuit device according to claim 1, further comprising four layers of the copper wiring. 6. The semiconductor integrated circuit device according to claim 5, wherein a solder bump is provided on the copper wiring of the fourth layer. 7. The semiconductor integrated circuit device is a bipolar LSI.
Claims 1 to 6 characterized in that
The semiconductor integrated circuit device according to any one of items. 8. A method of manufacturing a semiconductor integrated circuit device having copper wiring, comprising: forming an anti-oxidation film on a copper film; and forming a film for forming an etching mask of the anti-oxidation film on the anti-oxidation film. And a photoresist pattern having a predetermined shape is formed on the etching mask forming film, and the etching mask forming film is etched using the photoresist pattern as a mask to form an etching mask. A step of removing the photoresist pattern by oxygen plasma treatment, a step of etching the antioxidant film using the etching mask, and a chlorine-based gas for the copper film using the etched antioxidant film as a mask. Anisotropic copper chloride is generated by plasma, and copper chloride is evaporated by lamp heating. The method of manufacturing a semiconductor integrated circuit device characterized by comprising a step of forming the copper wiring by Rukoto. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the anti-oxidation film is titanium nitride. 10. The film according to claim 8, wherein the film for forming the etching mask is an aluminum film.
Item 9. A method for manufacturing a semiconductor integrated circuit device according to Item 9 or Item 9. 11. The semiconductor integrated circuit according to claim 8, wherein the etching mask forming film is etched using a chlorine-based etching gas. Device manufacturing method. 12. The manufacturing of a semiconductor integrated circuit device according to claim 8, wherein the antioxidant film is etched using a fluorine-based etching gas. Method. 13. The step of anisotropically forming copper chloride in the copper film by chlorine-based gas plasma, the copper film is, for example, 200.degree.
C1 ₂ at a temperature of ~500 ℃, BC1 _3, CC1 chlorine Patent any one range of paragraph 8 to 12 the preceding claims, characterized in that conducted by reactive ion etching using an etching gas such as ₄ A method of manufacturing a semiconductor integrated circuit device according to item 1. 14. The semiconductor integrated circuit device according to claim 8, wherein lamp annealing is used to heat the semiconductor wafer during the reactive ion etching. Manufacturing method. 15. The lamp annealing condition as set forth in any one of claims 8 to 14, wherein irradiation is performed at a power of about 4 KW per semiconductor wafer for about 10 seconds to 2 minutes. A method for manufacturing the semiconductor integrated circuit device described. 16. The semiconductor according to claim 8, wherein the heating by the lamp annealing and the reactive ion etching by the chlorine-based etching gas are alternately repeated. Manufacturing method of integrated circuit device. 17. The method according to claim 14, wherein the heating by the lamp annealing and the reactive ion etching are performed using a dry etching apparatus which can be repeated simultaneously or alternately. 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1. 18. The method for manufacturing a semiconductor integrated circuit device according to claim 8, further comprising four layers of the copper wiring. 19. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein a solder bump is provided on the copper wiring of the fourth layer. 20. The semiconductor integrated circuit device is a bipolar LS.
Claims 8 to 1, characterized in that it is I
Item 10. A method for manufacturing a semiconductor integrated circuit device according to any one of items 9.