JPH0376031B2 - - Google Patents
Info
- Publication number
- JPH0376031B2 JPH0376031B2 JP9890181A JP9890181A JPH0376031B2 JP H0376031 B2 JPH0376031 B2 JP H0376031B2 JP 9890181 A JP9890181 A JP 9890181A JP 9890181 A JP9890181 A JP 9890181A JP H0376031 B2 JPH0376031 B2 JP H0376031B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- silicon
- semiconductor device
- region
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 2
- -1 tungsten nitride Chemical class 0.000 claims description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910011208 Ti—N Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- PWKWDCOTNGQLID-UHFFFAOYSA-N [N].[Ar] Chemical compound [N].[Ar] PWKWDCOTNGQLID-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は半導体素子、特にシリコン半導体基
板上に活性領域を形成させ、この活性領域の電極
として金電極を用いる半導体素子に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which an active region is formed on a silicon semiconductor substrate and a gold electrode is used as an electrode of the active region.
従来のこの種の金電極構造をもつ半導体素子の
例として、こゝではバイポーラトランジスタを挙
げ、その断面を第１図に示してある。この第１図
において、まずＮ型のシリコン半導体基板１に、
Ｐ型不純物、例えばＢを選択的に拡散してベース
領域２を形成し、またこのベース領域２にＮ型不
純物、例えばリンを選択的に拡散してエミツタ領
域３を形成してから、これらの表面をシリコン酸
化膜４で覆つたのち、各領域２，３の一部にコン
タクトホールを開口させ、白金を蒸着しかつこれ
をシリサイド化してコンタクトホールのオーミツ
ク抵抗領域５を形成し、ついでチタン・タングス
テン層６、金電極７を順次に蒸着し、通常のホト
レジスト工程でこれらを選択的にエツチング除去
したものである。 As an example of a conventional semiconductor element having this type of gold electrode structure, a bipolar transistor is cited here, and a cross section of the bipolar transistor is shown in FIG. In FIG. 1, first, on an N-type silicon semiconductor substrate 1,
A base region 2 is formed by selectively diffusing a P-type impurity such as B, and an emitter region 3 is formed by selectively diffusing an N-type impurity such as phosphorus into the base region 2. After covering the surface with a silicon oxide film 4, a contact hole is opened in a part of each region 2, 3, and platinum is deposited and silicided to form an ohmic resistance region 5 of the contact hole. A tungsten layer 6 and a gold electrode 7 are sequentially deposited and selectively etched away using a normal photoresist process.
こゝでこの従来構成にあつて、Tiはシリサイ
ドと金との間の密着性をよくするために使用さ
れ、かつＷは金−シリコン間のバリア金属として
働くが、Tiは金に２％溶け酸素雰囲気中、300〜
400℃の温度で金表面にチタン酸化物を形成する
ことになり、その後のワイヤボンド工程において
密着不良の原因となるものであつた。 In this conventional configuration, Ti is used to improve the adhesion between silicide and gold, and W acts as a barrier metal between gold and silicon, but Ti is 2% soluble in gold. In oxygen atmosphere, 300~
Titanium oxide was formed on the gold surface at a temperature of 400°C, which caused poor adhesion in the subsequent wire bonding process.
この発明は従来のこのような電極構造不良を改
善するために、前記Ti−Ｗに代えTiNとMoN、
WNなどの化合物を用いたものである。 In order to improve such conventional electrode structure defects, this invention uses TiN, MoN, and
It uses a compound such as WN.
以下、この発明に係わる半導体素子の一実施例
につき、第２図および第３図を参照して詳細に説
明する。 Hereinafter, one embodiment of a semiconductor device according to the present invention will be described in detail with reference to FIGS. 2 and 3.
これらの第２図および第３図において、この実
施例でもまず従来と同様にＮ型のシリコン半導体
基板１にＰ型のベース領域２、このベース領域２
にＮ型のエミツタ領域３を順次に形成させ、かつ
これらの表面にシリコン酸化膜４を被覆し、これ
に開口したコンタクトホールに白金蒸着、シリサ
イド化（窒素雰囲気500℃、10分シンタ−）およ
び王水エツチングにより選択的にオーミツク抵抗
領域５を形成する。 2 and 3, in this embodiment as well, first a P-type base region 2 is formed on an N-type silicon semiconductor substrate 1, and this base region 2 is
N-type emitter regions 3 are sequentially formed on the substrate, and a silicon oxide film 4 is coated on these surfaces, and the contact holes opened therein are subjected to platinum vapor deposition, silicidation (sintering at 500° C. for 10 minutes in a nitrogen atmosphere), and The ohmic resistance region 5 is selectively formed by aqua regia etching.
ついでこれらの表面にホトレジスト膜１１、
こゝではAZ−1350を塗布形成して現像し、コン
タクトホール部８を選択的に形成し、その後、高
周波スパツタ蒸着装置によりアルゴン窒素雰囲気
（５mmTorr）中でTi−Ｗをスパツタし、かつ雰囲
気中の窒素と反応させてTi−Ｎ、Ｗ−Ｎ系化合
物層９を形成させ、かつアルゴン雰囲気中で金電
極１０を蒸着して第２図の構成とし、さらに続い
て前記ホトレジスト膜１１をアセトンで溶融し、
同時に不要な金属を除去して、結果的に第３図に
示すようにシリコン−金間にTi−Ｎ、Ｗ−Ｎ系
の化合物もしくは混合物層９を介在させた構成を
得るのである。 Then, a photoresist film 11 is applied to these surfaces.
Here, AZ-1350 is coated and developed to selectively form contact hole portions 8. Thereafter, Ti-W is sputtered in an argon nitrogen atmosphere (5 mmTorr) using a high frequency sputter evaporation device. is reacted with nitrogen to form a Ti--N, W--N compound layer 9, and a gold electrode 10 is deposited in an argon atmosphere to obtain the structure shown in FIG. melt,
At the same time, unnecessary metal is removed, resulting in a structure in which a Ti--N or W--N compound or mixture layer 9 is interposed between silicon and gold as shown in FIG.
従つてこのように形成されたTi−Ｎは化学的
に安定なために金に溶け難く、金表面でのチタン
酸化物の生成が低下し、Ｗ、Mo系の金属素化物
により金−シリコン間の化学反応も阻止されるこ
とになる。 Therefore, the Ti-N formed in this way is chemically stable and therefore difficult to dissolve in gold, reducing the formation of titanium oxide on the gold surface, and forming a bond between gold and silicon due to W and Mo-based metal oxides. chemical reactions will also be inhibited.
以上詳述したようにこの発明によるときは、金
電極を用いる半導体素子において、シリコン−金
間に窒化チタン（TiN）と金属窒化物（例えば
MoN、WN）の化合物もしくは混合物を介在さ
せたから、シリコン−金間の化学反応を阻止で
き、ワイヤボンド工程での密着不良を解消し得る
だけでなくTiNとすることによる以上のような
改善に加えて、このTiNと化合されるかまたは
混合されるＷもWNとすることにより、これの例
えば電気抵抗率がよいことからTiNとすること
による電気的特性が低下することを防止すること
ができるなどの特長がある。 As detailed above, according to the present invention, titanium nitride (TiN) and metal nitride (e.g.
By interposing a compound or mixture of MoN, WN), it is possible to prevent the chemical reaction between silicon and gold, which not only eliminates poor adhesion during the wire bonding process, but also provides the above-mentioned improvements by using TiN. Therefore, by using WN to be combined or mixed with this TiN, it is possible to prevent the electrical properties from deteriorating due to using TiN, for example, since it has good electrical resistivity. It has the following characteristics.
第１図は従来例による半導体素子の構造を示す
断面図、第２図および第３図はこの発明に係わる
半導体素子の一実施例を工程順に示す断面図であ
る。
１……Ｎ型シリコン半導体基板、２……Ｐ型ベ
ース領域、３……Ｎ型エミツタ領域、４……シリ
コン酸化膜、５……オーミツク抵抗領域、８……
コンタクトホール部、９……Ti−Ｎ、Ｗ−Ｎ系
化合物層、１０……金電極、１１……ホトレジス
ト膜。
FIG. 1 is a cross-sectional view showing the structure of a conventional semiconductor device, and FIGS. 2 and 3 are cross-sectional views showing an embodiment of the semiconductor device according to the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1... N-type silicon semiconductor substrate, 2... P-type base region, 3... N-type emitter region, 4... silicon oxide film, 5... Ohmic resistance region, 8...
Contact hole portion, 9...Ti-N, W-N compound layer, 10...gold electrode, 11...photoresist film.
Claims (1)
せ、この活性領域に金電極を用いる半導体素子に
おいて、シリコンと金電極との間に、窒化チタン
とタングステンの窒化物との化合物、もしくは混
合物層を付在させたことを特徴とする半導体素
子。1. In a semiconductor device in which an active region is formed on a silicon semiconductor substrate and a gold electrode is used in the active region, a compound or a mixture layer of titanium nitride and tungsten nitride is added between the silicon and the gold electrode. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9890181A JPS57211269A (en) | 1981-06-22 | 1981-06-22 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9890181A JPS57211269A (en) | 1981-06-22 | 1981-06-22 | Semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57211269A JPS57211269A (en) | 1982-12-25 |
| JPH0376031B2 true JPH0376031B2 (en) | 1991-12-04 |
Family
ID=14232027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9890181A Granted JPS57211269A (en) | 1981-06-22 | 1981-06-22 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57211269A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59119867A (en) * | 1982-12-27 | 1984-07-11 | Toshiba Corp | Semiconductor device |
| JPS59175763A (en) * | 1983-03-25 | 1984-10-04 | Fujitsu Ltd | Semiconductor device |
| US4566026A (en) * | 1984-04-25 | 1986-01-21 | Honeywell Inc. | Integrated circuit bimetal layer |
| US5227335A (en) * | 1986-11-10 | 1993-07-13 | At&T Bell Laboratories | Tungsten metallization |
| JPS63312613A (en) * | 1987-06-15 | 1988-12-21 | Nec Corp | Single plate capacitor |
| JPS6449243A (en) * | 1987-08-20 | 1989-02-23 | Nec Corp | Semiconductor integrated circuit device |
-
1981
- 1981-06-22 JP JP9890181A patent/JPS57211269A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57211269A (en) | 1982-12-25 |
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