JP3195807B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field-effect transistor having a recess gate structure, and more particularly to a method of manufacturing a field-effect transistor capable of improving reproducibility and uniformity in a manufacturing process .

[0002]

2. Description of the Related Art FIG. 2 shows the structure of a conventional field effect transistor (FET) using a heterojunction as a channel. Usually, in such an FET, an undoped In _0.53 Ga _0.47 As layer and an n-type In _0.52
Undoped In at Heterojunction with Al _0.48 As Layer
High-speed operation is achieved by utilizing a high-mobility two-dimensional electron gas generated on the GaAs layer side.

[0003] Such an FET is composed of a semi-insulating InP substrate 21.
An InAlAs layer 22 serving as a buffer layer, an undoped InGaAs layer 23 serving as a two-dimensional electron gas, an undoped InAlAs layer 24 serving as a spacer layer, an n-type InAlAs layer 25 serving as a carrier supply layer, and an n-type InGaAs serving as a cap layer. The layer 27 is formed by an epitaxial growth method. Next, the Ti layer 28-11 / Pt layer 28
-12 / Source electrode 28- composed of Au layer 28-13
1. After the drain electrode 28-2 is formed, the InGaAs layer 27 and a part of the InAlAs layer 25 in a region to be a gate portion are recessed by etching, and then the gate electrode 26 is formed in the region.

The InGaAs cap layer 27 has a 1 × 1
Since the doping can be performed at a concentration as high as 0 ¹⁹ cm ^{−3 and} the band gap of InGaAs is small, even if the metal is difficult to react with a semiconductor such as Ti or W or WSi, the InGaAs cap may be used. An ohmic connection can be easily established with the layer 27. In order to reduce the resistance of the electrode, the uppermost layer 28-1 is used.
For Au, Au is often used. Pt layer 28 serving as an intermediate layer
Reference numeral -12 denotes a barrier layer for preventing Au in the uppermost layer (Au layer) 28-13 from diffusing into the semiconductor through the Ti layer 28-11, and is a layer provided for increasing the reliability of the electrode. .

In general, the recess etching of the gate portion is performed using a sulfuric acid-based wet etching solution, leaving the InAlAs layer 25 so that the desired drain current of the FET is obtained, and forming the InGaAs cap layer 27 and the InAlAs layer 25.
Is partially etched.

[0006]

The end point of the recess etching is determined by confirming that the drain current has been adjusted to a desired value by the etching. Therefore, as shown in FIG. 3, the source / drain electrode portion must be opened so that the drain current can be monitored. For this reason, portions that come into contact with the etching solution during etching become gate recess portions and source / drain electrodes. As is known in the field of electrochemistry, when an electrolytic solution (etching solution) comes into contact with a metal or a semiconductor, a contact portion has a contact potential difference. Since the gate recess portion and the source / drain electrodes are electrically connected via the channel, a closed circuit is formed with the electrolytic solution as shown in FIG. 4, and a current flows through the semiconductor due to the difference between the semiconductor contact potential difference and the Au contact potential difference. The flow and the recess etching rate are greatly increased. For example etching of GaAs or the ^{like, GaAs + 6p + + 6X -} → Ga 3+ + AsX 6 3- or can proceed in _{^{GaAs + 6p + + 3H 2 O}} → Ga 3+ + H 3 AsO 3 + 3H + reaction scheme are known. Here, p ⁺ is a hole and X ⁻ is an ion. Therefore, when the semiconductor is applied with a positive potential, the hole concentration on the surface increases and the etching is promoted. That is, if the electrode has a positive potential with respect to the electrolytic solution, etching is promoted, and the etching rate depends on the electrode area and the semiconductor area, and it is difficult to control the characteristics of transistors having various shapes on the semiconductor substrate. Become.

According to the present invention, the outermost layer (eg, Au layer) of a conventional source / drain electrode is covered with a metal having a negative potential with respect to an etching solution, so that the resistance of the ohmic electrode is not increased. An object of the present invention is to provide a method for manufacturing a field effect transistor having an ohmic electrode capable of reducing electrochemical effects in recess etching and improving uniformity and reproducibility independent of the shape of the transistor .

[0008]

According to the present invention, there is provided a field effect transformer.
The method of manufacturing a transistor is to form a buffer layer on a semi-insulating substrate.
A first semiconductor layer to be formed and a second semiconductor layer in which a two-dimensional electron gas is formed.
Semiconductor layer, a third semiconductor layer forming a spacer layer, and a carrier.
A fourth semiconductor layer having a first conductivity type, which is a supply layer;
The first conductivity type serving as a cap layer is heavily doped.
Forming a fifth stacked semiconductor layer in sequence,
First and second openings for forming a pole and a drain electrode
A first resist pattern having the following formula:
Forming the first and second openings on the first and second openings.
A first metal layer that is in ohmic contact with the semiconductor layer of No. 5,
The etching liquid capable of dissolving the fifth semiconductor layer 2 has a negative value.
A second metal layer having a potential, and a source electrode
Forming a drain electrode and the first resist
Removing the pattern and then forming a gate region
The surface of the fifth semiconductor layer and the source and drain electrodes;
A second opening having an opening exposing the surface of the second metal layer forming the pole;
After the formation of the resist pattern, the fifth semiconductor layer and the
And a part of the fourth semiconductor layer are etched by etching
And a step of performing the step of:
Gate electrode in the area where a part of the conductor layer is etched away
And a step of forming

The metal layer forming an ohmic junction with the semiconductor may have a single-layer structure or a multilayer structure of two or more layers. The metal forming the metal layer may be a pure metal or an alloy such as a metal silicide. You may.

The metal forming the metal layer having a negative potential with respect to the etching solution may be a pure metal or an alloy.

[0011]

The operation of the present invention will be described below.

Table 1 shows the standard potentials in the surface reactions of the main metals with respect to the hydrogen electrode (reference: "Basic Electrochemistry").
By Kohei Uozaki and Hideaki Kita).

[0013]

[Table 1] The potential of a metal in an etching solution greatly differs depending on the type of the metal and the etching solution. Taking Au and Pt as examples, it can be seen from Table 1 that Au and Pt have a positive potential of 1 to 1.5 V in a sulfuric acid-based etchant. Therefore, when Au or Pt is exposed on the surface of the ohmic electrode, the semiconductor has a positive potential, and the etching is promoted. However, if the electrode surface is Al, C
When covered with a metal such as o, Cr, Ti, Ni, Pt, Mo, and W, the electrode potential becomes negative, and it can be expected that the promotion of etching is suppressed. Therefore, gate recess etching with a small electrochemical effect can be performed by covering, for example, a conventionally used Ti / Pt / Au electrode with these metals having a negative potential with respect to the etching solution.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1a to 1c.

On a semi-insulating InP substrate 11, for example, molecules
Non-doped In by the line epitaxial growth method_0.52
Al_0.48The As layer 12 is made of 2000 °, non-doped In._0.53
Ga_0.47The As layer 13 is made of 300 °_0.52
Al_0.48The As layer 14-1 is formed as follows: 10¹⁸cm^-3To
In doped with Si_0.52Al_0.48As layer 14-2
20 °, undoped In_0.52Al_0.48As layer 14-
3 for 200Å, 4 × 10¹⁸cm^-3Doping with Si
In_0.52Al_0.48250Å, 4 × 1
0¹⁸cm^-3In doped with Si_0.53Ga_0.47A
The s layer 15 is grown successively by 100 ° (FIG. 1a).

After element isolation, a resist pattern having an opening in the ohmic region is formed, and a Ti layer 16-1 is formed as an ohmic electrode at 300.degree.
0 °, the Au layer 16-3 is deposited at 1000 °, the Ti layer 16-4 is deposited at 300 °, and the Ni layer 16-5 is deposited at 200 °, for example, by an evaporation method. The unnecessary metal is lifted off together with the resist to form an ohmic electrode (FIG. 1b).

Next, a resist pattern 17 having an opening on the gate region and the ohmic electrode is formed, and recess etching is performed. The ohmic electrode is contacted with a probe made of a fine needle, and the resistance between the source and the drain and the current value are monitored (FIG. 1c).

After recess etching to a desired drain current, a Ti layer / Pt
If a layer / Au layer is deposited, lifted off and a gate electrode is formed, the FET is completed.

With the structure of this embodiment, the ohmic electrode is exposed to the etching solution during the recess etching, but the surface is covered with a Ni layer, so that the potential difference from the electrolytic solution is as shown in Table 1. Is at most about -0.3 V, and as described in "Problems to be Solved by the Invention",
The InGaAs layer in the gate portion and the I
The effect of accelerating the etching rate of the nAlAs layer is small. Therefore, the recess etching rate does not depend on the gate length and the shape of the FET.
A reproducible FET manufacturing technique is realized.

[0020]

According to the present invention, reproducibility and uniformity in the manufacturing process can be improved.

[Brief description of the drawings]

FIG. 1a is a FET having an ohmic electrode according to an embodiment.
5 is a conceptual side view of the FET, showing a manufacturing process of FIG.

FIG. 1b is a FET having an ohmic electrode according to an embodiment.
5 is a conceptual side view of the FET, showing a manufacturing process of FIG.

FIG. 1c is a FET having an ohmic electrode according to an embodiment.
5 is a conceptual side view of the FET, showing a manufacturing process of FIG.

FIG. 2 is a conceptual side view of a conventional FET.

FIG. 3 is a conceptual diagram illustrating an opening on an ohmic electrode necessary for monitoring a current flowing through a channel during recess etching.

FIG. 4 is a diagram illustrating an electrochemical effect during recess etching.

[Explanation of symbols]

11 semi-insulating InP substrate, 12 non-doped InAlAs layer, 13 non-doped InGaAs layer, 14-1 non-doped InAlAs layer, 14-2 Si-doped InAlAs layer, 14-3 non-doped InAlAs layer, 14-4 Si Doped InAlAs layer, 15Si doped InGaAs layer, 16-1 Ti layer, 16-2 Pt layer, 16-3 Au layer, 16-4 Ti layer, 16-5 Ni layer, 17 resist pattern, 21 semi-insulating InP substrate, 22 InAlAs layer (buffer layer), 23 undoped InGaAs layer, 24 undoped InAlAs layer (spacer layer), 25 n-type InAlAs layer (carrier supply layer), 26 gate electrode, 27 n-type InGaAs layer (cap layer) , 28-11 Ti layer ( Barrier layer), 28-12 Pt layer (intermediate layer), 28-13 Au layer (top layer), 28-1 source electrode, 28-2 drain electrode.

Continuation of the front page (56) References JP-A-1-72558 (JP, A) JP-A-63-221683 (JP, A) JP-A-1-98078 (JP, A) JP-A-1-260861 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21 / 306,21 / 308 H01L 21 / 338,29 / 812

Claims (1)

(57) [Claims] 1. A semiconductor device according to claim 1 , wherein a buffer layer is formed on the semi-insulating substrate.
1st semiconductor layer, 2nd semiconductor in which two-dimensional electron gas is formed
Body layer, third semiconductor layer forming spacer layer, carrier supply
A fourth semiconductor layer having a first conductivity type,
Fifth heavily doped first conductivity type to be the
A step of sequentially forming a plurality of semiconductor layers,
Has first and second openings for forming a rain electrode
Forming a first resist pattern on the fifth semiconductor layer.
Forming the fifth half into the first and second openings.
A first metal layer that is in ohmic contact with the conductor layer;
A negative potential is applied to an etching solution that can dissolve the semiconductor layer 2.
And a source electrode and a drain.
Forming an in-electrode, the first resist pattern
And the fifth half to be a gate region thereafter
Connect the surface of the conductive layer and the source and drain electrodes.
A second register having an opening exposing a surface of the second metal layer;
After forming the stop pattern, the fifth semiconductor layer and the fifth
Recess etching of part of the semiconductor layer of 4 with an etchant
And the fifth and fourth semiconductor layers
Gate electrode is formed in the area where part of the gate is etched away
Field effect transistor, comprising:
Star manufacturing method.