JP2571583B2 - III-V compound semiconductor field effect transistor - Google Patents

Description

The present invention relates to a metal-insulating layer having a III-V compound semiconductor as an active layer, which can handle a large voltage amplitude at a high speed and is suitable for integration. -It relates to a semiconductor field effect transistor (hereinafter referred to as MISFET).

<Conventional technology> III-V group compound semiconductors have high speed, low power consumption,
Currently, its development is being actively carried out to surpass silicon in terms of low noise. For the element formation, MISFETs equivalent to MOSFETs realized by silicon are preferable because they are suitable for high performance and high integration, but GaAs, which is currently in practical use, is difficult to form. MESFETs using key gates are commonly used. However, MESFET has a small voltage amplitude during circuit operation,
It is difficult to say that the device structure is advantageous from the viewpoint of high speed and high integration of the device, such as a small driving capability.

<Problems to be Solved by the Invention> If an MISFET is realized, an electronic device with a high logic amplitude (amplitude of an input voltage), high resistance to noise and power supply voltage fluctuation, and a high degree of integration will be realized. Therefore, indium-based III-V compounds such as InP and InGaAs are suitable as the material. However, these MISFETs have problems in that the interface characteristics are insufficient for practical use, and that characteristic drift occurs during operation.
Further, even if these indium-based III-V compounds are stacked to form a channel at a position distant from the MIS interface, a channel is also formed at the MIS interface due to the combination of the stacked semiconductor layers and the operating voltage. There was a problem that high performance could not be achieved.

The present invention has been made in view of the above points, solves the above technical problems, is stable in operation,
Moreover, it aims to provide a high-performance MISFET.

<Means for Solving the Problems> In order to achieve the above object, a group III-V compound semiconductor field effect transistor of the present invention comprises a III-V compound semiconductor
A group III-V compound semiconductor comprising: a semiconductor stack formed by stacking group compound semiconductors; and a gate insulating layer formed on the semiconductor stack, wherein at least one of the substrate or the semiconductor stack includes In and P. In the field effect transistor, the semiconductor stack includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer in contact with the gate insulating layer includes:
It has a larger energy gap than the second semiconductor layer, the gate voltage is VG, the energy difference between the conduction band of the first semiconductor layer and the second semiconductor layer is ΔEc, and the thickness of the gate insulating layer is d.
1, the relative permittivity of the gate insulating layer is ε1, the thickness of the first semiconductor layer is d2, and the relative permittivity of the first semiconductor layer is ε2, Is set so as to satisfy the following relationship.

<Operation> With the above configuration, a channel is formed at a position distant from the MIS interface, which causes carrier capture and characteristic drift, etc., so that characteristics can be stabilized and energy gap can be measured. Several III- with different Eg
With the combination of the group V compounds, a high-performance transistor using a two-dimensional electron gas or the like suitable for ultrahigh-speed operation can be formed.

Furthermore, the characteristics of the MISFET, such as high driving capability and large logic amplitude, are maintained.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a cross-sectional view showing the structure of an MIS field-effect transistor according to an embodiment of the present invention, and shows a lattice-matched In _1-X G _ax As second semiconductor on a semi-insulating InP substrate 3. Layer 2 (x = 0.4
7), comprising an InP first semiconductor layer 1, a gate insulating layer 4, a gate electrode 5, and source / drain electrodes 6 and 7.

FIG. 2 shows an energy band diagram when a positive voltage is applied to the gate electrode 5. The energy gap (1.35 eV) of InP is larger than that of InGaAs (0.8 eV).
A channel is formed on the InGaAs layer side of the interface between the aAs layer 2 and the InP layer 1.

In this embodiment, InP is, for example, undoped,
It functions as a buffer layer separating the channel and the MIS interface.

Thicknesses of the gate insulating layer 4 and the first semiconductor layer (InP) 16;
Let the relative permittivity and electric field strength be d ₁ , ε ₁ , E ₁ and d ₂ , ε ₂ , E _{2 respectively.}
Assuming that the gate voltage is V _G , V _G = V ₁ + V ₂ + V ₃ E ₁ d ₁ + E ₂ d ₂ (V ₃ is about 0.1 V and should be ignored) ε ₁ E ₁ = ε ₂ It is E _2, And approximately the first semiconductor layer (InP) 1 Is applied.

Here, V ₂ > ΔE _C (ΔE _C : Conduction between InGaAs and InP
In the case of band discontinuity, channels are formed not only at the interface between the first semiconductor layer 1 and the second semiconductor layer 2 but also at the MIS interface, and high-speed performance cannot be obtained. Therefore
In order for no new channel to be formed at the MIS interface, E ₂ d ₂
It is desirable that the condition of <ΔE _C be satisfied.

Therefore Becomes (Here, V _G >> ΔE _C , and most of the voltage is applied to the insulating layer 4).

As is apparent from the above equation (1), the thickness of the first semiconductor layer 1 is preferably at most about 1000 ° or less, depending on the combination of materials and the operating voltage of the element.

For example, when SiO ₂ having a thickness of d ₁ = 1000 ° is used as the gate insulating layer 4, InP is used as the first semiconductor layer 1, and InGaAs is used as the second semiconductor layer 2, ε ₁ (SiO ₂ ) = 3.9, ε ₂
Since (InP) = 12, ΔE _C (InP−InGaAs) = 0.3V, V
If set to about 1V to _G, if you d ₂ 1000 Å. Therefore, the V _G and about 4.5V, the d ₂ 200 Å.

Next, a method of manufacturing the MISFET according to the embodiment of the present invention will be described with reference to FIG.

First, MOCVD, halide VPE on semi-insulating InP substrate 3
Using a method capable of growing high-purity crystals.
The μ InGaAs layer 2 is formed by lattice matching. The crystal layer 2 preferably has a purity as high as n <10 ¹⁶ cm ^-2 , and more preferably n <10 ¹⁵ cm ^-2 , in order to increase the operation speed of the device. Next, an InP layer 1 having a thickness of 100 to 1000 ° is continuously formed. After the gate insulating layer 4 is formed, the process
Performed according to the SFET process. Here, in the case of this structure, the gate insulating layer 4 has a small influence on the drift and the like as compared with a normal MISFET because the MIS interface is away from the channel, but still employs a material and a forming method with as excellent interface characteristics as possible. It is desirable to do. Preferably, SiO ₂ , SiN, PON, PAsO or the like or a composite film thereof is formed and used by using a low-irradiation-damaging low-temperature insulating film forming method such as a photo-CVD method or an ECR plasma CVD method. Next, the gate electrode 5 is formed using Al by EB vapor deposition or W by sputtering, and further processed by photolithography into a shape having a predetermined L / W. Preferably, the source and drain portions of the device are doped with impurities by a method such as Si ⁺ ion implantation to form impurity-doped regions 8, 8, as shown by dotted lines in FIG. Is removed by etching, and electrodes 6, 7 of AuGe or the like are formed by a combination of a vacuum deposition method and a lift-off method to complete the device.

In the embodiment of the present invention, the InP semiconductor layer 1 is undoped. However, if necessary, a doped crystal layer may be used, or a double structure of an undoped layer and a doped layer may be used. good.

In this case, depending on the doping amount N _D, the threshold voltage of the transistor varies about qN _D d ^{2 2} _/ 2ε, which can be used for threshold voltage control.

In the transistor realized by the embodiment of the present invention, the electrons induced in the channel region form a two-dimensional electron gas, and the operation of the enhancement type and the depletion type depends on the thickness and the doping state of the InP semiconductor layer. It is also possible to have

Further, in the present embodiment, an amorphous layer was used as the gate insulating layer, but a wide gap II such as InAlP or GaAlAs was used.
It is also possible to use an IV group compound semiconductor.

Embodiment 2 In the present invention, the first semiconductor layer 1 in contact with the gate insulating layer 4 in FIG. 1 and the second semiconductor layer 2 thereunder may be of a lattice mismatch type. In this case, an interface state is generated between the two layers due to lattice misalignment, but the amount is considered to be on the order of 10 ¹¹ cm ^-2 for a mismatch of 1 to 2%, which can be obtained by a usual method. An amorphous gate insulating layer 4
It is smaller than the number of levels at the interface of the first semiconductor layer 1 of InP. Thus, the allowable range of the mismatch is up to about 1 to 2%. Therefore, in Example 1, an example of InP and In _1-X Ga _X As (X = 0.47) lattice-matched to InP was shown.
In _1-X G of x = 0.3-0.7 considering mismatch of about 2%
a _X As can be adopted. A particularly desirable structure is a composition of 0.3 <x <0.47 with a mismatch of about 1%. In this case, a larger electron mobility can be obtained as compared with a lattice-matched system of x = 0.47, and a film of about 1000 ° or less can be obtained. The thick first semiconductor layer (InP) 1 can be formed on the second semiconductor layer (InGaAs) 2 in the form of a strained lattice by absorbing the misfit by elastic deformation and without generating many lattice defects. In the second embodiment, the subsequent MISFET manufacturing process can be performed in the same manner as in the first embodiment.

Embodiment 3 In this embodiment, the second semiconductor layer 2 is made of InP in FIG. 1, and the first semiconductor layer 1 is made of InAlAs, InAlP, InGaP or the like having a larger energy gap.

These semiconductor laminated structures are excellent in controllability of thin layer growth and can be formed by a method such as MBE, halide VPE, MOCVD, etc., which provide a high-purity film, as in Examples 1 and 2. The first semiconductor layer 1
In the case of In _X Al _{1 -X} As, this composition can be used because lattice matching with InP occurs near x = 0.52. But the first
If the first semiconductor layer 1 shown in the drawing is a thin layer of about 1000 °, even if there is a small mismatch, the thin layer is elastically deformed due to the strain as described above without generating crystal defects, as described above. Can be formed on Therefore, InAlAs of x = 0.3 to 0.4 having lattice irregularity of about 1% can be used. Next, since the first semiconductor layer 1 of the present element is in contact with the amorphous gate insulating layer 4 on the front surface side, the first semiconductor layer 1 has excellent interface characteristics with this.
More preferably, a group III-V compound containing P and P is used. In this case, lattice mismatch with the InP lower layer occurs, but if a lattice mismatch of about 1 to 2% is allowed as in the above-described strained superlattice, In _x Al ₁ -XP can have a value up to about x = 0.3. Can be used. At this time, the energy gap of InAlP is 0.
This is about 4 eV, which can be a suitable material for the first semiconductor layer.

From the same viewpoint, InGa as the second semiconductor layer of the present embodiment is used.
It is clear that strained lattice systems such as As and InAsP can be used.

Also in this embodiment, the MISFET manufacturing process after the formation of the semiconductor lamination is performed according to the first embodiment.

In the above embodiment, the substrate on which the semiconductor stack is formed is an InP bulk substrate, an insulating substrate such as sapphire,
A substrate or the like in which InP is heteroepitaxially formed on i can be used.

FIG. 3 shows an example in which an InP / Si substrate is used. In addition,
GaAs for improving crystallinity between these substrates and the semiconductor stack
Of course, those having various buffer layers such as s, GaP, InGaAs, and InAlAs can also be used. In FIG. 3, 9
Is a buffer layer for epitaxial growth, and 10 is an epitaxy layer.

<Effects of the Invention> As described above, according to the present invention, no channel is formed at the MIS interface even when a III-V compound semiconductor is stacked,
It is possible to improve the stability of element operation, which has been a problem in ISFETs, and to form a high-speed electronic device using a two-dimensional electron gas or the like while maintaining the characteristics of MISFETs that can handle a larger voltage amplitude. In particular, In of Examples 1 and 2
MISFETs containing GaAs are effective for the construction of high-speed logic ICs due to their high mobility characteristics.
MISFETs can be effectively used in the construction of high-output high-speed devices due to the material characteristics (high peak speed, high electric field resistance, etc.) of InP.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of an MIS field effect transistor according to one embodiment of the present invention, FIG. 2 is an energy band diagram when a positive voltage is applied to the device shown in FIG. 1, and FIG. FIG. 9 is a diagram illustrating a structure of an MIS field-effect transistor according to another embodiment of the present invention. 1... First semiconductor layer in contact with the gate insulating layer, 2.
Semiconductor layer, 3 ... substrate, 4 ... gate insulating layer, 5 ... gate electrode, 6, 7 ... source and drain electrodes, 8 ... impurity doped region, 9 ... buffer layer for epitaxy growth, 10 ... Epitaxy layer.

Claims (5)

(57) [Claims] 1. A semiconductor laminate comprising a group III-V compound semiconductor laminated on a substrate, and a gate insulating layer formed on the semiconductor laminate, wherein at least one of the substrate and the semiconductor laminate is provided. Is a III-V compound semiconductor field effect transistor including In and P, wherein the semiconductor stack comprises a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer in contact with the gate insulating layer is a second semiconductor layer. It has a larger energy gap than the semiconductor layer, the gate voltage is VG, the energy difference in the conduction band between the first semiconductor layer and the second semiconductor layer is ΔEc, and the thickness of the gate insulating layer is d.
1, the relative permittivity of the gate insulating layer is ε1, the thickness of the first semiconductor layer is d2, and the relative permittivity of the first semiconductor layer is ε2, A group III-V compound semiconductor field-effect transistor characterized by satisfying the following relationship: 2. The method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are lattice-matched, or the lattice mismatch between the first semiconductor layer and the second semiconductor layer is within 2%. The III-V compound semiconductor field-effect transistor according to claim 1, characterized in that: 3. The III-V compound semiconductor field effect transistor according to claim 1, wherein the thickness of the first semiconductor layer is 1000 ° or less. 4. The semiconductor device according to claim 1, wherein the first semiconductor layer is made of InP, and the second semiconductor layer is made of InGaAs.
Item III-V compound semiconductor field-effect transistor according to Item 2. 5. The first semiconductor layer is _{In 1-X Al X P,} In 1-X Ga X P, In
_1-X Al _X As, and the second semiconductor layer is InP, In _1-X G
_{a X As, InAs 1-X} P III-V group compound semiconductor field effect transistor of the Claims first of claims, or the second term, wherein a is any one of _X.