JP4745652B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a field effect transistor using a heterostructure.

  Compound semiconductors such as gallium nitride (chemical formula GaN) have higher electron mobility than single semiconductors such as silicon (element symbol Si), and can be expected to reduce switching time when used in transistors, etc. Research is ongoing. As a transistor using a compound semiconductor, a transistor using a heterostructure of a compound semiconductor can be given.

  For example, a field effect transistor using a nitride III-V compound semiconductor heterostructure includes a GaN layer formed of gallium nitride (chemical formula GaN) and aluminum gallium nitride (chemical formula AlGaN) having a smaller lattice constant than GaN. ) Is formed (see, for example, Patent Document 1). The source electrode, drain electrode, and gate electrode are formed on the surface of the AlGaN layer opposite to the side in contact with the GaN layer. Since AlGaN has a smaller lattice constant than GaN, in the AlGaN / GaN heterostructure, the piezoelectric effect and spontaneous polarization occur when AlGaN is subjected to lattice strain. As a result, electrons are induced, and a two-dimensional electron gas layer is formed at the heterointerface between the GaN layer and the AlGaN layer. Here, the two-dimensional electron gas layer is an electron that can freely move in a direction parallel to the heterointerface but cannot move in a direction perpendicular to the heterointerface (hereinafter referred to as a two-dimensional electron gas). It is a layer of.

  Thus, in a field effect transistor using a heterostructure, a region in which electrons can flow even when the gate voltage is zero is formed, and electrons are present in that region, so that no gate voltage is applied. However, when a voltage is applied between the source electrode and the drain electrode, a drain current flows. For this reason, a field effect transistor using a hetero structure is called a normally-on type transistor.

FIG. 5 is a diagram schematically illustrating an example of current-voltage characteristics of a field effect transistor using a conventional heterostructure. In FIG. 5, the horizontal axis represents a voltage (hereinafter referred to as source-drain voltage) V _DS (V) applied between the source electrode and the drain electrode, and the vertical axis represents the drain current I _D (mA). Show. In FIG. 5, a curve indicated by reference numeral 61 indicates a case where the gate voltage Vg is minus (−) 6V, a curve indicated by reference numeral 62 indicates a case where the gate voltage Vg is minus (−) 4V, A curve indicated by reference numeral 63 indicates a case where the gate voltage Vg is minus (−) 2V, a curve indicated by reference numeral 64 indicates a case where the gate voltage Vg is 0V, and a curve indicated by the reference numeral 65 indicates a gate voltage. The case where Vg is 2V is shown.

As shown in FIG. 5, in the conventional transistor, even when the gate voltage Vg indicated by reference numeral 64 is zero (0), the drain current _ID flows as the source-drain voltage V _DS increases.

US Pat. No. 5,192,987 (column 4, FIG. 5)

  When considering application to a general circuit, a normally-off type transistor in which no current flows when the gate voltage is zero is preferable to a normal-on type transistor in which a current flows when the gate voltage is zero. This is due to the following reason. In a normally-off type transistor, unless a voltage is applied to the gate, there is no possibility that an overcurrent flows between the source and the drain even if a problem occurs in the circuit. Therefore, the possibility that the transistor itself is broken is very small. On the other hand, in a normally-on type transistor, if the gate voltage becomes zero for some reason, an overcurrent flows between the source and the drain, so that the transistor itself may be destroyed.

The normally-off type transistor is a metal-oxide-semiconductor field effect metal-oxide-semiconductor field effect transistor using silicon (Si).
Transistor (abbreviated as MOSFET) can be realized. FIG. 6 is a diagram schematically illustrating an example of current-voltage characteristics of a normally-off type transistor using silicon (Si). In FIG. 6, as in FIG. 5, the horizontal axis represents the source-drain voltage V _DS (V), and the vertical axis represents the drain current I _D (mA). In FIG. 6, a curve indicated by reference numeral 71 indicates a case where the gate voltage Vg is 0V, a curve indicated by reference numeral 72 indicates a case where the gate voltage Vg is 2V, and a curve indicated by reference numeral 73 is The case where the gate voltage Vg is 4V is shown, the curve indicated by reference numeral 74 indicates the case where the gate voltage Vg is 6V, and the curve indicated by reference numeral 75 indicates the case where the gate voltage Vg is 8V. As shown in FIG. 6, in a normally-off type transistor using Si, when the gate voltage indicated by reference numeral 71 is zero, the drain current _ID flows even when a voltage is applied between the source and the drain. Absent.

  As a normally-off type transistor using Si, for example, an enhancement type n-type MOSFET can be cited. In an enhancement type n-type MOSFET using Si, an n-type source region and a drain region are formed in the vicinity of a surface portion of a p-type semiconductor substrate, and the p-type semiconductor substrate between the source region and the drain region is formed. A gate electrode is formed on the surface portion through an insulating film.

  A similar structure can be formed using a compound semiconductor such as GaN. However, in the case of GaN, it is difficult to form a high-quality p-type substrate, and impurity ions such as Si are used. There is a problem that it is extremely difficult to form an n-type layer in a p-type layer by implantation and diffusion of s. For this reason, a MOSFET having the same configuration as that of a MOSFET using Si, that is, a compound semiconductor MOSFET not using a heterostructure has not been realized.

  Further, although a compound semiconductor MOSFET using a heterostructure has been realized, this MOSFET has a two-dimensional electron gas layer formed at the heterointerface as in the field effect transistor disclosed in the above-mentioned Patent Document 1 or the like. , Normal on type.

  Thus, it is theoretically difficult to fabricate a normal-off type field effect transistor using a compound semiconductor heterostructure.

  An object of the present invention is to provide a semiconductor device such as a normally-off type field effect transistor in which a current does not flow in a state where a gate voltage is not applied despite the inclusion of a semiconductor heterostructure.

The present invention includes a first semiconductor layer composed of a nitride III-V compound semiconductor,
A second semiconductor layer provided in contact with the first semiconductor layer and made of a nitride III-V compound semiconductor;
A source electrode, a gate electrode, and a drain electrode provided on a side opposite to the side in contact with the first semiconductor layer of the second semiconductor layer,
Stress applying means capable of applying stress to the second semiconductor layer, the stress applying means including a piezoelectric effect material layer formed of a material having a piezoelectric effect and provided between the second semiconductor layer and the gate electrode. Prepared,
The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer satisfy a relationship of the following formulas (1) and (2) .
a ₁ ≦ a ₂ (1)
Eg ₁ <Eg ₂ (2)
(Where a ₁ represents the a-axis lattice constant of the semiconductor material constituting the first semiconductor layer, a ₂ represents the a-axis lattice constant of the semiconductor material constituting the second semiconductor layer. Eg ₁ represents the first semiconductor. shows the bandgap of the semiconductor material constituting the layers, Eg ₂ shows the band gap of the semiconductor material of the second semiconductor layer.)

  In addition, the present invention is characterized in that the material having a piezo effect is an oxide having a perovskite structure.

In the present invention, the oxide having a perovskite structure may be BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₉ , LiNbO ₃ and Sr ₂ Nb _2. characterized in that from the group consisting of O ₇ is one or more selected.

  Further, the present invention is characterized in that the material having a piezo effect is a fluoride having a fluorite structure.

The present invention is also characterized in that the fluoride having a fluorite structure is at least one of BaMgF ₄ and BaMnF ₄ .

  Further, the invention is characterized in that the material having a piezo effect is polyvinylidene fluoride.

According to the present invention, the semiconductor device is provided in contact with each other, and stress can be applied to the first semiconductor layer and the second semiconductor layer that satisfy the relationship of the above formulas (1) and (2), and the second semiconductor layer. Stress applying means. As shown in the above formula (1), the a-axis lattice constant a ₂ of the semiconductor material constituting the second semiconductor layer is not less than the a-axis lattice constant a _{1 of} the semiconductor material constituting the first semiconductor layer (a ₁ ≦ a ₂ ). For this reason, in a state where no stress is applied to the second semiconductor layer by the stress applying means, the second semiconductor layer is not subjected to in-plane tensile stress. Therefore, an electron is present at the heterointerface between the first semiconductor layer and the second semiconductor layer. Is not induced, and a two-dimensional electron gas layer is not formed. As shown in the above formula (2), the band gap Eg ₂ of the semiconductor material constituting the second semiconductor layer is larger than the band gap Eg ₁ of the semiconductor material constituting the first semiconductor layer (Eg ₁ <Eg ₂ ). Therefore, in the state where the two-dimensional electron gas layer is not formed, even if electrons are injected from the second semiconductor layer into the first semiconductor layer, the injected electrons flow into the second semiconductor layer from the first semiconductor layer. I can't. That is, no current flows when no stress is applied to the second semiconductor layer by the stress applying means. Here, the in-plane tensile stress is a tensile stress acting in a direction parallel to the heterointerface between the first semiconductor layer and the second semiconductor layer.

  When stress such as in-plane tensile stress is applied to the second semiconductor layer by the stress applying means, electrons are induced at the heterointerface between the first semiconductor layer and the second semiconductor layer, and a two-dimensional electron gas layer is formed. In this state, when electrons are injected from the second semiconductor layer into the first semiconductor layer, the injected electrons can flow from the first semiconductor layer into the second semiconductor layer, so that a current flows.

As described above, the semiconductor device of the present invention includes the heterostructure of the first semiconductor layer and the second semiconductor layer, but the two-dimensional electron gas layer at the heterointerface between the first semiconductor layer and the second semiconductor layer. It is possible to switch between a state in which current flows and a state in which current does not flow by changing between a state in which the current is formed and a state in which the current is not formed. Therefore, for example, when a source electrode, a drain electrode, and a gate electrode are provided on the second semiconductor layer and the gate voltage is zero, stress is not applied to the second semiconductor layer by the stress applying means, and the gate electrode is negatively applied. Alternatively, when applying a positive voltage, a stress is applied to the second semiconductor layer by the stress applying means, so that a current does not flow when no gate voltage is applied. A transistor can be realized.
The stress applying means includes a piezo effect material layer formed of a material having a piezo effect. Here, the material having a piezo effect is a material that generates dielectric polarization when a stress is applied from the outside and deforms when a voltage is applied. When a voltage is applied to the piezo effect material layer, crystal displacement occurs in the piezo effect material layer, and the piezo effect material layer is deformed. Due to the deformation, stress is applied to the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer A two-dimensional electron gas layer is formed at the heterointerface with In a state where no voltage is applied to the piezo effect material layer, no stress is applied to the second semiconductor layer, so that a two-dimensional electron gas layer is not formed at the heterointerface between the first semiconductor layer and the second semiconductor layer. As described above, when a piezo effect material layer is used, whether or not a two-dimensional electron gas layer is formed at the heterointerface can be easily controlled depending on whether or not a voltage is applied to the piezo effect material layer. It is possible to easily and quickly switch between the state where the air flows and the state where the air does not flow. Therefore, the operation speed of the semiconductor device can be improved.
In addition, the semiconductor device includes a source electrode, a gate electrode, and a drain electrode on the opposite side of the second semiconductor layer that is in contact with the first semiconductor layer, and the piezo effect material layer is interposed between the second semiconductor layer and the gate electrode. Provided. Thus, a field effect transistor having the first semiconductor layer as a channel layer is realized. Since the piezo effect material layer is provided between the second semiconductor layer and the gate electrode, a voltage can be applied by the gate electrode. When the gate voltage, which is a voltage applied to the gate electrode, is zero, no voltage is applied to the piezo effect material layer, so that the piezo effect material layer is not deformed and no stress is applied to the second semiconductor layer. For this reason, when the gate voltage is zero, since the two-dimensional electron gas layer is not formed, no current flows even if a voltage is applied between the source electrode and the drain electrode. When a gate voltage is applied to the gate electrode, a voltage is applied to the piezo effect material layer, and the piezo effect material layer is deformed. Therefore, stress is applied to the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer A two-dimensional electron gas layer is formed at the heterointerface. When a voltage is applied between the source electrode and the drain electrode in this state, a current flows.
When the voltage is applied to the piezo effect material layer using the gate electrode in this way, the piezo effect material layer required when the electrode for applying the voltage to the piezo effect material layer is provided separately from the gate electrode. Since a means for synchronizing the application of the voltage and the application of the gate voltage to the gate electrode is not required, the device configuration can be simplified. In addition, since synchronization is not lost, it is possible to prevent voltage from being applied to the piezo effect material layer when the gate voltage is zero, and to prevent overcurrent from flowing between the source electrode and the drain electrode. it can. Therefore, it is possible to further suppress the destruction of the semiconductor device due to the overcurrent as compared with the case where an electrode for applying a voltage to the piezoelectric effect material layer is provided separately from the gate electrode.
The semiconductor material constituting the first semiconductor layer and the second semiconductor layer is preferably a nitride III-V compound semiconductor. Since nitride-based III-V compound semiconductors exhibit higher electron mobility than silicon and the like, by using a nitride-based III-V compound semiconductor, for example, the switching time in a field effect transistor is shortened, The responsiveness of the semiconductor device can be improved. Accordingly, power loss can be suppressed and power utilization efficiency can be greatly improved, so that energy saving and downsizing of the semiconductor device can be achieved.

  According to the invention, the material having a piezo effect is preferably an oxide having a perovskite structure. An oxide having a perovskite structure exhibits a remarkable piezo effect, and can efficiently convert an applied voltage (hereinafter simply referred to as an applied voltage) into crystal displacement. Therefore, by using an oxide having a perovskite structure as a material having a piezo effect, the voltage applied to the piezo effect material layer can be efficiently converted into a stress applied to the second semiconductor layer. Whether or not a two-dimensional electron gas layer is formed at the heterointerface between the layer and the second semiconductor layer can be efficiently controlled.

In addition, according to the present invention, the material having a piezo effect is, among oxides having a perovskite structure, BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti _3. One or more selected from the group consisting of O ₉ , LiNbO ₃ and Sr ₂ Nb ₂ O ₇ are preferred. These compounds exhibit a particularly remarkable piezo effect and can convert the applied voltage into crystal displacement more efficiently. Therefore, by using these compounds, the state in which the two-dimensional electron gas layer is formed and the state in which the two-dimensional electron gas layer is not formed can be switched with a smaller voltage, so that the power consumption of the semiconductor device can be reduced. it can.

According to the present invention, the material having a piezo effect is preferably a fluoride having a fluorite structure, and more preferably, at least one of BaMgF ₄ and BaMnF ₄ . Fluorides having a fluorite structure, particularly BaMgF ₄ and BaMnF ₄ , like the oxide having a perovskite structure, exhibit a remarkable piezo effect and can efficiently convert the applied voltage into crystal displacement. Therefore, by using a fluoride having a fluorite structure as a material having a piezo effect, preferably at least one of BaMgF ₄ and BaMnF ₄ , an applied voltage to the piezo effect material layer is applied to the second semiconductor layer. Since the stress can be efficiently converted to the applied stress, the presence / absence of the formation of the two-dimensional electron gas layer at the heterointerface between the first semiconductor layer and the second semiconductor layer can be efficiently controlled.

  According to the present invention, the material having a piezo effect is preferably polyvinylidene fluoride. By using polyvinylidene fluoride, a piezo effect material layer can be formed at a lower temperature than when an inorganic material such as an oxide is used. Therefore, changes in characteristics of the first semiconductor layer and the second semiconductor layer due to heating, for example, changes in the band gap, can be suppressed, so that malfunction of the semiconductor device can be prevented and reliability can be improved.

  FIG. 1 is a cross-sectional view showing a simplified configuration of a semiconductor device 1 according to an embodiment of the present invention. A semiconductor device 1 exemplified as the present embodiment is a field effect transistor 1. The semiconductor device 1 includes a substrate 11, a buffer layer 12, a channel layer 13 that is a first semiconductor layer, a barrier layer 14 that is a second semiconductor layer, a piezoelectric effect film layer 15 that is stress applying means, a source electrode 16, and a drain electrode 17. And the gate electrode 18.

  The buffer layer 12, the channel layer 13, and the barrier layer 14 are sequentially stacked in this order on the surface portion on one side in the thickness direction of the substrate 11. The channel layer 13 is provided so as to be in contact with the barrier layer 14 at one surface portion in the thickness direction and in contact with the buffer layer 12 at the other surface portion. The channel layer 13 and the barrier layer 14 form a heterojunction. A piezoelectric effect material layer 15, a source electrode 16, and a drain electrode 17 are provided on the surface portion of the barrier layer 14 opposite to the side in contact with the channel layer 13. A gate electrode 18 is provided on the surface portion of the piezoelectric effect material layer 15 opposite to the side in contact with the barrier layer 14. That is, the piezo effect material layer 15 is provided between the barrier layer 14 and the gate electrode 18, and a voltage can be applied by the gate electrode 18.

  The source electrode 16, the drain electrode 17, and the gate electrode 18 are provided apart from each other. The piezo effect material layer 15 is provided between the source electrode 16 and the drain electrode 17. In the present embodiment, the piezo effect material layer 15 is in contact with the source electrode 16 and the drain electrode 17 so as to cover the entire remaining portion of the barrier layer 14 except the portion where the source electrode 16 and the drain electrode 17 are formed. Provided.

The channel layer 13 and the barrier layer 14 are formed so as to satisfy the relationship of the following formulas (1) and (2).
a ₁ ≦ a ₂ (1)
Eg ₁ <Eg ₂ (2)

Here, a ₁ represents the a-axis lattice constant of the semiconductor material constituting the channel layer 13 (hereinafter also simply referred to as the a-axis lattice constant of the channel layer 13). a ₂ represents the a-axis lattice constant of the semiconductor material constituting the barrier layer 14 (hereinafter also referred to as the a-axis lattice constant of the barrier layer 14). Eg ₁ indicates a band cap (hereinafter also referred to as a band gap of the channel layer 13) of a semiconductor material constituting the channel layer 13. Eg ₂ indicates the band gap of the semiconductor material constituting the barrier layer 14 (hereinafter also referred to as the band gap of the barrier layer 14).

  The a-axis lattice constant is a lattice constant in the a-axis direction of a crystal lattice such as a wurtzite structure taken by a GaN-based semiconductor. Note that the values of the a-axis lattice constant and the band gap in this specification are values in the bulk state, that is, the unstrained state, unless otherwise specified. The values of these a-axis lattice constants and band gaps are described in, for example, Isamu Akasaki “Advanced Electronics I-1 III-V Group Compound Semiconductor” (Hafukan Co., Ltd., published on October 30, 2002, the fourth edition, 330) ˜page 331). The a-axis lattice constant can also be obtained by depositing a target semiconductor material on the substrate so as to cause a lattice relaxation due to dislocation, and analyzing the obtained semiconductor film by an X-ray diffraction method. The band gap can be obtained by analyzing a semiconductor film formed in the same manner as when measuring the a-axis lattice constant by a photoluminescence method such as a microphotoluminescence method.

When the a-axis lattice constant a ₂ of the barrier layer 14 is smaller than the a-axis lattice constant a _{1 of the} channel layer 13 (a ₁ > a ₂ ), the barrier layer 14 receives an in-plane tensile stress to induce electrons, and the channel A two-dimensional electron gas layer is formed at the interface between the layer 13 and the barrier layer 14.

In the present embodiment, the a-axis lattice constant a ₂ of the barrier layer 14 is not less than the a-axis lattice constant a ₁ of the channel layer 13 (a ₁ ≦ a ₂ ) as shown in the above formula (1). The barrier layer 14 is not subjected to in-plane tensile stress acting in a direction parallel to the interface with the channel layer 13. For this reason, in the state where no external force is applied, electrons are not induced at the heterointerface between the channel layer 13 and the barrier layer 14.

Specifically, when the a-axis lattice constant a ₂ of the barrier layer 14 is larger than the a-axis lattice constant a _{1 of the} channel layer 13 (a ₁ <a ₂ ), the barrier layer 14 receives in-plane compressive stress. Holes are induced. When the a-axis lattice constant a ₂ of the barrier layer 14 is equal to the a-axis lattice constant a _{1 of the} channel layer 13 (a ₁ = a ₂ ), the barrier layer 14 is not subjected to in-plane tensile stress or in-plane compressive stress. Therefore, neither electrons nor holes are induced. Here, the in-plane compressive stress is a compressive stress acting in a direction parallel to the heterointerface between the channel layer 13 and the barrier layer 14.

Thus, in the state where no external force is applied, electrons are not induced at the interface between the channel layer 13 and the barrier layer 14, and a two-dimensional electron gas layer is not formed. If the two-dimensional electron gas layer is not formed, the band gap Eg ₂ of the barrier layer 14 is larger than the band gap Eg ₁ of the channel layer 13 (Eg ₁ <Eg ₂ ) as shown in the above formula (2). Even if a voltage is applied between the source electrode 16 and the drain electrode 17, no drain current flows.

  In the present embodiment, the piezoelectric effect material layer 15 is provided in contact with the barrier layer 14. Since the piezo effect material layer 15 is formed of a material having a piezo effect (hereinafter also referred to as a piezo material), which will be described later, it can be deformed by applying a voltage, and stress can be applied to the barrier layer 14 by the deformation. Specifically, when a voltage is applied to the gate electrode 18, a voltage is applied to the piezo effect material layer 15, crystal displacement occurs in the piezo effect material layer 15, and the piezo effect material layer 15 is deformed, and thereby the barrier layer 14. Stress such as in-plane tensile stress is applied to the surface.

  As described above, when a voltage is applied to the piezoelectric effect material layer 15 in a state where electrons are not induced or holes are induced, and a stress such as in-plane tensile stress is applied to the barrier layer 14, the barrier layer 14 As a result, strain is generated and electrons are induced at the interface between the channel layer 13 and the barrier layer 14 to form a two-dimensional electron gas layer. As a result, a drain current can flow, and when a voltage is applied between the source electrode 16 and the drain electrode 17, the drain current flows.

  Since the voltage applied to the gate electrode 18 (hereinafter referred to as the gate voltage) is zero and no voltage is applied to the piezo effect material layer 15, the piezo effect material layer 15 is not deformed. No stress is applied. This state is a state in which the aforementioned external force is not applied. In this state, since a two-dimensional electron gas layer is not formed at the heterointerface, the drain current can be applied even if a voltage is applied between the source electrode 16 and the drain electrode 17. Does not flow.

  As described above, the semiconductor device 1 according to the present embodiment includes the heterostructure of the channel layer 13 and the barrier layer 14, but the two-dimensional electron gas layer is present at the heterointerface between the channel layer 13 and the barrier layer 14. Since it can be changed into two states, a state where it is formed and a state where it is not formed, it is possible to switch between a state where current flows and a state where current does not flow. Therefore, a normal-off type field effect transistor can be obtained as the semiconductor device 1. As a result, it is possible to prevent an overcurrent from flowing between the source electrode 16 and the drain electrode 17 when the gate voltage is zero, and to suppress the breakdown of the semiconductor device 1 due to the overcurrent.

  In the present embodiment, since stress is applied to the barrier layer 14 by the piezo effect material layer 15, the stress acting on the barrier layer 14 is changed depending on whether a voltage is applied to the piezo effect material layer 15, Whether or not a two-dimensional electron gas layer is formed at the heterointerface between the channel layer 13 and the barrier layer 14 can be controlled. Therefore, the switching operation between the state in which the drain current flows (hereinafter also referred to as the conduction state) and the state in which the drain current does not flow (hereinafter also referred to as the cutoff state) can be easily controlled. Further, since it is possible to quickly switch between a conduction state in which the drain current flows and a cut-off state in which the drain current does not flow, the switching time, which is the time required for switching between the passage state and the cut-off state, is shortened, and the semiconductor device 1 The operation speed can be improved.

  In the present embodiment, since a voltage is applied to the piezo effect material layer 15 by the gate electrode 18, it is not necessary to separately provide an electrode for applying a voltage to the piezo effect material layer 15. When the gate voltage is zero, that is, when no voltage is applied to the gate electrode 18, no voltage is applied to the piezo effect material layer 15. When a voltage is applied to the gate electrode 18, a voltage is applied to the piezo effect material layer 15. Will be. When the voltage is applied to the piezo effect material layer 15 using the gate electrode 18 as described above, the voltage is applied to the piezo effect material layer 15 in synchronization with the application of the voltage to the gate electrode 18. Therefore, a means for synchronizing the application of the voltage to the piezoelectric effect material layer 15 and the application of the gate voltage to the gate electrode 18 becomes unnecessary. Therefore, the apparatus configuration can be simplified as compared with the case where an electrode for applying a voltage to the piezoelectric effect material layer 15 is provided separately from the gate electrode 18.

  In addition, since the application of the voltage to the gate electrode 18 and the application of the voltage to the piezo effect material layer 15 are not synchronized, the voltage is applied to the piezo effect material layer 15 when the gate voltage is zero. This prevents the overcurrent from flowing between the source electrode 16 and the drain electrode 17 more reliably. Therefore, as compared with the case where an electrode for applying a voltage to the piezoelectric effect material layer 15 is provided separately from the gate electrode 18, the breakdown of the semiconductor device 1 due to overcurrent can be further suppressed.

The difference between the a-axis lattice constant a ₂ of the a-axis lattice constant a ₁ and a barrier layer 14 of the channel layer 13, is preferably small. Specifically, the value (a ₂ −a ₁ ) obtained by subtracting the a-axis lattice constant a ₁ of the channel layer 13 from the a-axis lattice constant a ₂ of the barrier layer 14 is preferably 0.002 nm or less. As a result, a two-dimensional electron gas layer can be formed at the interface between the channel layer 13 and the barrier layer 14 with a smaller voltage, and the field effect transistor 1 that is the semiconductor device 1 can be operated (turned on). The power consumption of the semiconductor device 1 can be reduced.

The value (Eg ₂ −Eg ₁ ) obtained by subtracting the band gap Eg ₁ of the channel layer 13 from the band gap Eg ₂ of the barrier layer 14 is preferably 0.05 eV or more. As a result, the two-dimensional electron gas can be confined at the heterointerface between the channel layer 13 and the barrier layer 14.

  The buffer layer 12 provided between the channel layer 13 and the substrate 11 is provided to prevent the occurrence of stacking faults at the interface between the substrate 11 and the channel layer 13. If the channel layer 13 is formed directly on the surface of the substrate 11 without providing the buffer layer 12, the crystal structure of the material constituting the substrate 11 is different from the crystal structure of the semiconductor material constituting the channel layer 13. There is a possibility that lattice distortion called stacking fault may occur in the vicinity of the interface between and the channel layer 13. When stacking faults occur, carriers such as electrons are scattered, and the carrier transport performance may be reduced. Therefore, it is preferable to provide the buffer layer 12 between the substrate 11 and the channel layer 13. By providing the buffer layer 12, it is possible to prevent the occurrence of stacking faults, so that it is possible to realize the semiconductor device 1 that prevents carrier scattering due to stacking faults and has excellent carrier transport performance.

  Examples of the material of the substrate 11 include sapphire, silicon (chemical formula Si), gallium nitride (chemical formula GaN), aluminum nitride (chemical formula AlN), silicon carbide (chemical formula SiC), and zinc oxide (ZnO). The thickness of the substrate 11 is, for example, 300 μm.

  The buffer layer 12 is made of, for example, a semiconductor material. The semiconductor material constituting the buffer layer 12 is formed on the substrate 11 so as to prevent the occurrence of stacking faults near the interface between the buffer layer 12 and the substrate 11 and near the interface between the buffer layer 12 and the channel layer 13. The material is appropriately selected according to the material and the type of semiconductor material constituting the channel layer 13.

  Examples of the semiconductor material constituting the buffer layer 12, the channel layer 13, and the barrier layer 14 include III-V group compound semiconductors such as gallium nitride (GaN) and gallium arsenide (chemical formula GaAs), and II such as zinc sulfide (chemical formula ZnS). It is preferable to use a compound semiconductor such as a -VI group compound semiconductor, and among these, it is more preferable to use a nitride-based III-V group compound semiconductor. Since compound semiconductors, particularly nitride-based III-V compound semiconductors, exhibit higher electron mobility than single semiconductors such as silicon (Si), the buffer layer 12, the channel layer 13 and the barrier are formed by these semiconductors. By forming the layer 14, the switching time can be shortened and the responsiveness of the semiconductor device 1 can be improved. As a result, power loss can be suppressed and power utilization efficiency can be greatly improved, so that energy saving and miniaturization of the semiconductor device 1 can be achieved.

  In addition, a compound semiconductor is particularly suitable as a semiconductor material constituting the channel layer 13 and the barrier layer 14 because the a-axis lattice constant and the band gap can be easily adjusted.

  Here, the nitride III-V compound semiconductor is a group V element including at least nitrogen (element symbol N), boron (element symbol B), aluminum (element symbol Al), gallium (element symbol Ga), It is a compound semiconductor with a group III element such as indium (element symbol In). Examples of nitride III-V compound semiconductors include binary compound semiconductors such as gallium nitride (GaN), and multi-element compound semiconductors such as aluminum nitride-gallium-indium (AlGaInN) and boron nitride-gallium-indium (BGaInN). Can be mentioned.

Note that when a multi-element compound semiconductor is represented by a chemical formula, constituent elements are shown side by side. For example, AlGaInN represents a quaternary compound semiconductor of aluminum (Al), gallium (Ga), indium (In), and nitrogen (N). In a multi-component compound semiconductor, when the composition ratio of each element is shown, it is described as a subscript beside each element in the chemical formula. For example, when A, B and C are group III elements and D is a group V element, the quaternary compound semiconductor of ABCD is A _x B _y C _1-xy D (0 <x <1, 0 <y <1, x + y <1).

The channel layer 13 and the barrier layer 14 that satisfy the relationship of the above formulas (1) and (2) can be realized by appropriately selecting the elements contained in the semiconductor material constituting each layer and the composition ratio of each element. . For example, the a-axis lattice constant of GaN is 0.3189 nm (3.189Å), the band gap at 300 K is 3.3 eV, and the a-axis lattice constant of Al _0.2 Ga _0.75 In _0.05 N is Since the band gap at 300 K is 3.5 eV, the channel layer 13 is formed of GaN, and the barrier layer 14 is formed of Al _0.2 Ga _0.75 In _0.05 N. By forming, the channel layer 13 and the barrier layer 14 that satisfy the relationship of the above formulas (1) and (2) can be realized.

  The buffer layer 12, the channel layer 13, and the barrier layer 14 are formed by, for example, a metal organic chemical vapor deposition (abbreviation: MOCVD) method, a molecular beam epitaxy (abbreviation: MBE) method, or the like. be able to. The temperature of the substrate 11 when the buffer layer 12 is formed using these methods is preferably 400 ° C. or higher and 800 ° C. or lower. By setting the temperature of the substrate 11 within the above range, it is possible to further suppress the occurrence of stacking faults at the interface between the substrate 11 and the buffer layer 12.

  The thickness of the buffer layer 12 is 20 nm, for example. The thickness d1 of the channel layer 13 is 3 μm, for example. The thickness d2 of the barrier layer 14 is 20 nm, for example. In the present embodiment, the thickness d1 of the channel layer 13 that is the first semiconductor layer is selected to be larger than the thickness d2 of the barrier layer 14 that is the second semiconductor layer (d1> d2). For example, when the thickness d1 of the channel layer 13 is about 1 to 3 μm, the thickness d2 of the barrier layer 14 is several tens of nm.

  The piezo effect material layer 15 is formed of a material having a piezo effect (piezo material). The piezo material for forming the piezo effect material layer 15 is not particularly limited as long as it has a piezo effect, and either an inorganic material or an organic material may be used. Hereinafter, an inorganic material used as a piezo material is also referred to as an inorganic piezo material. An organic material used as a piezo material is also referred to as an organic piezo material.

  As the inorganic piezo material, an oxide having a perovskite structure and a fluoride having a fluorite structure are preferably used. These compounds exhibit a remarkable piezo effect and can efficiently convert the applied voltage into crystal displacement. By using at least one of an oxide having a perovskite structure and a fluoride having a fluorite structure as a piezo material, an applied voltage can be efficiently converted into a stress applied to the barrier layer 14. A piezo effect material layer 15 can be realized. Therefore, the presence / absence of the formation of the two-dimensional electron gas layer at the heterointerface between the channel layer 13 and the barrier layer 14 can be efficiently controlled. Among these compounds, an oxide having a perovskite structure is particularly preferably used because it exhibits an excellent piezo effect.

The oxide having a perovskite structure is not particularly limited as long as it has a piezo effect, and known oxides can be used. Among them, barium titanate (chemical formula BaTiO ₃ ), lead lanthanum zirconate titanate (chemical formula (Pb, La) (Zr, Ti) O ₃ ), strontium bismuth tantalate (chemical formula SrBi ₂ Ta ₂ O ₉ ), titanic acid Bismuth (Chemical Formula Bi ₄ Ti ₃ O ₉ ), Lithium Niobate (Chemical Formula LiNbO ₃ ), and Strontium Niobate (Chemical Formula Sr ₂ Nb ₂ O ₇ ) are used in Ferro-electric Random Access Memory (abbreviated as FeRAM). It is preferably used because it exhibits a particularly remarkable piezo effect as it is used as a ferroelectric film material and can convert the applied voltage into crystal displacement more efficiently. By using these compounds, the state in which the two-dimensional electron gas layer is formed and the state in which the two-dimensional electron gas layer is not formed can be switched with a smaller voltage, so that the power consumption of the semiconductor device 1 can be reduced. .

Here, (Pb, La) (Zr, Ti) O ₃ represents a composite oxide of lead (Pb), lanthanum (La), zirconium (Zr), and titanium (Ti). Examples of (Pb, La) (Zr, Ti) O ₃ include Pb _0.8 La _0.2 Zr _0.2 Ti _0.8 O ₃ . (Pb, La) (Zr, Ti) O ₃ does not contain any one of Pb and La, for example, lead zirconate titanate Pb (Zr, Ti) O ₃ , and any one of Zr and Ti Including those that do not contain.

The fluoride having a fluorite structure is not particularly limited as long as it has a piezo effect, and known ones can be used. Among these, magnesium barium fluoride (chemical formula BaMgF ₄ ) and manganese barium fluoride (chemical formula BaMnF ₄ ) are preferably used because they exhibit an excellent piezo effect.

When the piezo effect material layer 15 is formed from these inorganic piezo materials, the piezo effect material layer 15 can be formed by a sputtering method such as a reactive sputtering method, a spin coating method, or the like. For example, when the reactive sputtering method is used, the piezo effect material layer 15 can be formed by using the piezo material described above as a target and depositing it on the surface of the barrier layer 14. The temperature of the board | substrate 11 at this time is about 600 degreeC, for example. Examples of the sputtering gas include plasma in which an active gas such as oxygen (molecular formula O ₂ ) is mixed with a rare gas such as argon (molecular formula Ar). In addition, when the spin coating method is used, it can be formed by applying a solution obtained by dissolving or dispersing the above-described piezo material in an appropriate solvent on the surface of the barrier layer 14 and then baking it. The firing temperature at this time is about 500-700 degreeC, for example.

  As the organic material used as the piezo material of the piezo effect material layer 15, polyvinylidene fluoride is preferably used since it exhibits an excellent piezo effect.

  When an organic piezo material is used, the piezo effect material layer 15 can be formed by a spin coating method or the like. Specifically, the piezo effect material layer 15 can be formed by applying a solution obtained by dissolving or dispersing the above-described organic piezo material in an appropriate solvent to the surface of the barrier layer 14 and then drying it. The drying temperature after application is, for example, 80 to 150 ° C., and the temperature of the substrate 11 when the piezoelectric effect material layer 15 is formed by sputtering using an inorganic piezo material and the piezo by spin coating using the inorganic piezo material. It is lower than the firing temperature when forming the effect material layer 15. In addition, when an organic piezo material is used, a firing step required when the piezo effect material layer 15 is formed by spin coating using an inorganic piezo material is not necessary.

  Thus, when an organic piezo material is used, the piezo effect material layer 15 can be formed at a lower temperature than when the above-described inorganic piezo material is used. This prevents changes in characteristics due to heating of the layers such as the buffer layer 12, the channel layer 13, and the barrier layer 14 formed on the one surface portion side of the substrate 11 before the formation of the substrate 11 and the piezoelectric effect material layer 15. Can do. For example, generation of lattice defects due to heating of the channel layer 13 and the barrier layer 14 can be prevented, and changes in the band gap and the like can be suppressed. Therefore, by using an organic piezo material such as polyvinylidene fluoride, malfunction of the semiconductor device 1 can be prevented and reliability can be improved.

  Whether an inorganic material or an organic material is used as the piezo material can be appropriately selected according to the type of material constituting each layer such as the channel layer 13 and the barrier layer 14.

  The thickness of the piezo effect material layer 15 is, for example, 100 to 1500 nm. The thickness of the piezo effect material layer 15 is not limited to this. Various thicknesses such as the thickness d2 of the barrier layer 14, the type of semiconductor material constituting the barrier layer 14, and the type of piezo material constituting the piezo effect material layer 15 are available. According to conditions, it can select suitably from a wide range.

  Although different from the present embodiment, the piezoelectric effect material layer 15 may be provided at a distance from the source electrode 16 and the drain electrode 17 so as not to contact the source electrode 16 and the drain electrode 17. However, in order to efficiently apply in-plane tensile stress to the barrier layer 14, the entire portion of the barrier layer 14 where the source electrode 16 and the drain electrode 17 are not formed is covered as in the present embodiment. Thus, it is preferable to form the piezoelectric effect material layer 15 in contact with the source electrode 16 and the drain electrode 17. In this way, by forming the piezo effect material layer 15 so as to cover the entire portion of the barrier layer 14 where the source electrode 16 and the drain electrode 17 are not formed, the piezo effect material layer 15 is formed in a larger portion of the barrier layer 14. Therefore, the barrier layer 14 can be efficiently distorted.

  The source electrode 16 and the drain electrode 17 are formed of a conductive material such as a metal material such as hafnium (chemical formula Hf), aluminum (chemical formula Al), or gold (chemical formula Au). The source electrode 16 and the drain electrode 17 may be formed of a multilayer conductive film formed by stacking films formed of the above-described conductive materials in the thickness direction. The source electrode 16 and the drain electrode 17 are formed by, for example, forming a resist mask having openings that are predetermined in order to form the source electrode 16 and the drain electrode 17 on the surface portion on one side in the thickness direction of the barrier layer 14. The conductive material is formed by depositing the above-described conductive material by a sputtering method or the like on a portion not covered with the film. The thickness of the source electrode 16 and the drain electrode 17, that is, the thickness of the conductive film that becomes the source electrode 16 and the drain electrode 17, is, for example, 300 nm.

  The gate electrode 18 is formed of a conductive material such as gold (Au). The gate electrode 18 can be formed, for example, by sputtering. The thickness of the gate electrode 18 is, for example, 200 nm.

  The thicknesses of the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14, the source electrode 16, the drain electrode 17, and the gate electrode 18 described above, and the temperature in the formation process of each layer are the values described above. However, it can be appropriately selected from a wide range according to the type of the material constituting the substrate 11 and each layer.

  As described above, the semiconductor device 1 of the present embodiment includes the piezo effect material layer 15 as a stress applying unit that applies stress to the barrier layer 14 that is the second semiconductor layer. The stress applying means is not limited to the piezo effect material layer 15, and at least in-plane tensile stress can be applied to the barrier layer 14 as in the piezo effect material layer 15, and the stress application state is controlled. Can be used as stress applying means. However, it is preferable to use the piezo effect material layer 15 as in the present embodiment because it is easy to control the state of stress applied to the barrier layer 14 and the apparatus configuration can be simplified.

  FIG. 2 is a cross-sectional view showing a simplified configuration of a semiconductor device 2 according to another embodiment of the present invention. The semiconductor device 2 of the present embodiment is similar to the semiconductor device 1 of the above-described embodiment, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted in the semiconductor device 2 of the present embodiment that the buffer layer 22 includes two types of layers formed of different semiconductor materials. Specifically, the buffer layer 22 has a stacked structure in which first buffer layers 20 and second buffer layers 21 formed of a semiconductor material different from the semiconductor material constituting the first buffer layer 20 are alternately stacked. Have.

  Thus, when the buffer layer 22 is formed of a plurality of layers, a buffer layer having excellent lattice matching with the substrate 11 is provided on the side in contact with the substrate 11, and lattice matching with the channel layer 13 is provided on the side in contact with the channel layer 13. Can be provided. Therefore, the occurrence of stacking faults in the vicinity of the interface between the buffer layer 22 and the substrate 11 and in the vicinity of the interface between the buffer layer 22 and the channel layer 13 can be further suppressed, so that the carrier transport performance can be improved.

  The buffer layer 22 can be formed using the same material as the buffer layer 12 of the above-described embodiment. The buffer layer 22 can be formed by alternately laminating the first buffer layer 20 and the second buffer layer 21 on the surface portion of the substrate 11 by using, for example, the MOCVD method, the MBE method, or the like. The total thickness of the buffer layer 22 is, for example, 20 nm.

  In the present embodiment, the buffer layer 22 includes three first buffer layers 20 and three second buffer layers 21. The number of layers constituting the buffer layer 22 is not limited to this, and can be appropriately selected from a wide range. For example, the buffer layer 22 may be formed of one first buffer layer 20 and one second buffer layer 21. Moreover, although there are two types of layers constituting the buffer layer 22 in the present embodiment, the type is not limited to this and may be three or more types.

  Although the semiconductor devices 1 and 2 of the first embodiment and the other embodiments described above are field effect transistors, the semiconductor device of the present invention is not limited to this, and at least the above formula (1) and What is the configuration as long as it includes two types of semiconductor layers, the first semiconductor layer and the second semiconductor layer satisfying (2), and stress applying means for applying stress to the second semiconductor layer? Also good.

Example 1
In this example, a field effect transistor (abbreviated as FET) having the same configuration as that of the semiconductor device 1 shown in FIG. 1 was manufactured as follows.

Using a MOCVD method, a 20 nm thick buffer layer made of gallium nitride (GaN) is grown at a substrate temperature of 500 ° C. on a 350 μm thick sapphire substrate (hereinafter also referred to simply as a substrate). A channel layer made of gallium nitride (GaN) was grown at 1100 ° C. by 3 μm. Further, a barrier layer made of Al _0.2 Ga _0.75 In _0.05 N was grown to 20 nm on the channel layer at a substrate temperature of 1100 ° C.

The a-axis lattice constant a ₁ of GaN constituting the channel layer is 0.3189 nm (3.189３), and the band gap Eg _{1 at} 300 K is 3.3 eV. The a-axis lattice constant a ₂ of Al _0.2 Ga _0.75 In _0.05 N constituting the barrier layer is 0.3191 nm (3.191 １９), and the band gap Eg _{2 at} 300 K is 3.5 eV.

  Next, a resist layer was formed on the barrier layer, and was patterned using a photolithography technique to form a resist mask in which predetermined portions were opened to form a source electrode and a drain electrode. Hafnium (Hf) is deposited to 10 nm, aluminum (Al) is deposited to 100 nm, hafnium (Hf) is deposited to 40 nm, and gold (Au) is deposited to 240 nm sequentially on the portion of the barrier layer that is not covered with the resist mask, and Hf (10 nm) / A multilayer film of Al (100 nm) / Hf (40 nm) / Au (240 nm) was formed, and heat treatment was performed at a temperature of 825 ° C. for 30 seconds to form a source electrode and a drain electrode.

Next, the resist mask is removed, and 1 μm of barium titanate (BaTiO ₃ ) is deposited by sputtering at a substrate temperature of 600 ° C. on the portion of the barrier layer where the source electrode and drain electrode are not formed to form a piezo-effect material layer did. In this example, a piezoelectric effect material layer was formed by reactive sputtering using plasma in which argon (Ar) and oxygen (O ₂ ) were mixed using barium titanate (BaTiO ₃ ) as a target.

  On the formed piezo effect material layer, the source electrode and the drain electrode, a resist mask having a predetermined portion opened to form a gate electrode is formed, and the piezo effect material layer is not covered with the resist mask. Gold (Au) was deposited to a thickness of 0.5 μm to form a gate electrode.

As described above, the field effect transistor of Example 1 was fabricated. With respect to the manufactured transistor, the relationship between the source-drain voltage V _DS and the drain current _ID (hereinafter referred to as current-voltage characteristics) was examined by changing the gate voltage Vg. The result is shown in FIG.

FIG. 3 is a graph showing current-voltage characteristics of the transistor manufactured in Example 1. In FIG. 3, the horizontal axis represents the source-drain voltage V _DS (V), and the vertical axis represents the drain current I _D (mA). In FIG. 3, a curve indicated by reference numeral 31 indicates a case where the gate voltage Vg is 0V, a curve indicated by reference numeral 32 indicates a case where the gate voltage Vg is 3V, and a curve indicated by the reference numeral 33 is The case where the gate voltage Vg is 6V is shown, the curve indicated by reference numeral 34 indicates the case where the gate voltage Vg is 9V, and the curve indicated by reference numeral 35 indicates the case where the gate voltage Vg is 12V.

As shown in FIG. 3, in the transistor manufactured in Example 1, when the gate voltage Vg indicated by reference numeral 31 is zero (0), the drain current I is increased even if the source-drain voltage V _DS is increased. _D did not flow and was found to be a normally-off type transistor.

(Example 2)
In this example, in the transistor having the same structure as that of Example 1, the current-voltage characteristics when the type of the piezo material forming the piezo effect material layer was changed were examined.

Specifically, a piezo effect material layer having the thickness shown in Table 1 is formed using each piezo material shown in Table 1, and a silicon carbide (SiC) substrate is used as the substrate, and the buffer layer is made of aluminum nitride (AlN). The channel layer is formed by growing In _0.05 Ga _0.95 N at a substrate temperature of 800 ° C., and the barrier layer is formed by using Al _0.1 Ga _0.83 In _0.07 N at a substrate temperature of 800 ° C. The transistors of Samples 1 to 8 shown in Table 1 were fabricated in the same manner as in Example 1 except that the transistors were grown at 0 ° C. Layers other than the piezoelectric effect material layer and the thickness of the substrate were the same as those of the transistor of Example 1.

The a-axis lattice constant a ₁ of In _0.05 Ga _0.95 N constituting the channel layer is 0.3207 nm (3.207３), and the band gap Eg _{1 at} 300 K is 3.25 eV. The a-axis lattice constant a ₂ of Al _0.1 Ga _0.83 In _0.07 N constituting the barrier layer is 0.3207 nm (3.207 Å), and the band gap Eg _{2 at} 300 K is 3.4 eV.

The current-voltage characteristics of each of the transistors 1 to 8 shown in Table 1 were examined in the same manner as in Example 1. When the gate voltage was zero, the source-drain voltage _VDS was increased. However, the drain current _ID did not flow, and it was found that the transistor was a normally-off type transistor.

For each of the transistors in Samples 1 to 8, the gate voltage Vg (V) at which the drain current _ID was 200 mA when the source-drain voltage V _DS was 20 V was obtained. The results are shown in Table 1.

From the comparison between sample 1 and sample 7, and the comparison between sample 2 and sample 8, the transistors of samples 1 and 2 using oxides having a perovskite structure as piezo materials use fluorides having a fluorite structure. It was found that the same amount of drain current _ID can be flowed with a smaller gate voltage Vg than the transistors of Samples 7 and 8.

(Example 3)
In this example, the field effect transistor of Example 3 was fabricated in the same manner as in Example 1 except that the thickness of the barium titanate (BaTiO ₃ ) layer, which is a piezoelectric effect material layer, was 200 nm.

When the current-voltage characteristics of the manufactured transistor were examined in the same manner as in Example 1, when the gate voltage was zero, the drain current _ID did not flow even when the source-drain voltage V _DS was increased. It was found to be a normally-off type transistor.

Further, when the gate voltage Vg (V) at which the drain current _ID is 200 mA when the source-drain voltage V _DS is 20 V is obtained for the manufactured transistor, it is 20 V.

Comparing the results of this result and sample 1 of Example 2 shown in Table 1, towards the a-axis lattice constant a ₁ and a barrier layer a-axis lattice constant a ₂ are equal sample 1 of the transistor channel layer, the difference between the a-axis lattice constant _{a 2} of the a-axis lattice constant _{a 1} and a barrier layer of the channel layer than in the transistor of example 3 is 0.0002Nm, the drain current _{I D} of the same amount in a smaller gate voltage Vg It turned out that it can flow. Therefore, as the difference between the a-axis lattice constant a ₂ of the a-axis lattice constant a ₁ and a barrier layer of the channel layer is small, it can be seen that it is possible to turn on the transistor with a smaller gate voltage.

Example 4
In this example, a transistor having the same configuration as that of the semiconductor device 2 shown in FIG. 2 was manufactured as follows.

Using MOCVD, a gallium nitride (GaN) film and an aluminum nitride (AlN) film are alternately grown on a 350 μm thick silicon (Si) substrate in this order from the GaN film at a substrate temperature of 500 ° C. A buffer layer having a thickness of 200 nm made of a GaN / AlN multilayer film of 10 layers of AlN was formed. The thickness of the GaN film and AlN film of each layer constituting the GaN / AlN multilayer film was 10 nm. Subsequently, a channel layer having a thickness of 1.5 μm made of gallium nitride (GaN) was formed at a substrate temperature of 1100 ° C. Further, a 10 nm thick barrier layer made of B _0.02 Ga _0.9 In _0.08 N was formed on the channel layer at a substrate temperature of 1100 ° C.

The a-axis lattice constant a ₁ of GaN constituting the channel layer is 0.3189 nm (3.189３), and the band gap Eg _{1 at} 300 K is 3.3 eV. The a-axis lattice constant a ₂ of B _0.02 Ga _0.9 In _0.08 N constituting the barrier layer is 0.3205 nm (3.205 Å), and the band gap Eg _{2 at} 300 K is 3.5 eV.

  Next, in the same manner as in Example 1, a source electrode and a drain electrode composed of a multilayer film of Hf (10 nm) / Al (100 nm) / Hf (40 nm) / Au (240 nm) were formed. Thereafter, polyvinylidene fluoride (specific gravity: 1.79, melting point: 175 ° C.) is applied to the portion of the barrier layer excluding the portion where the source electrode and the drain electrode are formed, using a spin coating method, and the thickness is obtained as a piezoelectric effect material layer. A 500 nm polyvinylidene fluoride film was formed. Next, a gate electrode was formed in the same manner as in Example 1.

  As described above, the field-effect transistor of Example 4 was produced. About the produced transistor, it carried out similarly to Example 1, and investigated the current-voltage characteristic. The result is shown in FIG.

FIG. 4 is a graph showing current-voltage characteristics of the transistor manufactured in Example 4. In FIG. 4, the horizontal axis represents the source-drain voltage V _DS (V), and the vertical axis represents the drain current I _D (mA). In FIG. 4, the curve indicated by reference numeral 41 indicates the case where the gate voltage Vg is 0 V, the curve indicated by reference numeral 42 indicates the case where the gate voltage Vg is 3 V, and the curve indicated by the reference numeral 43 is The case where the gate voltage Vg is 6V, the curve indicated by reference numeral 44 indicates the case where the gate voltage Vg is 9V, and the curve indicated by reference numeral 45 indicates the case where the gate voltage Vg is 12V.

As shown in FIG. 4, in the transistor of the fourth embodiment, the drain current _ID does not flow when the gate voltage Vg indicated by reference numeral 41 is zero, as in the transistor of the first embodiment. It turned out that.

Further, comparing the transistor of Example 1 with the transistor of Example 4, in the transistor of Example 4, the magnitude of the drain current _ID obtained when the same gate voltage Vg was applied was The size is smaller than that of the first transistor. For example, in the transistor of Example 4, when the gate voltage Vg indicated by reference numeral 45 is 12 V, the drain current _ID is 150 mA. However, in the transistor of Example 1, it is indicated by reference numeral 35 in FIG. When the gate voltage Vg applied is 12V, the drain current _ID is 200 mA.

  This is because the transistor of Example 1 uses an oxide having a perovskite structure as the piezo material, so that the piezoelectric effect material layer is deformed at a smaller voltage than the transistor of Example 4 using polyvinylidene fluoride. This is presumed to be because stress could be applied to the barrier layer.

  As described above, the channel layer, which is the first semiconductor layer, and the barrier layer, which is the second semiconductor layer, are formed so as to satisfy the relationship of the above formulas (1) and (2), and the piezo-effect material is used as the stress applying means. By providing the layer, a normally-off type field effect transistor could be realized.

It is sectional drawing which simplifies and shows the structure of the semiconductor device 1 which is one Embodiment of this invention. It is sectional drawing which simplifies and shows the structure of the semiconductor device 2 which is the other embodiment of this invention. 6 is a graph showing current-voltage characteristics of a transistor manufactured in Example 1. FIG. 6 is a graph showing current-voltage characteristics of a transistor manufactured in Example 4. FIG. It is a figure which shows typically an example of the current-voltage characteristic of the field effect transistor using the conventional hetero structure. It is a figure which shows typically an example of the current-voltage characteristic of the normally-off type transistor using silicon.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 11 Substrate 12, 22 Buffer layer 13 Channel layer 14 Barrier layer 15 Piezoelectric effect material layer 16 Source electrode 17 Drain electrode 18 Gate electrode

Claims (6)

A first semiconductor layer composed of a nitride III-V compound semiconductor;
A second semiconductor layer provided in contact with the first semiconductor layer and made of a nitride III-V compound semiconductor;
A source electrode, a gate electrode, and a drain electrode provided on a side opposite to the side in contact with the first semiconductor layer of the second semiconductor layer,
Stress applying means capable of applying stress to the second semiconductor layer, the stress applying means including a piezoelectric effect material layer formed of a material having a piezoelectric effect and provided between the second semiconductor layer and the gate electrode. Prepared,
The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer satisfy a relationship of the following formulas (1) and (2) .
a ₁ ≦ a ₂ (1)
Eg ₁ <Eg ₂ (2)
(Where a ₁ represents the a-axis lattice constant of the semiconductor material constituting the first semiconductor layer, a ₂ represents the a-axis lattice constant of the semiconductor material constituting the second semiconductor layer. Eg ₁ represents the first semiconductor. shows the bandgap of the semiconductor material constituting the layers, Eg ₂ shows the band gap of the semiconductor material of the second semiconductor layer.) 2. The semiconductor device according to claim 1, wherein the material having a piezo effect is an oxide having a perovskite structure. The oxide having a perovskite structure is composed of BaTiO ₃ , (Pb, La) (Zr, Ti) O ₃ , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₉ , LiNbO ₃ and Sr ₂ Nb ₂ O _7. The semiconductor device according to claim 2, wherein the semiconductor device is one or more selected from the group consisting of: 2. The semiconductor device according to claim 1, wherein the material having a piezo effect is a fluoride having a fluorite structure. Fluoride having a fluorite structure, the semiconductor device according to claim 4, characterized in that at least either of the BaMgF ₄ and BaMnF _4. 2. The semiconductor device according to claim 1, wherein the material having a piezo effect is polyvinylidene fluoride.

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