JP2003243424A - Heterojunction field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction field effect transistor that flattens a surface, and prevents deterioration in characteristics caused by the grain state of the surface. <P>SOLUTION: The heterojunction field effect transistor is a semiconductor device where at least a low-temperature buffer layer, a channel layer, a spacer layer, and an electron supply layer are successively formed. In this case, a cap layer is further formed on the electron supply layer, and the lattice constant of the cap layer is nearly the same as that of the channel layer and is different from those of the spacer and electron supply layers. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a heterojunction field effect transistor.

[0002]

2. Description of the Related Art Various types of transistors, which are one of semiconductor elements, are known.
Heterojunction field effect transistors have been attracting attention because they can operate at high speed and can obtain low noise performance. The heterojunction field effect transistor has a non-doped III-V compound semiconductor layer and an n-type III-V compound semiconductor layer formed on a III-V compound semiconductor substrate.
The gate electrode controls the high-mobility two-dimensional electron gas concentration generated at the heterojunction surface.

As the heterojunction field effect transistor, a III-nitride type (in particular, AlGaN /
(GaN-based) semiconductor element, Staci Kel
ler et al. : IEFE Trans. El
electron Devices, 48, 552 (200
1), '' Gallium nitride Base
d High Power Heterojuncti
on Field effect Transisto
rs: Process Development an
d Present Status at UCS
Examples thereof include those described in B ″.

In the AlGaN / GaN heterojunction field effect transistor described in the above document, AlGaN / G grown by metal organic chemical vapor deposition (MOCVD method).
The AlGaN film on the surface of the aN laminated film has an Al composition ratio of 0.25.
It is described that if it is larger than that, it becomes grainy and can be improved from grainy to flat by reducing the ammonia flow rate of the laminated film growth parameter. However, even in this method, the grain state still remains, and a good flat film is not obtained.

When the AlGaN surface layer becomes grainy,
It becomes impossible to increase the two-dimensional electron concentration, and it becomes impossible to increase the current value of the heterojunction field effect transistor. Further, the grainy shape increases the number of surface defects and deteriorates the high frequency characteristics. That is, the characteristics of the heterojunction field effect transistor are deteriorated.

FIG. 5 shows an Al _0.26 Ga _0.74 N / GaN laminated structure of a heterojunction field effect transistor with reference to the above-mentioned document. As its structure, sapphire (Al ₂
A GaN layer (low temperature buffer layer) 102 and a non-doped GaN layer (channel layer) 10 are formed on a substrate 101 made of O ₃ ).
3, non-doped Al _0.26 Ga _0.74 N layer (spacer layer) 1
04, n-type Al _0.26 Ga _0.74 N layer (electron supply layer) 10
5 and a non-doped Al _0.26 Ga _0.74 N layer (cap layer) 106 are sequentially formed.

[0007] Similar to the above document, in our experiments, a non-doped Al _{0. 26} Ga _0.74 N layer 1 which is the uppermost surface layer
It was impossible to form 06 as a completely flat film on the surface, and cracks were observed on the surface, and it was still grainy.

One of the causes of the grain shape is that the lattice constant (equivalent to the interatomic distance) of Al _0.26 Ga _0.74 N in the electron supply layer and the spacer layer is smaller than that of GaN which is the channel layer. It is considered that the lattice mismatch causes cracks to form from the surface to the inside.

[0009]

From the above, the present invention is
An object of the present invention is to provide a heterojunction field effect transistor in which the surface is made flat and the characteristic deterioration due to the above-mentioned surface becoming grainy is not caused.

[0010]

As a result of intensive studies to solve the above problems, the present inventors have found that the problems can be solved by the present invention described below. That is, the present invention is a semiconductor element in which at least a low temperature buffer layer, a channel layer, a spacer layer, and an electron supply layer are sequentially formed on a substrate, and the cap layer is further formed on the electron supply layer. Are formed, and the lattice constant of the cap layer is
A heterojunction field effect transistor, which has substantially the same lattice constant as that of the channel layer and is different from the lattice constants of the spacer layer and the electron supply layer.

<2> The channel layer is made of GaN, and the spacer layer and the electron supply layer are made of Al _i G.
a _1-i N (0 <i <1), and the cap layer is A
The heterojunction field effect transistor according to <1>, which is made of l _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1).

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION <Heterojunction Field Effect Transistor> The heterojunction field effect transistor of the present invention has at least non-doped GaN or AlGa on a substrate.
A low temperature buffer layer made of N or the like, a channel layer made of non-doped GaN or the like, a spacer layer made of non-doped AlGaN or the like, and an electron supply layer made of n-type AlGaN or the like are sequentially formed, and n is further formed on the electron supply layer. A cap layer made of Al _x In _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1) or the like is formed. Since the cap layer is formed in a flat state, it is possible to prevent the two-dimensional electron concentration from decreasing due to surface defects and prevent the deterioration of the heterojunction field effect transistor characteristics such as the deterioration of high frequency characteristics. The term "flat" means that the surface of the cap layer has almost no cracks or no cracks. More specifically, the surface roughness is measured by an atomic force microscope (AFM). RMS represented)
Is 0.4 nm or less, preferably 0.3 nm or less. When RMS exceeds 0.4 nm,
The number of surface cracks increases, and as a result, the number of defects increases, the surface layer (cap layer) becomes uneven, and the characteristics of the heterojunction field effect transistor are likely to deteriorate.

[0013]

[Equation 1]

In the above formula (1), Z _i represents the height of the surface at the measurement point i, Z _ave represents the average height for all the measurement points, and n represents the number of measurement points. .

The “flat” cap layer has a lattice constant of n-type Al _x In _y Ga _1-xy N of GaN.
It is obtained by performing lattice matching so that the lattice constant is substantially the same as the lattice constant of. Here, the term “substantially the same” means that when the lattice constant of GaN is C, the lattice constant of Al _x In _y Ga _1-xy N is in the range of 0.997C to 1.01C. Within such a range, cracks (surface defects) are eliminated and a flat surface can be obtained.

As described above, cracks are generated on the surface of the conventional heterojunction field effect transistor because the lattice constants of the channel layer and the spacer layer and the electron supply layer in contact with the channel layer are different. It is considered that the lattice mismatch occurs and the lattice becomes free as it goes away from the channel layer in the thickness direction. Therefore, if the cap layer can be lattice-matched with the material forming the channel layer (for example, GaN), the lattice of the electron supply layer is also subjected to stress from the lattice of the cap layer on the electron supply layer, and cracks do not occur. Conceivable. As a result, the surface of the cap layer is in a flat state with little or no defects, and deterioration of the characteristics of the heterojunction field effect transistor can be prevented.

In the heterojunction field effect transistor of the present invention, the cap layer is preferably n-type Al _x I.
A layer made of n _y Ga _1-xy N is formed on the electron supply layer.
The above Al _x In _y Ga _1-xy N is obtained by _replacing x and y in the formula with
By setting appropriately in the range of 0 ≦ x <1, 0 ≦ y <1,
It comes to be lattice-matched with the channel layer made of GaN.

Al lattice-matched with GaN (channel layer)
_{By using x} In _y Ga _1-xy N as the cap layer, the upper part of the electron supply layer (interface between the cap layer and the electron supply layer) receives stress from the cap layer, and the interaction with the lower channel layer causes By suppressing the generation of such cracks, which are considered to suppress the generation of cracks, it is considered that the surface becomes flat and the above-described effect is achieved.

_{X in the} formula of Al _x In _y Ga _1-xy N,
y can be set from the relationship between the lattice constant and the band gap of the material having the GaN-based laminated structure shown in FIG.

That is, Al _x I lattice-matched with GaN
n _y Ga _1-xy N is the same as the above “substantially the same”.
As shown in FIG. 1, the lattice constants of 3.179 to 3.221Å (C
Is 0.997C as the lattice constant of GaN is 3.189Å.
(Corresponding to 1.01C) (hatched portion in FIG. 1). Therefore, by defining the values of x and y in the above region, Al _x In _y Ga lattice-matched with GaN can be obtained.
_A flat cap layer of _1-xy N is formed. The lattice constants (Å) of AlN, GaN, and InN in FIG.
Are 3.112, 3.189, and 3.548, respectively, and the band gap (eV) is 3.3, respectively.
They are 9.6.20 and 1.89.

Here, in the n-type Al _x In _y Ga _1-xy N, an atomic force microscope (AFM) of the surface of the n-type Al _x In _y Ga _1-xy N when the electron supply layer is covered with GaN when x = y = 0 is used as the cap layer. The image is shown in FIG. As is clear from FIG.
No cracks are visible on its surface. Also, the surface roughness (RM
S) is 0.31 nm, and it can be confirmed that the surface is flat. That is, it can be confirmed from the results of the AFM that a flat cap layer having no defects on the surface is formed by lattice matching.

Further, the cap layer made of n-type Al _x In _y Ga _1-xy N has a band gap within the range shown by the diagonal lines in FIG. 1, for example, Al _0.26 Ga.
If the composition is made to match the band gap of _0.74 N, the band gaps of Al _x In _y Ga _1-xy N and Al _0.26 Ga _0.74 N become equal and the band discontinuity becomes small, so that the heterojunction electric field is reduced. The series resistance component of the effect transistor can be reduced, and the characteristics of the heterojunction field effect transistor can be improved. Other means for reducing the series resistance component include means for increasing the carrier concentration between the cap layer and the electron supply layer.

From the above, the cap layer made of n-Al _x In _y Ga _1-xy N is lattice-matched with GaN, and its band gap is made of a material (for example, Al).
_0.26 Ga _0.74 N)
It can be said that it is preferable to make the composition so as to fall within the shaded area in the triangle shown in FIG.

<Manufacturing Method of Heterojunction Field Effect Transistor> In the manufacturing method of the heterojunction field effect transistor of the present invention, at least n-type Al having substantially the same lattice constant as GaN (channel layer) on the electron supply layer is formed. _x In _y Ga
It is preferable to have a cap layer forming step of forming a cap layer made of _1-xy N. Hereinafter, a method for manufacturing the heterojunction field effect transistor of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram showing a manufacturing process of the heterojunction field effect transistor of the present invention. FIG. 3A shows the laminated structure of the semiconductor element. Such a laminated structure can be produced by, for example, a metal organic chemical vapor deposition method (MOCVD method). Here, the source gas of nitrogen (N) is, for example, ammonia (NH ₃ ), the source gas of gallium is, for example, trimethylgallium (TMG), and the source gas of aluminum is, for example, trimethylaluminum, indium. As the source gas, for example, trimethylindium (TMI); n
Silane (SiH ₄ ); is preferably applied as the type dopant.

Specifically, first, 5 installed in the growth apparatus
A low temperature buffer layer 2 having a thickness of 20 to 60 nm is formed on the substrate 1 at a temperature of 00 to 700 ° C., and then the temperature of the substrate 1 is set to 10
The channel layer 3 has a thickness of 2-3 μm.
It is formed by m. Here, the flow rate of the source gas at the time of forming the channel layer is NH ₃ : 5 liter / min, TMG: 69
It is preferable to carry out at μmol / min.

The substrate 1 is sapphire (Al ₂ O ₃ )
In addition to SiC and SiC, it is preferable to use a GaN single crystal substrate which has recently been used at the research level. Further, as a material forming the low temperature buffer layer 2, GaN or AlGaN is used.
Etc. can be mentioned. Furthermore, examples of the material forming the channel layer 3 include non-dove GaN.

A spacer layer 4 having a thickness of 5 to 15 nm is formed on the formed channel layer 3. On the formed spacer layer 4, the carrier concentration is (1 to 10) × 10 ¹⁸ cm ⁻³
The electron supply layer 5 is formed to have a thickness of 10 to 40 nm.

As a material for forming the spacer layer 4,
A semiconductor material composed of Al, Ga and N, particularly non-doped Al _0.26 Ga _0.74 N. In addition, as a material forming the electron supply layer 5, Al or Ga is used.
And N are semiconductor materials, especially n-Al _0.26 G
a _0.74 N and the like can be mentioned. Here, the temperature for forming the spacer layer 4 and the electron supply layer 5 is 100
The temperature is preferably 0 to 1100 ° C. Also, NH ₃ ,
The flow rates of TMG and TMA are 5 liter / min and 29.5 μmol / min for the Al _0.26 Ga _0.74 N layer, respectively.
Min, 5.2 μmol / min.

Next, n-type Al _x I having a carrier concentration of (1-5) × 10 ¹⁸ cm ^-3 was formed on the formed electron supply layer.
A cap layer made of n _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1,) is formed with a thickness of 10 to 20 nm (cap layer forming step). Although _{x and y of} Al _x In _y Ga _1-xy N are set so as to be lattice-matched with GaN as described above,
Considering the band gap and the like, x and y are respectively set to 0.
It is preferably about 29, 0.07. The cap layer can also be formed by a general MOCVD method.

Next, the laminated body (wafer) on which the cap layer 6 is formed is taken out from the growth apparatus, and the resist pattern 1 as shown in FIG.
1 is formed.

After that, a metal laminated thin film 21 having a thickness of 3 is formed for forming ohmic electrodes (source electrode, drain electrode).
It is formed by vacuum evaporation at a thickness of 00 to 400 nm, the metal laminated thin film 21 on the resist pattern 11 is removed by a lift-off method, and an electrode structure as shown in FIG. 3C is formed.
The wafer on which the electrode structure is formed is heated in a nitrogen atmosphere at 450
Ohmic electrode (source electrode, drain electrode) having ohmic contact by annealing for several minutes at ℃ or more
21 'is obtained.

As the ohmic electrode 21 'laminated structure,
For example, a Ti thin film, an Al thin film, a Ni thin film, and an Au thin film may be laminated in this order. The metal of the first layer (metal forming the metal thin film 21) in contact with the cap layer 5 in the ohmic electrode 21 ′ is Ti.
Besides, one kind may be selected and used from Al, Pd, Nd and the like. It should be noted that the annealing condition is an example and is not limited to this.

Next, the resist pattern 31 of FIG. 3D is formed again by photolithography, a Schottky metal is vapor-deposited, and a gate electrode 41 as shown in FIG. 3E is formed by lift-off method. A junction field effect transistor is produced. The Schottky metal may be appropriately selected from Re, W, Pt, Ni, Pd, Au and the like.

The heterojunction field effect transistor of the present invention is manufactured as described above. Note that the above manufacturing method is an example, and various modifications can be made such that various known layers are appropriately provided within a range that does not impair the effects of the present invention.

[0036]

EXAMPLES The present invention will now be described in detail with reference to examples, but the present invention is not limited thereto.

Example 1 In this example, a metal organic chemical vapor deposition method (MOCVD method) was used to form a layer.
As a source gas of nitrogen (N), ammonia (N
H ₃ ), gallium source gas is trimethyl gallium (TMG); aluminum source gas is trimethyl aluminum; indium source gas is trimethyl indium (TMI); n-type dopant is silane (SiH _4). ); Is used. First, a 600 ° C. sapphire substrate (thickness 0.3
mm), a GaN low-temperature buffer layer having a thickness of 30 nm was formed, and then the channel temperature of the substrate was set to 1050 ° C. to form a channel layer made of non-doped GaN having a thickness of 2.5 μm. The flow rate of the source gas at the time of forming the channel layer is NH ₃ : 5 liter / min, TMG: 69 μmol /
Minutes (hereinafter the same).

Non-doped Al is formed on the formed channel layer.
_A spacer layer made of _0.26 Ga _0.74 N was formed to a thickness of 10 nm. Then, n-type Al is formed on the spacer layer.
Electron supply layer consisting of _0.26 Ga _0.74 N (carrier concentration 5 ×
10 ¹⁸ cm ⁻³ ) was formed with a thickness of 20 nm. Here, the temperature when forming the spacer layer 4 and the electron supply layer 5 was 1050 ° C.

A carrier concentration is formed on the formed electron supply layer.
1 x 10¹⁸cm^-3N-type Al _0.29In_0.07Ga
_0.64N (lattice constant: 3.189Å, band gap:
4.12 eV) cap layer with a thickness of 10 nm
(Cap layer forming step).

The surface of the formed cap layer was measured by an atomic force microscope (AFM). The measured AFM image was almost the same as that in FIG. 2, and it could be confirmed that there were no defects on the surface. The surface roughness (RMS) was measured and found to be 0.2 nm. That is, it was confirmed that the surface of the manufactured laminate (the surface of the cap layer) was flat and had a surface defect-free state.

Next, the laminated body (wafer) on which the cap layer is formed is taken out from the growth apparatus, a resist pattern is formed by known photolithography, and a Ti thin film is formed for forming an ohmic electrode (source electrode, drain electrode). 15 nm thick, Al thin film 220 nm thick, Ni thin film 40 nm thick, Au thin film 50 nm thick vacuum-deposited in this order to form a metal laminated thin film, and the metal laminated thin film on the resist pattern is removed by lift-off method. did.

An ohmic electrode (source electrode, drain electrode) having ohmic contact was obtained by annealing the wafer on which this metal laminated thin film was formed at 450 ° C. or higher for several minutes in a nitrogen atmosphere. Next, a resist pattern was formed again by photolithography, Re was deposited as a Schottky metal, and a gate electrode was formed by a lift-off method to manufacture a heterojunction field effect transistor.

Comparative Example 1 n-type Al was used for the cap layer.
_0.29 In _0.07 Ga _0.64 N instead of N undoped Al
_A heterojunction field effect transistor was produced in the same manner as in Example 1 except that a layer (thickness 5 nm) made of _0.26 Ga _0.74 N was formed. FIG. 4 shows the AFM measurement results for the surface state of the cap layer made of non-doped Al _0.26 Ga _0.74 N before ohmic contact. From Figure 4,
It was confirmed that the surface was grainy. Furthermore, A
Surface roughness (RMS) calculated from FM is 0.94 nm
Then, the existence of surface defects was confirmed. It is considered that this is because the surface was cracked due to the lattice mismatch.

The characteristics of the heterojunction field effect transistors manufactured in Example 1 and Comparative Example 1 were evaluated by Hall effect measurement and current-voltage characteristic measurement. In Comparative Example 1, deterioration of characteristics due to surface defects was observed. However, in Example 1, good characteristics were always obtained.

[0045]

According to the present invention, it is possible to provide a heterojunction field effect transistor in which the surface is made flat and the characteristics are not deteriorated due to the grainy surface.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a band gap of a semiconductor and a lattice constant.

FIG. 2 is a photograph showing an atomic force microscope image of the cap layer surface.

FIG. 3 is a diagram showing an example of a manufacturing process of a heterojunction field effect transistor.

FIG. 4 is a photograph showing an atomic force microscope image of a cap layer made of non-doped Al _0.26 Ga _0.74 N in Comparative Example 1.

FIG. 5: Al _{0.26 of a} heterojunction field effect transistor
It is a sectional view showing a Ga _0.74 N / GaN laminated structure.

[Explanation of symbols]

1 ... Substrate 2 ... Low temperature buffer layer 3 ... Channel layer 4 ... Spacer layer 5 ... Electron supply layer 6 ... Cap layer 11, 31 ... Resist pattern 21 ... Metal thin film 21 '... Ohmic electrode 41 ... Gate electrode

Continued front page    F-term (reference) 5F102 GB01 GC01 GD01 GJ02 GJ04                       GJ10 GK04 GL04 GM04 GM08                       GQ01 GT01 GT03 HC01 HC11                       HC19 HC21

Claims (2)

[Claims] 1. A semiconductor device in which at least a low-temperature buffer layer, a channel layer, a spacer layer, and an electron supply layer are sequentially formed on a substrate, and a cap layer is further formed on the electron supply layer. A heterojunction field effect transistor, wherein a lattice constant of the cap layer is substantially the same as a lattice constant of the channel layer and different from lattice constants of the spacer layer and the electron supply layer. 2. The channel layer is made of GaN, and the spacer layer and the electron supply layer are Al _i Ga _{1 -i} N.
(0 <i <1), and the cap layer is Al _x In _y
The heterojunction field effect transistor according to claim 1, wherein the heterojunction field effect transistor is made of Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1).