JPH03187269A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable high-speed actions of transistors in heterostructures free of alloy scattering by using a simple substance of Ge undergoing compression strain as the channel of a field effect transistor and the base of a bipolar transistor. CONSTITUTION:A layer through which carriers run consists of a germanium layer 3 that overlies a strain control layer 2 and shows compression strain. That is, compression strain is given to the germanium layer 3 under control by the strain control layer 2 located below, or above and below, the germanium layer 3. The strain control layer 2 employs an Si1-XSGeXS mixed crystal layer and varies this mixed crystal ratio Xs to control strain given to the germanium layer 3. As a result, two-dimensional hole gas of high mobility, high saturation speed, and high concentration thus formed by a simple substance layer of Ge showing compression strain can realize the speedup of a field effect transistor and a bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an electric field seedling transistor and a bipolar transistor.

[Conventional technology]

In recent years, research has been active on betaro structures in which different types of semiconductors with different band gaps are stacked for application to ultrahigh-speed devices. In particular, GaAs.

Research has begun not only on compound semiconductors such as AQGaAs, but also on Si-based semiconductors that are suitable for integration.

Figure 2 shows a typical example of this.
< 1) The mixed crystal is used as the channel of the field effect transistor (
It is used as the base of a bipolar transistor (FIG. 2(b)). In the case of field effect transistors, if impurities are introduced into the Sj-layer, carriers will migrate to the Si□-xGex side where the bandgap is smaller, reducing impurity scattering and achieving high mobility. .

(T. Pearsall et al., I.E.E., Electron Device Letters, Vol. 7 (198
6th grade) page 308) In the case of a bipolar transistor, the n-type Si emitter and the p
Since the band gap difference between the Si knee x Gex base acts as a barrier against hole injection from the base to the emitter, a sufficient current amplification factor can be ensured even if the base concentration is increased.

Increasing the concentration of the base is necessary for thinning the base and reducing base resistance, which are essential for increasing the speed of transistors.

(G. L. Patton et al., IE Electron Device Letters, Vol. 9 (198
[Problems to be Solved by the Invention] However, in the above conventional technology, the channel and base layers, which are most dominant in the operating speed of a transistor, are
Since it is formed from a disordered alloy called a (0<x<1) mixed crystal, there is a problem in that carriers are subject to alloy scattering and cannot exhibit sufficient high speed performance.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide the above-mentioned Peter structure free from alloy scattering, and to realize even higher speed operation of the transistor.

[Means to solve the problem]

The above object is achieved by using compressively strained elemental Ge as the channel of a field effect transistor and the base of a bipolar transistor.

Compressive strain is controlled and applied to the germanium layer by strain control layers provided below or above and below the germanium layer. A Si□-χ, Ge and S mixed crystal layer is used for the strain control layer, and by changing the mixed crystal ratio xs, the strain imparted to the germanium layer is controlled. That is, the lattice constant of the strain control layer is changed by the content of Si, which has a small lattice constant, and is made smaller than the lattice constant of the germanium layer grown continuously with the strain control layer, thereby imparting compressive strain.

[Effect]

The active M (channel,
The reasons for using compressively strained elemental Ge as the base (base) are as follows.

First of all, elemental Ge has a higher mobility of carriers (particularly holes) than Si and Si, Gex (0<x<1) mixed crystals. For example, as shown in Figure 3, the hole mobility at room temperature is approximately 1
An order of magnitude larger.

(K, Takeda et al., Journal of Physics C, Solid State Physics, No. 16
(1983), p. 2237) Secondly, it is theoretically predicted that compressive strain changes the valence band and reduces the effective mass of holes by nearly an order of magnitude. (For example, G. C. Osbourn, Journal of Vacuum Science and Technology A Vol. 3, (1985), p. 826) The reduction in effective mass is
This results in increased carrier mobility and saturation velocity.

Thirdly, confinement of holes to the Ge side at the S i,-xG ex/G e heterointerface and transfer from Ge to S 1
It is known that the band discontinuity value ΔEv (corresponding to the depth of the potential valley for holes) at the hetero interface, which is effective in blocking hole injection into l-xGex, increases. For example, considering the case of x=0.5, ΔEvχ0.1eV in a structure where Ge is not strained, whereas
In a structure where Ge has a compressive strain of 1%, ΔEvχ0.17
It is expected that it will be eV. (This is R, Peop
le et al.

Applied Physics Letters Volume 48.

(1986) p. 538. ) This is effective in realizing high current drive capability by increasing the number of carriers in field effect transistors, and in realizing high current amplification factors and low base resistance in bipolar transistors.

〔Example〕

A basic embodiment of the present invention is shown in FIGS. 1(a) and 1(b).

Shown in (c). In FIG. 1(,), an S 1l-XS Ge
FIG. 3 is a cross-sectional view showing a state in which a 1i-X Gex mixed crystal layer 4 is provided. FIG. 1(b) shows an application of such a structure to a MODFET, and FIG. 1(c) shows an application of such a structure to a bipolar transistor.

In this way, the present invention provides an S
i□-xGex/Ge/5it-x, Gex! ,/substrate (0<x, xs<1) heterostructure.

That is, the field effect transistor has a structure in which the Ge channel layer is subjected to compressive strain by the buffer layer as shown in FIG. 1(b). In a bipolar transistor, S 11-! 5 G e X5
The structure is such that a single buffer layer is used as a collector, and a Ge base and a Si1-xGex emitter are formed in a distorted manner on top of the collector.

On the example.

Next, a first example of the present invention in which a p-channel modulation doped transistor was specifically manufactured will be described.

As shown in FIG. 4, on the n-type Ge substrate 41,
nm S 11-x3 G e XS buffer fi4
2 (0,15<1 xs<0.45), and the substrate temperature 5
After heteroepitaxial growth was performed by molecular beam epitaxy (MBE) at 20°C, a 20 nm Ge channel layer 43.15 nm p-type Si,..., Geo, S layer 44 was grown at 400°C. Since the thickness of the buffer layer is sufficiently thick (more than the critical thickness for strained growth), many misfit dislocations occur at the interface with the Ge substrate, and the lattice constant becomes the same as that of bulk Si! ,G
e x is equal to 3 (strain relaxation growth), whereas the film thickness of the Ge and Sx o, 5 G e o, s layers is sufficiently thin, so the in-plane lattice constant is matched to the buffer layer and the growth ( distorted growth). The above is the cross section T E M
This was revealed by observation and Raman scattering spectroscopy. Fifth
Figure (a) shows the results obtained from Raman scattering spectroscopy. The strain in the Ge channel layer is shown as a function of the Si composition I xs of the buffer layer. The strain is compressive strain, and almost according to theory, I
It was found that it can be controlled in proportion to. However, 1
At xs"0.45, the Ge film thickness of 20 nm exceeds the critical film thickness and the strain is relaxed.

The p-type impurities are doped into the S i, , G eo, and s layers 44 by so-called doping. That is, first, at 400°C, 15 nm of Sio, sGe,...
After growing the film, the temperature of the substrate is kept below 100°C, Ga is adsorbed on the surface, and then 15 nm of amorphous S'1B, sGeo
, 5 films were deposited. Thereafter, by heating to 450° C., this film was single-crystalized by solid-phase epitaxial growth, resulting in a structure in which Ga was embedded in the Si, Ge, e film in the form of a spike. An AnGa electrode was installed on this structure and the electrical conductivity properties were investigated.

FIG. 5(b) shows the mobility and concentration of holes as a function of 1-XS, determined by Hall effect measurement at 77K. When I xs<0.25, the hole mobility and concentration tended to increase with strain as expected, but when I xs>0.25, it was found that they conversely decreased. As a result of cross-sectional TEME observation, it was revealed that the number of penetrating dislocations increased rapidly in this region, suggesting that the concentration and mobility of holes were reduced due to dislocations. Therefore, in order to reduce the penetration dislocations, Si□
-x, Gex, the thickness of the buffer layer is increased to 2 μm,
Also, S l 1-XS G e X at the interface with the Ge substrate
S/Ge/Si, x, Gsxs/Ge/...
......A superlattice layer was provided. This results in 1
Hole concentration and mobility increased in the region of xs>0.25.

(Fig. 5(c), (d)) However, 1-xs) When Q, 4 and Ixs<0.1-5, the Ge channel layer 43 or the Si,..., Geo, s layer 44 is Two-dimensional hole gas could not be observed because dislocations were generated and the strain relaxation grew. (Dot in the figure) That is, Ge film thickness 2
0 nm Si (1, sG ea, s film thickness 30 nm
Under the conditions, it is effective to select 0.2<1 xs<0.4. When the Ge film thickness and Si,...,Geo,5 film thickness are both 10 nm, the range of IXS is O<1. − x s < 0, it is possible to expand to 5. (In this example, a Ge substrate was used, but S
Similar results were obtained using the i-substrate. ) The maximum value of the hole mobility achieved by the present invention is ↓5000m”
/vs (77K), which is more than 10 times the conventional value.

Furthermore, a field effect transistor was fabricated by using Ti as the gate electrode 46. The gate length is approximately 2 μm. The value of field effect mobility calculated from the dependence of transfer conductance g on gate voltage Va is also 10000 cm"/v
-s or more.

Next, as shown in FIG. 4(b), a WSi gate 49 and a p
A MOSFET with a submicron gate length and a positive region was fabricated. In order to prevent punch-through due to the shortening of the channel, an SB doping spike 51 is provided. For Si n-channel MO8FET, the channel length is 0.1 μm.
It is known that so-called velocity overshoot, in which the carrier velocity exceeds the saturation velocity, cannot be observed unless the carrier velocity is below (for example, G, A, 5
aj-Halosz et al. IEE Electron Device Letters, Volume 9, (1988),
(Page 464) Due to the high mobility of the FET of the present invention, even at a channel diameter of 0.3 μm, the velocity
We were able to improve performance through ty overshoot.

Example 2 Next, an example in which a p-channel, channel-doped field effect transistor was manufactured will be described.

As shown in FIG. 6, the p-type Ge channel layer 61 is made of Ge.
B is grown by CVD (chemical vapor deposition) method compatible with ultra-high vacuum using H4 gas, and B is grown by IX using B2HG gas.
The strained Ge layer 61 is doped with 10" am-3. The mobility of the strained Ge layer 61 is about twice that of the bulk Ge N41, and together with the high hole concentration, the transfer conductance at room temperature is equivalent to that of a modulation top transistor. value was achieved.

In FIG. 6, parts indicated by the same reference numerals as in FIG. 4 indicate the same or equivalent parts as in FIG. 4.

Example 3 Next, an example of manufacturing a hetero bipolar transistor using two-dimensional hole gas (2D HG) will be described.

As shown in FIG. 7(a), a layer with a thickness of 8.
00 nm n"S i,, tSGe, 5 ml director layer 72, 200 nm n"'S io, 5Ge,...
5 collector M73 was heteroepitaxially grown by the MBE method at a substrate temperature of 520'C, and then 20. nm non-doped Ge base layer 74, Ga doping spike 4
5 was set. 20 nm thick non-doped Sio,,G
ea, layer 80, 80 nm n”S io, ,G e
O and c emitter layers 75 were sequentially formed.

In this structure, non-doped S 10.4G eo, 6/
The two-dimensional hole gas formed at the Ge heterointerface acts as an ultra-thin and low-resistance base layer. After confirming the basic operation of a bipolar transistor using the structure shown in FIG. 7(a), a transistor using the structure shown in FIG. 7(b) with reduced parasitic elements was fabricated.

In this structure, the external base is formed by forming the base and emitter layers on the CVD5 i○2 film 7 film 6 which has an opening in the part corresponding to the intrinsic base region.
+Polycrystalline Ge film is used to significantly reduce parasitic resistance and parasitic capacitance caused by this external base. By using this structure, we achieved a performance of fT=150 GHz.

Example 4 Next, an example in which a hetero bipolar transistor using a p-type base layer having a normal structure was manufactured will be described.

The P-type Ge base [81 was formed in the same manner as in Example 2, and the B doping concentration was I x 101 gcm-3. Due to the high electron mobility within the Ge base, a performance of fr=150 GHz was also obtained in this structure.

In Fig. 8, the parts indicated by the same reference numerals as in Fig. 7(b) are the same.
or equivalent parts.

Example 5 Next, an example in which a p-channel field effect transistor using a two-dimensional hole gas and a bipolar transistor are integrated (monolithically) fabricated on the same substrate will be described.

As shown in FIG. 9, the structures in the depth direction of both transistors are completely the same, and the bipolar transistor was manufactured using almost the same process as that of the bipolar transistor shown in Example 3. Ultra-high-speed logic circuits have been created by monolithically integrating bipolar transistors with large current drive capabilities and field-effect transistors suitable for high integration. In FIG. 9, 91 is a substrate bias electrode, 92 is n"Sio, 2, Ge0.7. buffer layer, 93 is n-8i, 5G e, 7. buffer layer, 94 is n ” S jo, G e a,
r and N are shown.

Example 6 Finally, an example in which p-channel and n-channel modulation tope transistors were monolithically manufactured will be described.

As shown in FIG. 10, the P-channel transistor has the same structure as in the embodiment, and the N-channel transistor has the following structure.
This is a structure in which the Ge layer 101 grown with strain relaxation serves as a channel. This means that if Ge'ff110↓ is not distorted, S io...G e. , 85/G e This is because the band discontinuity value of the conduction band at the heterointerface becomes large.

According to the present invention, a complementary logic circuit with high speed and low power consumption can be manufactured. 102 in FIG. 10 is S 1o14. G
The eIl,lls mixed crystal layer, 103, shows the S5 doping spike.

〔Effect of the invention〕

According to the present invention, high-mobility, high saturation velocity, and high-concentration two-dimensional hole gas formed in a single Ge layer having compressive strain can realize high-speed field effect transistors and bipolar transistors.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the basic structure of the present invention, FIG. 2 is a sectional view of a known example, FIG. 3 is a temperature characteristic diagram of hole mobility of Ge, and 4.6, 7, 8, 9. FIG. 10 is a sectional view of an embodiment of the present invention, and FIG. 5 is a diagram showing the experimental results that form the basis of the present invention. 1...Substrate, 2-Slily, 3GeXS buffer layer, 3...GeJli4-S], 1-XGexM ' (no change in content) Ka warm (phantom-r no (2) A degree CK) Ka 4 times (phantom chart (b) ρ I・l II' L!J・3 /・4 ha'wa77- Normal δr#A I・5 1-χS Z/ Gate t(2, +YaneIL斥Oh-ru0yashari斥 [r-Ryo-nley-g Kinuta e false\4 (0 9 Figure man/ρ Figure /θ3 Shtohi'n7-Suha14no

Claims (1)

Claims: 1. A semiconductor device characterized in that the layer on which carriers travel is made of a germanium layer, the germanium layer is provided on a strain control layer, and the germanium layer has compressive strain. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a p-type impurity is introduced into a strain control layer close to a germanium layer. 3. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a p-type impurity is introduced into a germanium layer. 4. In the semiconductor device according to claim 3, the strain control layer is made of Si_1_-_x_sGe_x_s mixed crystal, and the mixed crystal ratio xs of the strain control layer is 0.5≦xs.
A semiconductor device characterized in that ≦0.9. 5. A semiconductor device characterized in that the base layer is made of a germanium layer, and the germanium base layer has compressive strain. 6. In the semiconductor device according to claim 2,
The above germanium base layer is P-Si_1_-_xGe_x (0<x<1)/i-G
A semiconductor device characterized by having a structure consisting of e. 7. In the semiconductor device according to claim 2,
A semiconductor device characterized in that a P-type impurity is introduced into the germanium base layer. 8. A semiconductor device comprising a substrate, a strain control layer provided on the substrate, a germanium layer provided on the strain control layer, and a first layer provided on the germanium layer, A semiconductor device characterized in that a carrier of the semiconductor device described above travels through a germanium layer. 9. The semiconductor device according to claim 8, wherein the germanium layer is a channel layer of a field effect transistor, and a gate electrode is provided on the first layer. 10. The semiconductor device according to claim 8, wherein the germanium layer is a base layer of a bipolar transistor. 11. The strain control layer is Si_1_−_x_sGe_x
_s mixed crystal layer, and the mixed crystal ratio xs is 0.5≦xs
11. The semiconductor device according to claim 8, wherein ≦0.9. 12. The thickness of the germanium layer is 10 nm or more, 3
12. The semiconductor device according to claim 8, wherein the semiconductor device has a thickness of 0 nm or less. 13. The strain control layer is made of Si_1_-_x_sGe_x
_s mixed crystal, and 0.15≦1−xs≦0.4
The semiconductor device according to any one of claims 8, 9, 10, and 12, characterized in that: