JPH02196436A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high speed element by constituting a channel layer of Ge semiconductor and making the channel layer be sandwiched between layers of Si or SiGe mixed crystal. CONSTITUTION:A channel layer 2 in which carrier travels is constituted of a Ge semiconductor layer buried in a semiconductor layer. The channel laver 2 constituted of Ge semiconductor is sandwiched between layers 3 of Si or SiGe mixed crystal. For example, on an Si substrate 1, the following are arranged; the channel laver 2 of Ge, the Si layer 3 formed on both sides of the channel layer 2, a gate electrode 4, and a source.drain 5, 6. An SiGe mixed layer may be used instead of the Si layer 3. At least a part of the layer 3 formed on both sides of the channel layer 2 is desirably doped with P-type impurity. The thickness of each layer is desirably as follows; the Ge channel layer 2 is 200Angstrom or less, and the Si or SiGe mixed layer 3 formed on both sides of the channel layer 2 is also 200Angstrom or less.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a field effect type semiconductor device having high mobility.

[Conventional technology]

Conventionally, in field effect transistors using Si and compound semiconductors such as GaAs and AjGaAs, a structure has been proposed in which a channel layer through which carriers travel is embedded in the semiconductor. To form a buried channel, it is necessary to create a potential depression to confine carriers (electrons or holes).

For this purpose, a method of using a heterostructure of different types of semiconductors having different band structures, and a method of creating a potential distribution by selectively doping impurities are well known.

Figure 2 (a) is an example of the former, in which the channel is a GaAs layer sandwiched between GaAlAs with a large bandgap. Electrons supplied from the GaAlAs layer form a potential well. It runs trapped in layers. This is 1 normal double hetero MODF
It is called ET (modulation doped field effect transistor). (For example, K., Inoue et al., Japanese Journal of Applied Physics, Vol.
Volume 3, No. 2 (1984), pages L61 to 63 (JPN
, J, Appl, phys, VoQ, 23 & 2
(1984) ppL61-63)) On the other hand, Figure 2(b) is an example of the latter, with n in Si.
A thin film doped with type impurities is provided, and a well is formed using the potential created by the dopant ions.
! It also serves as a channel layer. This is commonly called a doped channel FET. (For example, A. Gorku+s et al., Japanese Journal of Applied Physics, Vol. 26, No. 12 (1987) No. L1933-1.
936 pages (TPN, J, Appl, phys-
Vo Q, 26 & 12 (1987) ppL193
3-1936)) The former MODFET is characterized by the absence of impurity ions in the channel, so there is no impurity scattering and high mobility;
A channel FET is characterized in that the carrier concentration in the channel can be increased.

[Problem to be solved by the invention]

However, the above structure has problems due to the physical properties of Si or GaAs. That is, Ga
A s has a high electron mobility (8600 d/V at room temperature
5ee), but the hole mobility is small.

(250 cxl/V-sac at room temperature) Therefore, it is a problem when forming P mMODFETs with n-type and creating complementary logic circuits. Also, dop of Si
An edchannel FET has a problem in that its mobility is reduced by about one order of magnitude compared to an undoped device due to scattering caused by impurity ions present in the channel.

An object of the present invention is to provide a field effect transistor that solves the above problems.

[Means to solve the problem]

The above object is achieved by using Go as the channel layer instead of conventionally used Si, GaAs, etc. in a semiconductor device having a structure in which the channel layer in which carriers travel is embedded in the semiconductor. .

As a disclosure of more specific means, the above-mentioned MOOFT
In the structure, a structure in which a Ga layer is sandwiched between Sj or 5iGe mixed crystal layers as shown in FIG. 1(a) is used, or in the above doped channel FET, Si is used as the material as shown in FIG. 1(b). G instead of
Use e.

Here, in the above-mentioned MODFET structure, the composition of the layers above and below the Ge layer is S i 1-XG ex/G e /
They may be different from each other such as S i 1-X'G ex' structure, and S 1t-xGax/Ge/S 1t
-xGaxloe... As shown in the structure, multiple Ga layers are
Alternatively, it may be sandwiched between SiGe mixed crystal layers to form a superlattice structure.Also, it is preferable to dope the Si or 5iGe mixed crystal layer with a p-type impurity as an impurity.
s On the other hand, in the above-mentioned doped channel FET, it is preferable to dope the Ga layer with an n-type impurity as an impurity.

[Effect]

Go has several electrical conductivity characteristics compared to Si, GaAs, and the like. Figure 3 shows Si
, Of3. This is a diagram showing the relationship between doping concentration and mobility for GaA+s.

The characteristic of Gs is that the hole mobility is i in the low doping region.
The electron mobility is extremely large at 900 at/V·see, and the doping concentration is 10"cll-" to 10.
Even if it is increased to "cn-", it will only decrease to about -.

The former feature is useful in MODFET structures.

FIG. 4 shows a band diagram of the structure shown in FIG. 1(a). Holes travel through GeM with high hole mobility, which is supplied from the upper and lower p-type 5iGe layers and forms a potential well. Here, the Ge layer is under compressive stress due to the difference in lattice constant between SiGa and Ge. This compressive stress is effective from the following two viewpoints. One is that when GeM is strained, the difference ΔEv between the valence band edge and the 5iGe layer, which is the depth of the potential well, increases.
For example, as a 5iGe mixed crystal, S ia, +sG e
If o and s are used, in a structure where G6 is not distorted, ΔE
.

20.11 eV, whereas when Ge is strained, Δ
Ev is 0.24 eV, which is advantageous for hole confinement.

Second, compressive stresses reduce the effective cover of the hole by as much as about -1 in some cases. In other words, the mobility increases approximately 10 times.

Therefore, a high performance structure can be obtained as a p-type MODFET.

It should be noted that although the effect zero hand body caused by radial compressive stress is known, the present invention specifically applies compressive stress,
It is important that the structure of the semiconductor device is such that the above effects can be produced.

Next, the second characteristic of electrical conduction of Ge is that it is doped
It works effectively in channel FET. That is, even if the Go channel is doped at a high concentration, the electron mobility does not decrease that much.

A mobility approximately 10 times that of Si can be achieved in a highly doped region. Therefore, doped channelF
The shortcomings of ET can be improved.

〔Example〕

(Example 1) First, an example of creating a Ge embedded channel MODFET will be described.

In FIG. 1(a), 1 is a Si substrate, 2 is a channel layer made of Ge, and 3 is a Si layer formed on both sides of the channel layer. Reference numeral 4 indicates a gate electrode, and reference numerals 5 and 6 indicate a source and a drain, respectively. A 5iGe mixed crystal layer may be used in place of this Si layer 3. At least a portion of the layers provided on both sides of this channel layer may contain impurities. Preferably, it is doped with P-type impurities.

The concentration of p-type impurity is 5×10F to 5×10L
About 6cn-' is preferable. The preferred thickness of each layer is approximately 200 Å or less for a Ge channel layer, and approximately 200 Å or less for a Si or S x Ge mixed crystal layer provided on both sides of the channel layer.

Next, a more detailed explanation will be given using FIG. 5.

Figure 5 shows its structure. It has a structure in which an i-type Ge channel 54 with a thickness of 50 people is sandwiched between p-type Sio, 5Geo, 352y56, and i-type Ga and p-type Sio, sG.
Spacer layers 53 and 55 of i-type S io, aG ao, and s are provided between e o and a. Ti was used for the gate electrode 58.

Sufficiently thick (>5000 layers) p-type Si on the Si substrate 51
o, 3G 80. +152 was epitaxially grown, and on top of that, 100 A i type Si o, sG e o,
+553150 people i type G e 54 / ], OO people i type Sio, IlG e o, s55/100 people p type S
io, sG eo, G56 / 100 people i type Si
1-xG x (x = 0, 5→0)57 was subsequently grown. For epitaxial growth, vapor deposition in an ultra-high vacuum (molecular beam epitaxy) was used, and the growth temperature was 5.
Below 50°C, for p-type doping, G a K-cel
The concentration was 1.0"am-'.

The Hall mobility of the channel part of the above MOOFET is 3
About 3000d/V-8, about 2000O at 77 at 00
L: Il/V-S, Sheet-It-Ya-Ya density is approximately i x 10''a++-2. Also, the effective mass of the holes is 1,1 mo (m.

: electronic trade fit). From the above results, MODFE
As gm (transfer conductance) of T, 200 m
s/I can be realized.

In the above, a Schottky gate electrode was used, but
Similar results were obtained using a MOS structure;
An increase in g was obtained by forming the channel portion into a superlattice channel structure that is repeated multiple times.

Note that the substrate is not limited to Si, and for example, a Ge substrate can also be used. Further, as a crystal growth method, a CVD method which is excellent in mass productivity may be used.

(Example 2) Next, the Go buried channel p-type MOD described in Example 1
An example in which a FET and a Ga channel n-type MOOFET are formed on the same substrate will be described.

As shown in FIG. 6, an i-type Si
, sG e o, 11 After growing 5000 layers of buffer layer 62, 50 layers of i-type Ge channel layer 63 were grown.
Cover with a 5ins film of i-type Go channel layer 64. n
Ge and Sio deposited on the mS
, zgGeo, and as are removed together with the 5iOz film, then the n-type MODFET portion is covered with a 5ift film.

p-type Sio, sGeo, and sse were grown.

Ge and Si o on 5ift by the same process as before
, sG e o, 8, the gate electrodes 67, 6
8 was formed.

In this structure, as mentioned above, the Ge of the p-type MOOFET is
The channel is compressed and distorted, has a large ΔEv, and is effective for hole confinement, while at the same time
Ge is not strained, has a large ΔEc, and is effective for electron confinement.

If the present invention is used, both n and P G
O-channel MODFETs can be integrated, which is effective for increasing the speed of complementary logic circuits.

In addition, in order to further increase ΔEc (~0.15 eV), an n-type MODF [ET channel-distorted Si
(Figure 7).

(Example 3) Finally, Go embedded doped channel F
An example of forming ET will be described.

In FIG. 1(b), 7 is a Ge substrate, and 8 is a Ge channel layer doped with n-type impurities.

4 is a gate electrode, and 5 and 6 are a source and a drain, respectively.

The concentration of n-type impurity in the Ge channel layer is 1012
~10L40-2 is preferred, and approximately 1018 is optimal.

Next, a more detailed explanation will be given using FIG. 8.

As shown in FIG. 8, a p-type Si substrate 81 is provided with a p-type Si
After growing 5,000 layers of o, aG e o, a ballast layer 82, 3,000 layers of p-type Ge layer 83 were formed.

Immediately after the Ge growth, sh was vapor-deposited in a molecular beam epitaxy apparatus, and the sb atoms were removed by heating it at 600° C., leaving only the sb monoatomic layer 84. Next, lower the substrate temperature to 50°C.

After depositing 500 pieces of amorphous Ge, it was heated to 600°C.
This was made into a single crystal by solid-phase epitaxial growth.

For the above structure, a gate of 5ins was formed by plasma CVD.
A film 86 was deposited, an AQ gate electrode 87 was provided, and As was ion-implanted using this as a mask to form a source 78 and a drain 89.

dopad Ge channel MOSF of the present invention
Since ET has a mobility approximately 10 times greater than that of Si in a high concentration region, it was possible to achieve a gm (transfer conductance) five times greater than that of the conventional structure.

〔Effect of the invention〕

According to the present invention, a high-speed device can be realized by using Ge as a channel layer in which carriers travel.

In MOOFET, the mobility of not only electrons but also holes can be significantly increased, and it is effective for complementary logic circuits.

A doped channel FET not only has a high sheet carrier concentration, but also suppresses a decrease in electron mobility and can achieve high transfer conductance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the basic structure of the present invention, and FIG. 2 is a sectional view showing the basic structure of the present invention.
3 is a cross-sectional view showing the basic structure of a known example; FIG. 3 is data explaining the electrical conduction features of Ge; FIG. 4 is a diagram showing the band structure; FIGS. 5, 6, 7, and 8 The figure is a cross-sectional structural diagram showing an embodiment of the present invention. 2...Ge channel, 3...Si or Si
Ge mixture, 8...doped Ge channel. Tomi 2 Figure (again) (D) Strategy diagram (Kun χ Ward 1 \ 7-Ten) Jη concentration (C 笈-Li factor Δ0 Tre 1 No. 1) Daito t'-mu \ 6th Fl

Claims (1)

[Claims] 1. The channel layer through which carriers travel is made of a Ge semiconductor embedded in a semiconductor layer, and the channel layer made of the Ge semiconductor is made of a layer of Si or SiGe mixed crystal,
A semiconductor device characterized by being sandwiched. 2. The semiconductor device according to claim 1, wherein a part of the Si or SiGe mixed crystal is doped with a p-type impurity. 3. A channel layer made of the Ge semiconductor, and the S
3. The semiconductor device according to claim 1, wherein the thickness of the i or SiGe mixed crystal layer is 200 Å or less. 4. A semiconductor device having a structure in which a channel layer through which carriers travel is made of a Ge semiconductor, and the channel layer made of the Ge semiconductor is doped with an n-type impurity. 5. The semiconductor device according to claim 4, wherein the channel layer made of the Ge semiconductor has an impurity concentration of 10^1^2 to 10^1^4 cm^-^2. 6. The semiconductor device according to claim 1, wherein the semiconductor device has a superlattice structure in which a plurality of sets of the channel layer made of the Ge semiconductor and the Si or SiGe layer are stacked alternately. 7. A semiconductor device comprising the p-channel semiconductor device according to claim 1 and an n-channel semiconductor device mounted on the same substrate. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a MOS field effect transistor.