WO2020009020A1 - Tunnel field-effect transistor - Google Patents

Tunnel field-effect transistor Download PDF

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Publication number
WO2020009020A1
WO2020009020A1 PCT/JP2019/025825 JP2019025825W WO2020009020A1 WO 2020009020 A1 WO2020009020 A1 WO 2020009020A1 JP 2019025825 W JP2019025825 W JP 2019025825W WO 2020009020 A1 WO2020009020 A1 WO 2020009020A1
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layer
ingaassb
inp
effect transistor
tunnel
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PCT/JP2019/025825
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French (fr)
Japanese (ja)
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学 満原
拓也 星
杉山　弘樹
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日本電信電話株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a planar type tunnel field effect transistor.
  • IT devices such as network devices, servers, PCs, and mobile terminals are required to have a performance capable of processing a large amount of data at high speed.
  • IoT Internet of Things
  • power consumption of the IT device in the total power will increase sharply with the high performance of the IT device.
  • MOSFETs field-effect transistors
  • the power consumption of the MOSFET is proportional to the square of the drive voltage. Therefore, if the MOSFET can be operated at a low drive voltage, the power consumption of the IT device can be reduced as a result.
  • an on state and an off state are switched by changing a drain current according to a gate voltage.
  • a gate voltage In order to reduce the drive voltage of the MOSFET, it is important to rapidly change the drain current with a small gate voltage.
  • the gate voltage required to increase the drain current by one digit is used as an important performance index, and this physical quantity is called an S value (unit: mV / decade). The lower the S value, the lower the drive voltage can be expected, which leads to lower power consumption of the MOSFET.
  • MOSFETs In MOSFETs, studies are underway to reduce the S value by examining the device structure and channel material. At present, the most widespread field-effect transistor is a MOSFET, and the on / off operation is switched by changing the drain current by raising and lowering the energy position of a conduction band serving as a current path by a gate voltage. . With this MOSFET, it is difficult in principle to realize an S value smaller than 0.6 mV / decade. Therefore, it is difficult to dramatically reduce the power consumption of the MOSFET.
  • tunnel field effect transistor Since the tunnel field effect transistor (TFET) operates on a principle different from that of the MOSFET described above, the S value can be made smaller than 0.6 mV / decade. By using this tunnel field effect transistor, an on / off operation can be realized with a drive voltage smaller than that of a MOSFET. Therefore, in recent years, research and development of tunnel field effect transistors have been energetically advanced. Several device structures have been studied for the tunnel field effect transistor. Among them, a planar tunnel field effect transistor is a particularly promising structure because it has an element structure similar to that of a MOSFET and a MOSFET can be applied to a manufacturing process in many cases.
  • the planar type tunnel field effect transistor has a structure similar to the MOSFET as described above.
  • the tunnel field effect transistor includes, for example, a channel region 301 made of a compound semiconductor, a source region 302, and a drain region 303 formed at a predetermined interval from the source region 302.
  • the source region 302 is formed by making the channel layer 301 p-type
  • the drain region 303 is formed by making the channel layer 301 n-type.
  • a channel region 304 is formed in a region of the channel layer 301 between the source region 302 and the drain region 303.
  • the source region 302, the channel region 304, and the drain region 303 are arranged in this order in a gate length direction on a plane parallel to the surface of the channel layer 301.
  • a source electrode 305 is formed in connection with the source region 302, and a drain electrode 306 is formed in connection with the drain region 303. Further, a gate electrode 308 is formed over the channel region 304 with a gate insulating layer 307 interposed therebetween.
  • the difference between the tunnel field effect transistor and the MOSFET is the conductivity type of the source region and the drain region.
  • a MOSFET n-type MOSFET
  • the source region and the drain region are both n-type doped.
  • the tunnel field effect transistor n-type TFET
  • the source region 302 is p-type and the drain region 303 is n-type.
  • the tunnel field effect transistor has a pn junction, and this pn junction becomes a tunnel junction.
  • the interface between the channel region 304 and the source region 302 becomes the tunnel junction region 311.
  • an electric field applied to the tunnel junction region 311 is controlled by a gate voltage, so that a current flowing to the drain region 303 is changed to perform an on / off operation.
  • One of the important performance indicators of a tunnel field effect transistor is the ratio of the current in the on state to that in the off state. Specifically, assuming that the current in the on state is the on current and the off current in the off state, the higher the ratio of the on current to the off current (I ON / I OFF ), the better the device characteristics.
  • I ON / I OFF the ratio of the on current to the off current
  • the off-state current also increases, so that I ON / I OFF does not always increase. Therefore, it is difficult to obtain a high I ON / I OFF even if the tunnel field effect transistor is manufactured using only a material having a small band gap.
  • the band gap of ⁇ ⁇ ⁇ ⁇ InP ( ⁇ 1.35 eV) is larger than that of silicon ( ⁇ 1.12 eV), and high-quality products are commercially available as substrates. Further, it is relatively easy to grow a material such as InGaAs having a smaller band gap than silicon on InP using the substrate as InP. For this reason, studies are being made to apply InGaAs grown on an InP substrate or a quantum well made of InGaAs to the channel layer of a tunnel field effect transistor, and good device characteristics have been confirmed in the manufactured device (non-device). Patent Document 2, Non-Patent Document 3).
  • GaAsSb is a material that can be lattice-matched to InP and has a band gap as small as InGaAs.
  • a crystal having a large Sb composition ratio is difficult to grow (see Non-Patent Document 4), there are not many devices using GaAsSb at present.
  • the band gap of the material used for the channel region can be made smaller than InGaAs lattice matching with InP.
  • One of the methods is a method disclosed in Non-Patent Document 3 in which an InGaAs quantum well having a large In composition ratio is used for a channel layer. When using an InGaAs quantum well, it is necessary to increase the In composition ratio and increase the layer thickness in order to reduce the band gap.
  • the present invention has been made to solve the above problems, and has as its object to improve the device characteristics of a planar tunnel field effect transistor.
  • a tunnel field effect transistor includes a channel layer including an InGaAsSb layer formed of InGaAsSb formed on an InP layer formed of InP, a first conductivity type source region formed in the channel layer, and a source region.
  • a second conductivity type drain region formed in the channel layer at a predetermined interval, a source electrode formed in connection with the source region, a drain electrode formed in connection with the drain region, and a source region.
  • a gate electrode formed on a channel region between the drain region and the drain region, and the InGaAsSb layer has a composition ratio of Sb in the group V element of 0.01 to 0.3.
  • the channel layer may have a quantum well structure in which an InGaAsSb layer is a well layer and a layer made of InGaAs or InGaAsSb is a barrier layer.
  • the well layer may have a thickness of 4 nm or more and 20 nm or less, a lattice constant larger than that of InP, and a compressive strain of 3.5% or less.
  • the barrier layer is preferably made of InGaAsSb, has a smaller lattice constant than InP, and has a tensile strain.
  • FIG. 1 is a sectional view showing a configuration of the tunnel field effect transistor according to the first embodiment of the present invention.
  • FIG. 2 is a characteristic diagram showing a result obtained by calculating a change in band gap according to the Sb composition ratio of InGaAsSb.
  • FIG. 3 shows the calculation of the tunnel current density for each of the case where the channel layer is composed of Si, the case where the channel layer is composed of InGaAs lattice-matched to InP, and the case where the channel layer is composed of InGaAsSb lattice-matched to InP.
  • FIG. 9 is a characteristic diagram showing the result of comparison.
  • FIG. 4 is a characteristic diagram in which a part of each result of the case where the channel layer shown in FIG.
  • FIG. 3 is a characteristic diagram showing electric field intensity dependence of current density.
  • FIG. 8 is a characteristic chart showing the results obtained by using the calculation method described in Non-Patent Document 7 to determine the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.1 when the lattice strain (compression strain) is changed.
  • FIG. 9 is a graph showing the results obtained by using the calculation method described in Non-Patent Document 7 to determine the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.2 when the lattice strain (compression strain) is changed.
  • FIG. FIG. 10 is a sectional view showing a layer structure of a multiple quantum well structure actually manufactured.
  • FIG. 10 is a sectional view showing a layer structure of a multiple quantum well structure actually manufactured.
  • FIG. 11 is a characteristic diagram showing a comparison between a measurement result (experiment) of an X-ray diffraction pattern of the manufactured multiple quantum well structure and a simulation result.
  • FIG. 12 is a characteristic diagram showing a photoluminescence emission spectrum at room temperature of the manufactured multiple quantum well structure.
  • FIG. 13 is a cross-sectional view showing a configuration of the tunnel field effect transistor.
  • FIG. 14 is a band diagram showing a change in band gap near the tunnel junction region in the ON state (solid line) and the OFF state (dotted line) of the tunnel field effect transistor.
  • This tunnel field effect transistor includes an InP layer 102 made of InP formed on a substrate 101, and a channel layer 103 formed on the InP layer 102.
  • the channel layer 103 includes an InGaAsSb layer made of InGaAsSb.
  • the channel layer 103 is an InGaAsSb layer.
  • the InGaAsSb layer has a composition ratio of Sb in the group V element of 0.01 to 0.3.
  • a source region 104 and a drain region 105 are formed at predetermined intervals.
  • the source region 104 has a first conductivity type (for example, p-type), and the drain region 105 has a second conductivity type (for example, n-type).
  • a source electrode 107 is formed so as to be electrically connected to the source region 104, and a drain electrode 108 is formed so as to be electrically connected to the drain region 105.
  • the first conductivity type may be n-type and the second conductivity type may be p-type.
  • a gate electrode 109 is formed on the channel region 106 between the source region 104 and the drain region 105.
  • the gate electrode 109 is formed over the channel region 106 of the channel layer 103 with the gate insulating layer 110 interposed.
  • the gate electrode 109 may be a Schottky connection with the channel layer 103.
  • the source region 104, the channel region 106, and the drain region 105 are arranged in the gate length direction on the plane parallel to the surface of the channel layer 103 in this order.
  • the interface between the channel region 106 and the source region 104 becomes the tunnel junction region 121.
  • an electric field applied to the tunnel junction region 121 is controlled by a gate voltage, so that a current flowing to the drain region 105 is changed to realize an on / off operation.
  • an InP layer 102 having a thickness of 0.1 ⁇ m and an InGaAsSb layer (channel layer 103) having a thickness of 0.1 ⁇ m are epitaxially grown on a substrate 101 made of semi-insulating InP.
  • an InP surface protection layer having a thickness of 20 nm is grown on the InGaAsSb layer. Note that the InP surface protective layer is not shown in FIG. 1 since it is completely removed by etching at the element stage.
  • TIn trimethylindium
  • TAGa triethylgallium
  • PH 3 phosphine
  • AsH 3 arsine
  • TDMASb trisdimethylaminoantimony
  • MOMBE organometallic molecular beam epitaxy
  • the Sb composition ratio of the channel layer 103 is set to 0.15, and the group III composition is adjusted so as to substantially match lattice with InP.
  • an epiwafer is prepared in which only the channel layer 103 shown in FIG. 1 is replaced with InGaAs which is substantially lattice-matched to InP.
  • the band gap is 0.69 eV for InGaAsSb and 0.74 eV for InGaAs.
  • Si is ion-implanted only into a region to be a drain, and a necessary heat treatment is performed to activate the Si, thereby forming a drain region 105.
  • ALD atomic layer deposition
  • the wafer is heated in a metal organic vapor phase epitaxy (MOVPE) apparatus while supplying phosphine and diethyl zinc (DEZn), so that part of the InGaAsSb is made p-type and the source region 104 is formed.
  • MOVPE metal organic vapor phase epitaxy
  • a gate insulating layer 110 is formed in a region to be a gate by depositing an insulating material by an atomic layer deposition method, a metal to be a gate electrode 109 is deposited by an electron beam deposition apparatus. By using a lift-off process, metal deposited on portions other than the gate electrode 109 is removed. In FIG. 1, the length of the gate electrode 109 in the horizontal direction (gate length direction) is 1 ⁇ m. After removing the insulating film deposited over the regions to be the source electrode and the drain electrode, the source electrode 107 and the drain electrode 108 are formed by a lift-off process. Thereafter, a heat treatment necessary for electrode formation is performed.
  • the planar-type tunneling electric field transistor using InGaAsSb for the channel layer 103 in the first embodiment shown in FIG. 1 has a drain current of 1.0 m under the condition that the source voltage is 60 mV and (gate voltage ⁇ threshold voltage) is 1 V. 7 ⁇ 10 ⁇ 1 ⁇ A / ⁇ m, and the minimum value of the S value is 55 mV / dec. It is.
  • the drain current of the tunnel electric field transistor using InGaAs for comparison as the channel layer under the same voltage condition is 1.3 ⁇ 10 ⁇ 1 ⁇ A / ⁇ m, and the minimum value of the S value is 63 mV / dec. . It is. From these results, it can be seen that in the planar tunneling electric field transistor, by changing the channel layer from InGaAs to InGaAsSb, the drain current can be increased and the S value can be reduced.
  • the metalorganic molecular beam epitaxy method is used as the crystal growth method.
  • InGaAsSb on InP can be crystallized by using another growth method such as the metalorganic vapor phase epitaxy method or the molecular beam epitaxy method. Can grow. Therefore, it is apparent that the tunnel electric field transistor using InGaAsSb as the channel layer 103 in Embodiment 1 can be manufactured by any crystal growth method that can grow InGaAsSb.
  • the band gap can be made smaller than that of InGaAs.
  • the Sb composition ratio of InGaAsSb is 0.15
  • the Sb composition ratio is 0.01 or more and 0.3 or less
  • InGaAsSb can be relatively easily crystal-grown. Therefore, needless to say, the present invention is effective even when InGaAsSb that does not lattice-match with InP is used, and when InGaAsSb having an Sb composition ratio other than 0.15 is used for the channel layer.
  • the source region 104 and the drain region 105 are formed by doping, Zn diffusion and ion implantation of Si are used, respectively.
  • Various doping methods other than the above are known. For this reason, the doping method is not limited to the above method.
  • the Sb composition of the channel layer 103 in the tunnel field effect transistor according to the first embodiment will be described.
  • a structure in which a material having a small bandgap is stacked as a channel layer on a layer having a large bandgap or a substrate is useful for improving device characteristics of a planar tunnel field effect transistor.
  • a structure in which InGaAs is grown on an InP layer (InP substrate) has been used.
  • InGaAsSb is useful as a material having a small band gap. This is because the band gap of InGaAsSb can be reduced even when the lattice constant is the same as that of InGaAs. In addition, in InGaAsSb, it is easy to obtain good crystallinity if the Sb composition ratio is small.
  • InGaAsSb also contains Sb as a group V element, but when the Sb composition ratio is small, a high-quality crystalline film can be grown (see Non-Patent Document 5). Further, InGaAsSb has an advantage that the band gap can be made smaller than that of InGaAs even if the Sb composition ratio is small, as described below.
  • FIG. 2 shows a result obtained by calculating a change in band gap depending on the Sb composition ratio of InGaAsSb.
  • the case where the lattice mismatch with InP is 0% is the band gap of InGaAsSb in the case of lattice matching with InP.
  • the bandgap of InGaAsSb lattice-matched to InP is such that when the Sb composition ratio is increased, the Sb composition ratio decreases from 0 to 0.25, is almost constant from 0.25 to 0.30, and is 0.30. It increases when it gets bigger. That is, in the case of InGaAsSb, when the Sb composition ratio is 0.30 or less, an effect of reducing the band gap by increasing the Sb composition ratio is observed.
  • InGaAsSb The above-mentioned Sb composition ratio of InGaAsSb needs to determine an effective composition ratio range in consideration of not only the band gap but also the ease of crystal growth.
  • the crystal growth of a group III-V compound semiconductor is greatly affected by the group V elements contained and their composition ratios.
  • InGaAsSb can be considered as a mixed crystal of an As-based material (InGaAs) and an Sb-based material (GaAsSb).
  • InGaAs on the InP layer can grow a crystal having good crystallinity relatively easily.
  • GaAsSb on the InP layer is more difficult to grow as compared with InGaAs.
  • One of the major factors is that Sb tends to remain on the surface during crystal growth, and the range of the raw material supply amount and growth temperature for obtaining good crystallinity is narrow (see Non-Patent Document 4).
  • the Sb composition ratio of InGaAsSb used for the channel layer 103 is desirably 0.01 or more. From the above, it is useful that the Sb composition ratio of InGaAsSb used for the channel layer 103 is 0.01 or more and 0.3 or less.
  • InGaAsSb having a lattice constant larger than that of InP laminate mismatch with InP: + 0.2%, + 0.5%, + 1.0%, + 1.5%) as well as the case of lattice matching with InP 3 also shows a change in the band gap depending on the Sb composition ratio. From this result, even in InGaAsSb having a larger lattice constant than InP, the change in the band gap due to the Sb composition ratio has the same tendency as in the case of lattice matching with InP. That is, when the Sb composition ratio is increased beyond 0.3, the band gap also increases.
  • the Sb composition ratio is desirably 0.01 or more and 0.3 or less.
  • FIG. 3 shows the calculation method described in Non-Patent Document 1 when the channel layer is made of Si, when the channel layer is made of InGaAs lattice-matched to InP, and when the channel layer is made of InGaAs lattice-matched to InP.
  • the tunnel current density is calculated for each of the cases where the configuration is made from FIG.
  • the horizontal axis in FIG. 3 is the electric field intensity at the tunnel junction interface.
  • the calculation was performed with the reverse bias voltage applied from the outside set to 0.3V.
  • InGaAsSb cases where the Sb composition was 0.1, 0.2, 0.3, and 0.4 were examined.
  • FIG. 4 is an enlarged view showing a part of each result of the case where the channel layer shown in FIG. 3 is made of InGaAs and the case where the channel layer is made of InGaAsSb.
  • a tunnel junction having a channel layer made of InGaAsSb can obtain a larger tunnel current density than InGaAs. More specifically, in InGaAsSb, the tunnel current density changes depending on the Sb composition ratio.
  • the tunnel current density increases by increasing the Sb composition ratio of InGaAsSb from 0.1 to 0.2, but hardly changes even when it is increased from 0.2 to 0.3.
  • the Sb composition ratio is further increased from 0.3 to 0.4, the tunnel current density decreases sharply and becomes smaller than when the Sb composition ratio is 0.1. From these facts, it is understood that the Sb composition ratio of InGaAsSb used for the channel layer 103 is desirably 0.3 or less in order to increase the tunnel current density.
  • This tunnel field effect transistor includes an InP layer 102 formed on a substrate 101, and a channel layer 103 formed on the InP layer 102.
  • a source region 104 and a drain region 105 are formed at predetermined intervals.
  • the source region 104 is, for example, p-type
  • the drain region 105 is, for example, n-type.
  • a source electrode 107 is formed so as to be electrically connected, and in the drain region 105, a drain electrode 108 is formed so as to be electrically connected. Further, a gate electrode 109 is formed on the channel region 106 between the source region 104 and the drain region 105 with a gate insulating layer 110 interposed therebetween.
  • the channel layer 103 has a quantum well structure in which the InGaAsSb layer is the well layer 112 and the layer made of InGaAs or InGaAsSb is the barrier layer 111. Further, this quantum well structure is formed on an underlayer 113 made of InGaAsSb. In the second embodiment, the channel layer 103 includes the underlying layer 113 and a quantum well structure including the barrier layer 111 and the well layer 112 formed thereon.
  • the well layer 112 may have a thickness of 4 nm to 20 nm, a lattice constant larger than that of InP, and a compressive strain of 3.5% or less.
  • the barrier layer 111 may be made of InGaAsSb and have a smaller lattice constant than InP and have a tensile strain.
  • the interface between the channel region 106 and the source region 104 becomes the tunnel junction region 121.
  • an electric field applied to the tunnel junction region 121 is controlled by a gate voltage, so that a current flowing to the drain region 105 is changed to realize an on / off operation.
  • an InP layer 102 having a layer thickness of 0.1 ⁇ m is grown on a substrate 101 made of semi-insulating InP, and an InP layer 102 made of InGaAsSb lattice-matched to InP with an Sb composition ratio of 0.07 is formed thereon.
  • the stratum 113 is grown.
  • a well layer 112 made of InGaAsSb having a thickness of 12 nm, a barrier layer 111 made of InGaAsSb having a composition ratio of Sb of 0.1, a tensile strain of 1.04%, and a thickness of 3 nm are grown.
  • an InP surface protection layer having a thickness of 20 nm is grown.
  • the source region 104 and the drain region 105 are formed, the gate insulating layer 110 and the gate electrode 109 are formed, and the source electrode 107 and the drain electrode 108 are formed in the same manner as in the first embodiment.
  • the source region 104 and the drain region 105 may be formed to a depth reaching the base layer 113, for example.
  • the planar-type tunneling electric field transistor using the strain-compensated quantum well structure of InGaAsSb according to the second embodiment for the channel layer 103 has a drain current of 1.0 m under the conditions of a source voltage of 60 mV and (gate voltage-threshold voltage) of 1 V. 9 ⁇ 10 ⁇ 1 ⁇ A / ⁇ m, and the minimum value of the S value is 51 mV / dec. It is.
  • the planar-type tunnel electric field transistor according to the second embodiment has a higher drain current and a lower minimum S value than the tunnel electric field transistor according to the first embodiment.
  • the strain-compensated quantum well structure of InGaAsSb for the channel layer 103, the band gap of the channel layer 103 can be reduced, and the device characteristics of the tunnel field effect transistor can be improved.
  • the strain compensation quantum well structure is used for the channel layer 103 has been described.
  • the well layer 112 made of InGaAsSb is used, the band gap of the channel layer 103 can be reduced. Therefore, even when a strained quantum well structure in which tensile strain is not applied to the barrier layer 111 or a quantum well structure in which the barrier layer 111 is made of InGaAs is used for the channel layer 103, device characteristics are improved as described above. Is clear.
  • InGaAsSb having a larger lattice constant than InP can have a smaller band gap than InGaAsSb lattice-matched to InP even with the same Sb composition ratio.
  • InGaAsSb having a lattice constant different from that of InP is crystal-grown, the generation of crystal defects due to lattice distortion becomes a problem.
  • the thickness of the well layer is too small in the InGaAsSb strained quantum well structure, the band gap increases due to the quantum size effect. In this case, the tunnel current in the tunnel field transistor decreases.
  • a description will be given of a range of the thickness of the well layer necessary for not significantly reducing the tunnel current density in the tunnel junction using the InGaAsSb strained quantum well.
  • FIG. 6 shows a tunnel current density in a tunnel junction using the strained quantum well structure when the well layer has a thickness of 2, 4, 6, 8, 10, 12 nm in the strained quantum well structure using InGaAsSb.
  • the Sb composition of the InGaAsSb well layer was 0.1
  • the lattice mismatch with InP was + 1.5%
  • the barrier layer was InGaAsSb with an Sb composition ratio of 0.1 and lattice matching with InP.
  • FIG. 6 also shows the result of the tunnel junction using InGaAs shown in FIG. 3 for comparison.
  • a larger tunnel current density can be obtained than in the case of using InGaAs.
  • the current density of the tunnel junction using the InGaAsSb strained quantum well changes depending on the thickness of the well layer. As shown in FIG. 6, the tunnel current density when the InGaAsSb strained quantum well is used increases sharply by increasing the layer thickness of the well layer from 2 nm to 4 nm. But it does not increase rapidly. This indicates that the thickness of the strained InGaAsSb quantum well layer is desirably 4 nm or more.
  • the upper limit of the thickness of the well layer may be a thickness having a quantum size effect as a quantum well, specifically, 20 nm or less.
  • FIG. 6 shows an example in which the Sb composition ratio of the well layer is 0.1 and the lattice mismatch with InP is + 1.5%, but the Sb composition ratio is other than 0.1 as described later. And the lattice mismatch with InP is other than + 1.5%, the tunnel current density is different only in absolute value, and 4 nm or more is still effective as the well layer thickness.
  • the strain quantum well structure using InGaAsSb lattice-matched to InP is described as the barrier layer, but the present invention is also effective when a barrier layer that does not lattice-match is used.
  • a quantum well using a barrier layer to which lattice strain (tensile strain) opposite to that of the well layer is applied will be described.
  • a quantum well in which a barrier layer has lattice strain opposite to that of a well layer has an effect of compensating for lattice strain in the well layer, and is therefore called a strain-compensated quantum well.
  • the well layer in the present invention (Embodiment 2) is made of InGaAsSb to which a compressive strain is applied, it is necessary to apply a tensile strain to the barrier layer in order to form a strain compensation quantum well structure.
  • InInGaAsSb tensile strain can be easily applied by increasing the Ga composition ratio.
  • InGaAsSb having a high Ga composition ratio for the barrier layer band discontinuity in the conduction band changes, and confinement of electrons in the InGaAsSb well layer increases. This increase in electron confinement is also useful for improving device characteristics as described below.
  • FIG. 7 shows the tunneling of the tunnel junction using the strain-compensated quantum well structure in the case where the thickness of the well layer is 2, 4, 6, 8, 10, and 12 nm in the strain-compensated quantum well structure using InGaAsSb.
  • the electric field strength dependence of the current density is shown.
  • the Sb composition of the InGaAsSb well layer is 0.2
  • the lattice mismatch with InP is + 144%
  • the Sb composition ratio of the barrier layer is 0.1
  • the lattice mismatch with InP is -0.87%.
  • FIG. 7 also shows the result of the tunnel junction using InGaAs for comparison, as in FIG.
  • the tendency when the strain-compensated quantum well structure is used also shows the same tendency as when the strain-quantum well structure described with reference to FIG. 6 is used.
  • the tunnel current density increases sharply by increasing the layer thickness of the well layer from 2 nm to 4 nm, but thereafter, even if the layer thickness is increased, the current density does not increase sharply. Therefore, even when the strain compensation quantum well structure is used for the channel layer, a layer thickness of 4 nm or more is effective as the well layer.
  • the result shown in FIG. 7 is an example in which tensile strain is applied to the upper and lower barrier layers above the well layer.
  • tensile strain is applied to one of the upper and lower barrier layers, the quantum size effect exists and the InGaAsSb well layer Is used to obtain a small band gap, so that the effective range of the well layer thickness described above does not change.
  • the layer thickness at which the crystal defects begin to occur is called the critical layer thickness. It is desirable that the layer thickness of the quantum well used for the tunnel electric field transistor is 4 nm or more, and in order to make the layer thickness of the well layer 4 nm or more, the compressive strain applied to the well layer needs to be a certain value or less. In other words, the lattice strain at which the critical layer thickness becomes 4 nm is the upper limit of the lattice strain that can be applied to the well layer.
  • FIG. 8 shows the results obtained by using the calculation method described in Non-Patent Document 7 for the critical layer thickness when lattice strain (compression strain) is changed for InGaAsSb having an Sb composition ratio of 0.1. I have.
  • FIG. 9 shows the result of calculating the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.2 by changing the lattice strain (compression strain) using the calculation method described in Non-Patent Document 7. Is shown.
  • the thickness of the well layer is larger than the curves shown in FIGS. 8 and 9, crystal defects are likely to occur. 8 and 9, the lattice strain at which the critical layer thickness is 4 nm is + 3.5% in both cases where the Sb composition ratio of InGaAsSb is 0.1 or 0.2. Therefore, when the InGaAsSb quantum well is used for the channel layer of the tunnel electric field transistor, the compressive strain of the well layer is desirably set to + 3.5% or less.
  • FIG. 10 is a sectional view showing a layer structure of the manufactured multiple quantum well structure.
  • a buffer layer 202 of InP having a thickness of 0.1 ⁇ m is grown on an InP substrate 201.
  • FIG. 11 shows a comparison between a measurement result (experiment) and a simulation result of the X-ray diffraction pattern of the above-described multiple quantum well structure.
  • the well layer 204 may be made of InGaAsSb with a compressive strain of 1.63% and a layer thickness of 12.9 nm
  • the barrier layer 203 may be made of InGaAsSb with a tensile strain of 1.04% and a layer thickness of 19.0 nm. Do you get it.
  • FIG. 12 shows a photoluminescence emission spectrum of the above-described multiple quantum well structure at room temperature.
  • the energy of the emission peak of photoluminescence is 0.57 eV.
  • the energy of the emission peak substantially matches the band gap of the well layer. For this reason, it was confirmed that the band gap of the strain compensation quantum well structure (multiple quantum well structure) using InGaAsSb was smaller than that of InGaAs (0.74 eV) lattice-matched to InP.
  • the channel layer is configured to include the InGaAsSb layer made of InGaAsSb formed on the InP layer made of InP, the device characteristics of the planar tunnel field effect transistor Can be improved.
  • the present invention in a planar tunnel field effect transistor, it is possible to increase the current in the ON state and to operate the transistor with a small gate voltage.
  • power consumption can be reduced, and as a result, energy saving of an electronic device can be realized.

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Abstract

This tunnel field-effect transistor is provided with: an InP layer (102) that is made of InP and formed on a substrate (101); and a channel layer (103) that is formed on the InP layer (102). The channel layer (103) is provided with an InGaAsSb layer that is made of InGaAsSb. In the InGaAsSb layer, the composition ratio of Sb in V group elements is 0.01-0.3. A source region (104) and a drain region (105) are formed at a prescribed interval in the channel layer (103). The source region (104) is set as a first conductive type (e.g., p-type), and the drain region (105) is set as a second conductive type (e.g., n-type).

Description

トンネル電界効果トランジスタTunnel field effect transistor
　本発明は、プレーナ型のトンネル電界効果トランジスタに関するものである。 << The present invention relates to a planar type tunnel field effect transistor.
　近年のＩｏＴ（Internet of Things）やクラウドコンピューティングなどの進展に伴い、ネットワーク機器、サーバー、ＰＣ、携帯端末などのＩＴ機器には、大量のデータを高速に処理できる性能が求められている。しかし、このＩＴ機器の高性能化に伴って、総電力に占めるＩＴ機器の消費電力が急激に増加することが懸念されている。低エネルギー社会を実現するためには、ＩＴ機器の消費電力を劇的に低減できるような革新的技術の開発が求められている。 With the recent development of Internet of Things (IoT) and cloud computing, IT devices such as network devices, servers, PCs, and mobile terminals are required to have a performance capable of processing a large amount of data at high speed. However, there is a concern that the power consumption of the IT device in the total power will increase sharply with the high performance of the IT device. In order to realize a low-energy society, it is required to develop innovative technologies that can dramatically reduce the power consumption of IT devices.
　ＩＴ機器の中には、多くの電子デバイスが使用されている。電子デバイスの中でも、いわゆるＭＯＳＦＥＴと呼ばれている電界効果トランジスタの使用数は非常に多い。このため、ＩＴ機器の低消費電力化を図る上では、ＭＯＳＦＥＴの消費電力を低減することが重要である。ＭＯＳＦＥＴの消費電力は、駆動電圧の２乗に比例する。このため、低い駆動電圧でＭＯＳＦＥＴを動作させることができれば、結果としてＩＴ機器の消費電力の低減に繋がる。 Many electronic devices are used in IT equipment. Among electronic devices, the number of field-effect transistors called MOSFETs is extremely large. Therefore, in order to reduce the power consumption of IT equipment, it is important to reduce the power consumption of the MOSFET. The power consumption of the MOSFET is proportional to the square of the drive voltage. Therefore, if the MOSFET can be operated at a low drive voltage, the power consumption of the IT device can be reduced as a result.
　ＭＯＳＦＥＴでは、ゲート電圧によりドレイン電流を変化させることでオン状態とオフ状態を切り替えている。ＭＯＳＦＥＴの駆動電圧を低減するには、小さなゲート電圧で急激にドレイン電流を変化させることが重要となる。これに関し、ＭＯＳＦＥＴでは、ドレイン電流を１桁増加させるために必要なゲート電圧を重要な性能指標としており、この物理量はＳ値（単位：ｍＶ／ｄｅｃａｄｅ）と呼ばれる。Ｓ値が小さいほど、駆動電圧の低減が期待でき、ＭＯＳＦＥＴの低消費電力化に繋がる。 (4) In a MOSFET, an on state and an off state are switched by changing a drain current according to a gate voltage. In order to reduce the drive voltage of the MOSFET, it is important to rapidly change the drain current with a small gate voltage. In this regard, in the MOSFET, the gate voltage required to increase the drain current by one digit is used as an important performance index, and this physical quantity is called an S value (unit: mV / decade). The lower the S value, the lower the drive voltage can be expected, which leads to lower power consumption of the MOSFET.
　ＭＯＳＦＥＴでは、デバイス構造やチャネル材料の検討等によりＳ値を低減する検討が進められている。現在、最も普及している電界効果トランジスタは、ＭＯＳＦＥＴであり、ゲート電圧によって電流通路となる伝導帯のエネルギー的な位置を上下させることでドレイン電流を変化させ、オン・オフの動作を切り替えている。このＭＯＳＦＥＴでは、原理的に０．６ｍＶ／ｄｅｃａｄｅよりも小さいＳ値を実現することが難しい。このため、ＭＯＳＦＥＴではその消費電力を劇的に低減することは困難である。 In MOSFETs, studies are underway to reduce the S value by examining the device structure and channel material. At present, the most widespread field-effect transistor is a MOSFET, and the on / off operation is switched by changing the drain current by raising and lowering the energy position of a conduction band serving as a current path by a gate voltage. . With this MOSFET, it is difficult in principle to realize an S value smaller than 0.6 mV / decade. Therefore, it is difficult to dramatically reduce the power consumption of the MOSFET.
　トンネル電界効果トランジスタ（ＴＦＥＴ）は、上述のＭＯＳＦＥＴとは異なる原理で動作するため、Ｓ値を０．６ｍＶ／ｄｅｃａｄｅよりも小さくできる。このトンネル電界効果トランジスタを用いれば、ＭＯＳＦＥＴよりも小さな駆動電圧でオン・オフ動作を実現できる。このため、近年、トンネル電界効果トランジスタの研究・開発が精力的に進められている。トンネル電界効果トランジスタでは、いくつかの素子構造が検討されている。この中でプレーナ型のトンネル電界効果トランジスタは、ＭＯＳＦＥＴと類似した素子構造を持ち、製造プロセスもＭＯＳＦＥＴの技術を応用できることが多いため、特に有望な構造である。 (4) Since the tunnel field effect transistor (TFET) operates on a principle different from that of the MOSFET described above, the S value can be made smaller than 0.6 mV / decade. By using this tunnel field effect transistor, an on / off operation can be realized with a drive voltage smaller than that of a MOSFET. Therefore, in recent years, research and development of tunnel field effect transistors have been energetically advanced. Several device structures have been studied for the tunnel field effect transistor. Among them, a planar tunnel field effect transistor is a particularly promising structure because it has an element structure similar to that of a MOSFET and a MOSFET can be applied to a manufacturing process in many cases.
　プレーナ型のトンネル電界効果トランジスタについて、図１３を参照して説明する。プレーナ型のトンネル電界効果トランジスタは、前述したようにＭＯＳＦＥＴと類似した構造を持つ。このトンネル電界効果トランジスタは、例えば、化合物半導体からなるチャネル層３０１に、ソース領域３０２と、ソース領域３０２に所定の間隔を開けて形成されたドレイン領域３０３とを備える。ソース領域３０２は、チャネル層３０１をｐ型とすることで形成され、ドレイン領域３０３は、チャネル層３０１をｎ型とすることで形成されている。 A planar tunnel field effect transistor will be described with reference to FIG. The planar type tunnel field effect transistor has a structure similar to the MOSFET as described above. The tunnel field effect transistor includes, for example, a channel region 301 made of a compound semiconductor, a source region 302, and a drain region 303 formed at a predetermined interval from the source region 302. The source region 302 is formed by making the channel layer 301 p-type, and the drain region 303 is formed by making the channel layer 301 n-type.
　また、チャネル層３０１のソース領域３０２とドレイン領域３０３とに挾まれた領域には、チャネル領域３０４が形成されている。ソース領域３０２、チャネル領域３０４、ドレイン領域３０３は、チャネル層３０１の表面に平行な平面でゲート長方向に、これらの順に配列されている。 チ ャ ネ ル A channel region 304 is formed in a region of the channel layer 301 between the source region 302 and the drain region 303. The source region 302, the channel region 304, and the drain region 303 are arranged in this order in a gate length direction on a plane parallel to the surface of the channel layer 301.
　また、ソース領域３０２に接続してソース電極３０５が形成され、ドレイン領域３０３に接続してドレイン電極３０６が形成されている。また、チャネル領域３０４の上には、ゲート絶縁層３０７を介してゲート電極３０８が形成されている。 ソ ー ス Further, a source electrode 305 is formed in connection with the source region 302, and a drain electrode 306 is formed in connection with the drain region 303. Further, a gate electrode 308 is formed over the channel region 304 with a gate insulating layer 307 interposed therebetween.
　トンネル電界効果トランジスタとＭＯＳＦＥＴとの違いは、ソース領域とドレイン領域の導電型である。ＭＯＳＦＥＴ（ｎ型ＭＯＳＦＥＴ）ではソース領域、ドレイン領域がともにｎ型にドーピングされている。これに対し、トンネル電界効果トランジスタ（ｎ型ＴＦＥＴ）ではソース領域３０２はｐ型、ドレイン領域３０３はｎ型にドーピングされている。トンネル電界効果トランジスタにはｐｎ接合が存在し、このｐｎ接合がトンネル接合となる。 The difference between the tunnel field effect transistor and the MOSFET is the conductivity type of the source region and the drain region. In a MOSFET (n-type MOSFET), the source region and the drain region are both n-type doped. On the other hand, in the tunnel field effect transistor (n-type TFET), the source region 302 is p-type and the drain region 303 is n-type. The tunnel field effect transistor has a pn junction, and this pn junction becomes a tunnel junction.
　図１３を用いて説明しているトンネル電界効果トランジスタでは、チャネル領域３０４とソース領域３０２との界面がトンネル接合領域３１１となる。トンネル電界効果トランジスタでは、トンネル接合領域３１１に加わる電界を、ゲート電圧によって制御することで、ドレイン領域３０３へと流れる電流を変化させ、オン・オフ動作をさせている。 で は In the tunnel field effect transistor described with reference to FIG. 13, the interface between the channel region 304 and the source region 302 becomes the tunnel junction region 311. In the tunnel field effect transistor, an electric field applied to the tunnel junction region 311 is controlled by a gate voltage, so that a current flowing to the drain region 303 is changed to perform an on / off operation.
　上述したトンネル電界効果トランジスタ動作について、図１４を参照して説明する。ゲート電圧を加えていないオフ状態（点線）では、ソース領域３０２とチャネル領域３０４との間には、高いエネルギー障壁が存在する。このため、ソース領域３０２からチャネル領域３０４への電子３２１の移動は困難であり、電流はほとんど流れない。一方、ゲート電圧を加えた場合（実線）、上述のエネルギー障壁は小さくなり、電子３２１はトンネル効果によって価電子帯から伝導帯への移動が可能になる。このため、ソース領域３０２とチャネル領域３０４との間のトンネル接合に電流が流れる。 {Operation of the above-described tunnel field effect transistor will be described with reference to FIG. In the off state (dotted line) where no gate voltage is applied, a high energy barrier exists between the source region 302 and the channel region 304. Therefore, it is difficult for the electrons 321 to move from the source region 302 to the channel region 304, and almost no current flows. On the other hand, when a gate voltage is applied (solid line), the above-described energy barrier becomes small, and the electrons 321 can move from the valence band to the conduction band by the tunnel effect. Therefore, a current flows through a tunnel junction between the source region 302 and the channel region 304.
　トンネル電界効果トランジスタでは、小さいゲート電圧でトンネル接合領域３１１付近のバンド配列を急激に変化させるような構造的工夫がなされており、これによって前述したようにＭＯＳＦＥＴでは困難な０．６ｍＶ／ｄｅｃａｄｅ以下のＳ値を実現している。 In the tunnel field effect transistor, structural measures are taken to rapidly change the band arrangement in the vicinity of the tunnel junction region 311 with a small gate voltage. As a result, as described above, 0.6 mV / decade or less, which is difficult for a MOSFET, is used. S value is realized.
　トンネル電界効果トランジスタにおいて、オン状態におけるドレイン電流を増加させるためには、トンネル接合領域における電子のトンネル確率を増加させる必要がある。トンネル確率は、トンネル接合領域となる材料のバンドギャップならびに電子と正孔の有効質量に大きく依存しており、基本的にはこれらの値が小さいほど、大きくすることが可能である（例えば、非特許文献１を参照）。 (4) In the tunnel field effect transistor, in order to increase the drain current in the ON state, it is necessary to increase the tunnel probability of electrons in the tunnel junction region. The tunnel probability largely depends on the band gap of the material serving as the tunnel junction region and the effective mass of electrons and holes. Basically, the smaller these values are, the larger the value can be. See Patent Document 1).
　トンネル電界効果トランジスタの重要な性能指標の１つとして、オン状態とオフ状態における電流の比がある。具体的には、オン状態における電流をオン電流、オフ状態におけるオフ電流とすると、オフ電流に対するオン電流の比（ＩON／ＩOFF）が高いほどデバイスとしての特性は良いことになる。トンネル確率を増加させるためには、上述したようにトンネル接合領域にバンドギャップが小さい材料を用いることが有効である。しかし、バンドギャップが小さい材料の場合、オフ電流も大きくなるため、必ずしもＩON／ＩOFFは増大しない。このため、トンネル電界効果トランジスタをバンドギャップが小さい材料だけを使って作製しても、高いＩON／ＩOFFを得ることは難しい。 One of the important performance indicators of a tunnel field effect transistor is the ratio of the current in the on state to that in the off state. Specifically, assuming that the current in the on state is the on current and the off current in the off state, the higher the ratio of the on current to the off current (I ON / I OFF ), the better the device characteristics. In order to increase the tunnel probability, it is effective to use a material having a small band gap in the tunnel junction region as described above. However, in the case of a material having a small band gap, the off-state current also increases, so that I ON / I OFF does not always increase. Therefore, it is difficult to obtain a high I ON / I OFF even if the tunnel field effect transistor is manufactured using only a material having a small band gap.
　オフ電流の増加を抑えつつ、オン電流を増加させるには、チャネル層のみにバンドギャップが小さい材料を用い、チャネル層以外の層にはバンドギャップの大きな材料を用いることが有効である。具体的には、基板としてバンドギャップの大きな半導体材料を用い、その上にバンドギャップが小さい半導体材料を成長させ、これをトンネル電界効果トランジスタ用の成長基板（エピウェハ）として用いることが有効である。 (4) In order to increase the on-current while suppressing the increase in the off-state current, it is effective to use a material having a small band gap only for the channel layer and use a material having a large band gap for layers other than the channel layer. Specifically, it is effective to use a semiconductor material having a large band gap as a substrate, grow a semiconductor material having a small band gap thereon, and use this as a growth substrate (epitaxial wafer) for a tunnel field effect transistor.
　ＩｎＰのバンドギャップ（～１．３５ｅＶ）は、シリコン（～１．１２ｅＶ）より大きく、基板として高品質な製品が市販されている。また、ＩｎＰを基板として、この上にシリコンよりもバンドギャップが小さいＩｎＧａＡｓなどの材料を成長することは、比較的容易である。このため、ＩｎＰ基板上に成長したＩｎＧａＡｓや、ＩｎＧａＡｓによる量子井戸をトンネル電界効果トランジスタのチャネル層に応用する検討が進められており、作製された素子において良好なデバイス特性が確認されている（非特許文献２、非特許文献３参照）。 The band gap of ギ ャ ッ プ InP (～ 1.35 eV) is larger than that of silicon (～ 1.12 eV), and high-quality products are commercially available as substrates. Further, it is relatively easy to grow a material such as InGaAs having a smaller band gap than silicon on InP using the substrate as InP. For this reason, studies are being made to apply InGaAs grown on an InP substrate or a quantum well made of InGaAs to the channel layer of a tunnel field effect transistor, and good device characteristics have been confirmed in the manufactured device (non-device). Patent Document 2, Non-Patent Document 3).
　前述したように、ＩｎＰ基板上のＩｎＧａＡｓやＩｎＧａＡｓ量子井戸構造をチャネル領域に用いたプレーナ型のトンネル電界効果トランジスタでは、優れたデバイス特性が得られている。このトンネル電界効果トランジスタにおいて、さらにオン電流を増加させ、駆動電圧を低減させるためには、ＩｎＧａＡｓよりもバンドギャップの小さな材料をチャネル層に用いることが有効である。 As described above, excellent device characteristics are obtained in a planar tunnel field effect transistor using an InGaAs or InGaAs quantum well structure on an InP substrate for a channel region. In this tunnel field effect transistor, in order to further increase the on-current and reduce the driving voltage, it is effective to use a material having a smaller band gap than InGaAs for the channel layer.
　現在、ＩｎＰに格子整合させることが可能な材料の中からバンドギャップの小さな材料を選ぶ場合、ＩｎＧａＡｓを選択することが一般的である。これは、ＩｎＧａＡｓが比較的容易に結晶品質の高い膜を結晶成長できるためである。ＩｎＧａＡｓ以外の材料の中で、ＩｎＰに格子整合させることができ、ＩｎＧａＡｓと同程度の小さいバンドギャップを持つ材料としてＧａＡｓＳｂがある。しかし、Ｓｂ組成比が大きい材料は結晶成長が難しいため（非特許文献４参照）、現状においてＧａＡｓＳｂを用いたデバイスは多くはない。 At present, when a material having a small band gap is selected from materials that can be lattice-matched to InP, InGaAs is generally selected. This is because InGaAs can relatively easily grow a crystal having a high crystal quality. Among materials other than InGaAs, GaAsSb is a material that can be lattice-matched to InP and has a band gap as small as InGaAs. However, since a crystal having a large Sb composition ratio is difficult to grow (see Non-Patent Document 4), there are not many devices using GaAsSb at present.
　ＩｎＰに格子整合しなくて良ければ、チャネル領域に用いる材料のバンドギャップはＩｎＰに格子整合するＩｎＧａＡｓよりも小さくすることができる。この方法の１つが、非特許文献３に示されているＩｎ組成比を大きなＩｎＧａＡｓの量子井戸をチャネル層に用いる方法である。ＩｎＧａＡｓ量子井戸を用いる場合、バンドギャップを小さくするには、Ｉｎ組成比を増加させるとともに、層厚を増加させる必要がある。 If it is not necessary to lattice match with InP, the band gap of the material used for the channel region can be made smaller than InGaAs lattice matching with InP. One of the methods is a method disclosed in Non-Patent Document 3 in which an InGaAs quantum well having a large In composition ratio is used for a channel layer. When using an InGaAs quantum well, it is necessary to increase the In composition ratio and increase the layer thickness in order to reduce the band gap.
　しかしながら、Ｉｎ組成比と層厚の増加に伴い、ＩｎＧａＡｓ井戸層には大きな圧縮歪が加わるため、これに起因した結晶欠陥の発生が起こり易くなる。この結晶欠陥があるために、ＩｎＧａＡｓ井戸層のＩｎ組成比と層厚を増加させることは容易ではない。このため、ＩｎＧａＡｓ量子井戸をチャネル領域に用いた場合でも、プレーナ型のトンネル電界効果トランジスタのデバイス特性を向上させることは容易ではない（非特許文献３を参照）。 However, with the increase of the In composition ratio and the layer thickness, a large compressive strain is applied to the InGaAs well layer, so that crystal defects due to this are likely to occur. Due to the crystal defects, it is not easy to increase the In composition ratio and the layer thickness of the InGaAs well layer. For this reason, it is not easy to improve the device characteristics of a planar tunnel field effect transistor even when an InGaAs quantum well is used for the channel region (see Non-Patent Document 3).
　本発明は、以上のような問題点を解消するためになされたものであり、プレーナ型のトンネル電界効果トランジスタのデバイス特性を向上させることを目的とする。 The present invention has been made to solve the above problems, and has as its object to improve the device characteristics of a planar tunnel field effect transistor.
　本発明に係るトンネル電界効果トランジスタは、ＩｎＰからなるＩｎＰ層の上に形成されたＩｎＧａＡｓＳｂからなるＩｎＧａＡｓＳｂ層を備えるチャネル層と、チャネル層に形成された第１導電型のソース領域と、ソース領域と所定の間隔を開けてチャネル層に形成された第２導電型のドレイン領域と、ソース領域に接続して形成されたソース電極と、ドレイン領域に接続して形成されたドレイン電極と、ソース領域とドレイン領域との間のチャネル領域の上に形成されたゲート電極とを備え、ＩｎＧａＡｓＳｂ層は、Ｖ族元素におけるＳｂの組成比が０．０１以上０．３以下とされている。 A tunnel field effect transistor according to the present invention includes a channel layer including an InGaAsSb layer formed of InGaAsSb formed on an InP layer formed of InP, a first conductivity type source region formed in the channel layer, and a source region. A second conductivity type drain region formed in the channel layer at a predetermined interval, a source electrode formed in connection with the source region, a drain electrode formed in connection with the drain region, and a source region. A gate electrode formed on a channel region between the drain region and the drain region, and the InGaAsSb layer has a composition ratio of Sb in the group V element of 0.01 to 0.3.
　上記トンネル電界効果トランジスタにおいて、チャネル層は、ＩｎＧａＡｓＳｂ層を井戸層とし、ＩｎＧａＡｓまたはＩｎＧａＡｓＳｂからなる層を障壁層とする量子井戸構造とされていてもよい。この場合、井戸層は、厚さが４ｎｍ以上２０ｎｍ以下とされ、ＩｎＰより格子定数が大きく、３．５％以下の圧縮歪みを有しているとよい。また、障壁層は、ＩｎＧａＡｓＳｂから構成され、ＩｎＰより格子定数が小さく、引っ張り歪みを有しているとよい。 In the above tunnel field effect transistor, the channel layer may have a quantum well structure in which an InGaAsSb layer is a well layer and a layer made of InGaAs or InGaAsSb is a barrier layer. In this case, the well layer may have a thickness of 4 nm or more and 20 nm or less, a lattice constant larger than that of InP, and a compressive strain of 3.5% or less. The barrier layer is preferably made of InGaAsSb, has a smaller lattice constant than InP, and has a tensile strain.
　以上説明したように、本発明によれば、チャネル層を、ＩｎＰからなるＩｎＰ層の上に形成されたＩｎＧａＡｓＳｂからなるＩｎＧａＡｓＳｂ層を備える構成としたので、プレーナ型のトンネル電界効果トランジスタのデバイス特性を向上させることができるという優れた効果が得られる。 As described above, according to the present invention, since the channel layer has the InGaAsSb layer made of InGaAsSb formed on the InP layer made of InP, the device characteristics of the planar tunnel field effect transistor can be improved. An excellent effect of being able to improve is obtained.
図１は、本発明の実施の形態１におけるトンネル電界効果トランジスタの構成を示す断面図である。FIG. 1 is a sectional view showing a configuration of the tunnel field effect transistor according to the first embodiment of the present invention. 図２は、ＩｎＧａＡｓＳｂのＳｂ組成比によるバンドギャップの変化を計算により求めた結果を示す特性図である。FIG. 2 is a characteristic diagram showing a result obtained by calculating a change in band gap according to the Sb composition ratio of InGaAsSb. 図３は、チャネル層をＳｉから構成する場合、チャネル層をＩｎＰに格子整合するＩｎＧａＡｓから構成する場合、およびチャネル層をＩｎＰに格子整合するＩｎＧａＡｓＳｂから構成する場合の各々について、トンネル電流密度を計算し、比較した結果を示す特性図である。FIG. 3 shows the calculation of the tunnel current density for each of the case where the channel layer is composed of Si, the case where the channel layer is composed of InGaAs lattice-matched to InP, and the case where the channel layer is composed of InGaAsSb lattice-matched to InP. FIG. 9 is a characteristic diagram showing the result of comparison. 図４は、図３に示したチャネル層をＩｎＧａＡｓから構成した場合と、チャネル層をＩｎＧａＡｓＳｂから構成した場合との各々の結果の一部を拡大して示した特性図である。FIG. 4 is a characteristic diagram in which a part of each result of the case where the channel layer shown in FIG. 3 is made of InGaAs and the case where the channel layer is made of InGaAsSb are enlarged. 図５は、本発明の実施の形態２におけるトンネル電界効果トランジスタの構成を示す断面図である。FIG. 5 is a sectional view showing a configuration of the tunnel field effect transistor according to the second embodiment of the present invention. 図６は、ＩｎＧａＡｓＳｂを用いた歪量子井戸構造において、井戸層の層厚を２，４，６，８，１０，１２ｎｍとした場合について、この歪量子井戸構造を用いたトンネル接合におけるトンネル電流密度の電界強度依存性を示す特性図である。FIG. 6 shows a tunnel current density in a tunnel junction using the strained quantum well structure when the well layer has a thickness of 2, 4, 6, 8, 10, 12 nm in the strained quantum well structure using InGaAsSb. FIG. 6 is a characteristic diagram showing the electric field intensity dependence of FIG. 図７は、ＩｎＧａＡｓＳｂを用いた歪補償量子井戸構造において、井戸層の層厚を２，４，６，８，１０，１２ｎｍとした場合について、この歪補償量子井戸構造を用いたトンネル接合のトンネル電流密度の電界強度依存性を示す特性図である。FIG. 7 shows the tunneling of the tunnel junction using the strain-compensated quantum well structure in the case where the thickness of the well layer is 2, 4, 6, 8, 10, and 12 nm in the strain-compensated quantum well structure using InGaAsSb. FIG. 3 is a characteristic diagram showing electric field intensity dependence of current density. 図８は、Ｓｂ組成比が０．１のＩｎＧａＡｓＳｂについて、格子歪（圧縮歪）を変化させた場合の臨界層厚を、非特許文献７に記載の計算方法を用いて求めた結果を示す特性図である。FIG. 8 is a characteristic chart showing the results obtained by using the calculation method described in Non-Patent Document 7 to determine the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.1 when the lattice strain (compression strain) is changed. FIG. 図９は、Ｓｂ組成比が０．２のＩｎＧａＡｓＳｂについて、格子歪（圧縮歪）を変化させた場合の臨界層厚を、非特許文献７に記載の計算方法を用いて求めた結果を示す特性図である。FIG. 9 is a graph showing the results obtained by using the calculation method described in Non-Patent Document 7 to determine the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.2 when the lattice strain (compression strain) is changed. FIG. 図１０は、実際に作製した多重量子井戸構造の層構造を示した断面図である。FIG. 10 is a sectional view showing a layer structure of a multiple quantum well structure actually manufactured. 図１１は、作製した多重量子井戸構造のＸ線回折パターンの測定結果（実験）とシミュレーション結果とを比較して示す特性図である。FIG. 11 is a characteristic diagram showing a comparison between a measurement result (experiment) of an X-ray diffraction pattern of the manufactured multiple quantum well structure and a simulation result. 図１２は、作製した多重量子井戸構造の室温におけるフォトルミネッセンス発光スペクトルを示す特性図である。FIG. 12 is a characteristic diagram showing a photoluminescence emission spectrum at room temperature of the manufactured multiple quantum well structure. 図１３は、トンネル電界効果トランジスタの構成を示す断面図である。FIG. 13 is a cross-sectional view showing a configuration of the tunnel field effect transistor. 図１４は、トンネル電界効果トランジスタのオン状態（実線）ならびにオフ状態（点線）におけるトンネル接合領域付近のバンドギャップの変化を示すバンド図である。FIG. 14 is a band diagram showing a change in band gap near the tunnel junction region in the ON state (solid line) and the OFF state (dotted line) of the tunnel field effect transistor.
　以下、本発明の実施の形態おけるトンネル電界効果トランジスタについて説明する。 Hereinafter, the tunnel field effect transistor according to the embodiment of the present invention will be described.
［実施の形態１］
　はじめに、本発明の実施の形態１におけるトンネル電界効果トランジスタについて図１を参照して説明する。 [Embodiment 1]
First, the tunnel field effect transistor according to the first embodiment of the present invention will be described with reference to FIG.
　このトンネル電界効果トランジスタは、基板１０１の上に形成されたＩｎＰからなるＩｎＰ層１０２と、ＩｎＰ層１０２の上に形成されたチャネル層１０３とを備える。チャネル層１０３は、ＩｎＧａＡｓＳｂからなるＩｎＧａＡｓＳｂ層を備える。実施の形態１においては、チャネル層１０３がＩｎＧａＡｓＳｂ層である。ここで、ＩｎＧａＡｓＳｂ層は、Ｖ族元素におけるＳｂの組成比が０．０１以上０．３以下とされている。 This tunnel field effect transistor includes an InP layer 102 made of InP formed on a substrate 101, and a channel layer 103 formed on the InP layer 102. The channel layer 103 includes an InGaAsSb layer made of InGaAsSb. In the first embodiment, the channel layer 103 is an InGaAsSb layer. Here, the InGaAsSb layer has a composition ratio of Sb in the group V element of 0.01 to 0.3.
　また、チャネル層１０３には、所定の間隔を開けてソース領域１０４およびドレイン領域１０５が形成されている。ソース領域１０４は、第１導電型（例えばｐ型）とされ、ドレイン領域１０５は、第２導電型（例えばｎ型）とされている。また、ソース領域１０４には、ソース電極１０７が電気的に接続して形成され、ドレイン領域１０５には、ドレイン電極１０８が電気的に接続して形成されている。なお、第１導電型をｎ型とし、第２導電型をｐ型としてもよい。 {Circle around (4)} In the channel layer 103, a source region 104 and a drain region 105 are formed at predetermined intervals. The source region 104 has a first conductivity type (for example, p-type), and the drain region 105 has a second conductivity type (for example, n-type). Further, a source electrode 107 is formed so as to be electrically connected to the source region 104, and a drain electrode 108 is formed so as to be electrically connected to the drain region 105. Note that the first conductivity type may be n-type and the second conductivity type may be p-type.
　また、ソース領域１０４とドレイン領域１０５との間のチャネル領域１０６の上には、ゲート電極１０９が形成されている。実施の形態１では、ゲート絶縁層１１０を介し、チャネル層１０３のチャネル領域１０６上にゲート電極１０９が形成されている。チャネル層１０３にショットキー接続するゲート電極１０９としてもよい。ソース領域１０４、チャネル領域１０６、ドレイン領域１０５は、チャネル層１０３の表面に平行な平面において、ゲート長方向にこれらの順に配列されている。 ゲ ー ト A gate electrode 109 is formed on the channel region 106 between the source region 104 and the drain region 105. In Embodiment 1, the gate electrode 109 is formed over the channel region 106 of the channel layer 103 with the gate insulating layer 110 interposed. The gate electrode 109 may be a Schottky connection with the channel layer 103. The source region 104, the channel region 106, and the drain region 105 are arranged in the gate length direction on the plane parallel to the surface of the channel layer 103 in this order.
　このトンネル電界効果トランジスタは、チャネル領域１０６とソース領域１０４との界面がトンネル接合領域１２１となる。このトンネル電界効果トランジスタは、トンネル接合領域１２１に加わる電界を、ゲート電圧によって制御することで、ドレイン領域１０５へと流れる電流を変化させ、オン・オフ動作を実現している。 は In this tunnel field effect transistor, the interface between the channel region 106 and the source region 104 becomes the tunnel junction region 121. In this tunnel field effect transistor, an electric field applied to the tunnel junction region 121 is controlled by a gate voltage, so that a current flowing to the drain region 105 is changed to realize an on / off operation.
　以下、実施の形態１におけるトンネル電界効果トランジスタの製造方法について説明する。まず、半絶縁性ＩｎＰからなる基板１０１の上に、層厚０．１μｍのＩｎＰ層１０２と層厚０．１μｍのＩｎＧａＡｓＳｂ層（チャネル層１０３）をエピタキシャル成長する。また、ＩｎＧａＡｓＳｂ層の上に層厚２０ｎｍのＩｎＰ表面保護層を成長する。なお、ＩｎＰ表面保護層は、素子段階ではエッチングによりすべて除去するため、図１には示していない。 Hereinafter, a method for manufacturing the tunnel field effect transistor according to the first embodiment will be described. First, an InP layer 102 having a thickness of 0.1 μm and an InGaAsSb layer (channel layer 103) having a thickness of 0.1 μm are epitaxially grown on a substrate 101 made of semi-insulating InP. In addition, an InP surface protection layer having a thickness of 20 nm is grown on the InGaAsSb layer. Note that the InP surface protective layer is not shown in FIG. 1 since it is completely removed by etching at the element stage.
　各層のエピタキシャル成長には、ＩＩＩ族原料ガスにトリメチルインジウム（ＴＭＩｎ）、トリエチルガリウム（ＴＥＧａ）、Ｖ族原料ガスにホスフィン（ＰＨ3）、アルシン（ＡｓＨ3）、トリスジメチルアミノアンチモン（ＴＤＭＡＳｂ）を用いた有機金属分子線エピタキシー（ＭＯＭＢＥ）法を用いる。チャネル層１０３は、Ｓｂ組成比を０．１５とし、ＩｎＰにほぼ格子整合させるようにＩＩＩ族組成を調整する。比較のために、図１のチャネル層１０３のみをＩｎＰにほぼ格子整合するＩｎＧａＡｓに代えたエピウェハを用意する。バンドギャップは、ＩｎＧａＡｓＳｂで０．６９ｅＶ、ＩｎＧａＡｓで０．７４ｅＶである。 For the epitaxial growth of each layer, trimethylindium (TMIn) and triethylgallium (TEGa) were used as group III source gases, and phosphine (PH 3 ), arsine (AsH 3 ), and trisdimethylaminoantimony (TDMASb) were used as group V source gases. An organometallic molecular beam epitaxy (MOMBE) method is used. The Sb composition ratio of the channel layer 103 is set to 0.15, and the group III composition is adjusted so as to substantially match lattice with InP. For comparison, an epiwafer is prepared in which only the channel layer 103 shown in FIG. 1 is replaced with InGaAs which is substantially lattice-matched to InP. The band gap is 0.69 eV for InGaAsSb and 0.74 eV for InGaAs.
　次に、上述したように形成したチャネル層１０３に、ドレインとなる領域のみにＳｉをイオン注入した後、必要な熱処理を施してＳｉを活性化させ、ドレイン領域１０５とする。次に、原子層堆積（ＡＬＤ）法を用いてウェハ全体にＡｌ2Ｏ3を堆積させた後、ソースとなる領域のＡｌ2Ｏ3を除去する。基板表面を洗浄後、このウェハを有機金属気相エピタキシー（ＭＯＶＰＥ）装置内において、ホスフィンとジエチルジンク（ＤＥＺｎ）を供給しながら昇温させることにより、ＩｎＧａＡｓＳｂの一部をｐ型にし、ソース領域１０４とする。 Next, in the channel layer 103 formed as described above, Si is ion-implanted only into a region to be a drain, and a necessary heat treatment is performed to activate the Si, thereby forming a drain region 105. Next, after depositing the Al 2 O 3 in the entire wafer using atomic layer deposition (ALD) method, to remove the Al 2 O 3 in the region to be the source. After cleaning the surface of the substrate, the wafer is heated in a metal organic vapor phase epitaxy (MOVPE) apparatus while supplying phosphine and diethyl zinc (DEZn), so that part of the InGaAsSb is made p-type and the source region 104 is formed. And
　次に、素子分離のために、素子を作製する領域以外のエピタキシャル成長層を除去した後に、すべてのＩｎＰ表面保護層を除去する。ゲートとなる領域に原子層堆積法を用いた絶縁材料の堆積によりゲート絶縁層１１０を形成した後、電子ビーム蒸着装置によりゲート電極１０９となる金属を蒸着させる。リフトオフプロセスを用いて、ゲート電極１０９以外に蒸着した金属を除去する。図１において、ゲート電極１０９の水平方向（ゲート長方向）の長さは１μｍである。ソース電極、ドレイン電極となる領域の上に堆積した絶縁膜を除去した後、リフトオフプロセスを用いてソース電極１０７とドレイン電極１０８を形成する。この後、電極形成に必要な熱処理を施す。 (4) Next, for device isolation, after removing the epitaxial growth layer other than the region where the device is to be manufactured, all InP surface protection layers are removed. After a gate insulating layer 110 is formed in a region to be a gate by depositing an insulating material by an atomic layer deposition method, a metal to be a gate electrode 109 is deposited by an electron beam deposition apparatus. By using a lift-off process, metal deposited on portions other than the gate electrode 109 is removed. In FIG. 1, the length of the gate electrode 109 in the horizontal direction (gate length direction) is 1 μm. After removing the insulating film deposited over the regions to be the source electrode and the drain electrode, the source electrode 107 and the drain electrode 108 are formed by a lift-off process. Thereafter, a heat treatment necessary for electrode formation is performed.
　図１に示した実施の形態１におけるＩｎＧａＡｓＳｂをチャネル層１０３に用いたプレーナ型トンネル電界トランジスタは、ソース電圧が６０ｍＶ、（ゲート電圧－しきい値電圧）が１Ｖの条件において、ドレイン電流が１．７×１０-1μＡ／μｍであり、Ｓ値の最小値が５５ｍＶ／ｄｅｃ．である。一方、比較用のＩｎＧａＡｓをチャネル層に用いたトンネル電界トランジスタに関して、同じ電圧条件を用いた場合のドレイン電流は１．３×１０-1μＡ／μｍであり、Ｓ値の最小値は６３ｍＶ／ｄｅｃ．である。これらの結果より、プレーナ型のトンネル電界トランジスタにおいて、チャネル層をＩｎＧａＡｓからＩｎＧａＡｓＳｂにすることでドレイン電流を増大させ、Ｓ値を低減することができることが分かる。 The planar-type tunneling electric field transistor using InGaAsSb for the channel layer 103 in the first embodiment shown in FIG. 1 has a drain current of 1.0 m under the condition that the source voltage is 60 mV and (gate voltage−threshold voltage) is 1 V. 7 × 10 −1 μA / μm, and the minimum value of the S value is 55 mV / dec. It is. On the other hand, the drain current of the tunnel electric field transistor using InGaAs for comparison as the channel layer under the same voltage condition is 1.3 × 10 −1 μA / μm, and the minimum value of the S value is 63 mV / dec. . It is. From these results, it can be seen that in the planar tunneling electric field transistor, by changing the channel layer from InGaAs to InGaAsSb, the drain current can be increased and the S value can be reduced.
　上述では、結晶成長方法として有機金属分子線エピタキシー法を用いた場合について説明したが、ＩｎＰ上のＩｎＧａＡｓＳｂは、有機金属気相エピタキシー法や分子線エピタキシー法などの他の成長方法を用いても結晶成長させることができる。このため、実施の形態１におけるＩｎＧａＡｓＳｂをチャネル層１０３とするトンネル電界トランジスタは、ＩｎＧａＡｓＳｂを成長できる結晶成長方法であれば、どの結晶成長方法を用いても作製できることは明らかである。 In the above description, the case where the metalorganic molecular beam epitaxy method is used as the crystal growth method has been described. However, InGaAsSb on InP can be crystallized by using another growth method such as the metalorganic vapor phase epitaxy method or the molecular beam epitaxy method. Can grow. Therefore, it is apparent that the tunnel electric field transistor using InGaAsSb as the channel layer 103 in Embodiment 1 can be manufactured by any crystal growth method that can grow InGaAsSb.
　上述では、ＩｎＧａＡｓＳｂ層によるチャネル層１０３がＩｎＰに格子整合する場合について示したが、ＩｎＧａＡｓＳｂがＩｎＰに格子整合しない場合でも、バンドギャップをＩｎＧａＡｓより小さくできる。また、上述では、ＩｎＧａＡｓＳｂのＳｂ組成比が０．１５の場合について示したが、Ｓｂ組成比が０．０１以上０．３以下であれば、ＩｎＧａＡｓＳｂは比較的容易に結晶成長できる。このため、ＩｎＰに格子整合しないＩｎＧａＡｓＳｂを用い、また、０．１５以外のＳｂ組成比のＩｎＧａＡｓＳｂをチャネル層に用いた場合でも、本発明は有効であることは言うまでも無い。 In the above description, the case where the channel layer 103 of the InGaAsSb layer is lattice-matched to InP has been described. However, even when InGaAsSb does not lattice-match to InP, the band gap can be made smaller than that of InGaAs. Although the case where the Sb composition ratio of InGaAsSb is 0.15 is described above, if the Sb composition ratio is 0.01 or more and 0.3 or less, InGaAsSb can be relatively easily crystal-grown. Therefore, needless to say, the present invention is effective even when InGaAsSb that does not lattice-match with InP is used, and when InGaAsSb having an Sb composition ratio other than 0.15 is used for the channel layer.
　上述では、ソース領域１０４、ドレイン領域１０５をドーピングにより形成する際に、各々Ｚｎ拡散とＳｉのイオン注入を用いた。ドーピングの方法には、上記以外にも様々な方法が知られている。このため、ドーピングの方法は上記の方法に限られるものではない。 In the above description, when the source region 104 and the drain region 105 are formed by doping, Zn diffusion and ion implantation of Si are used, respectively. Various doping methods other than the above are known. For this reason, the doping method is not limited to the above method.
　次に、実施の形態１におけるトンネル電界効果トランジスタにおけるチャネル層１０３のＳｂ組成について説明する。前述のように、プレーナ型のトンネル電界効果トランジスタのデバイス特性を向上させるには、バンドギャップの大きな層や基板の上にバンドギャップが小さい材料をチャネル層として積層させた構造が有用である。従来、この構造としてＩｎＰ層（ＩｎＰ基板）の上にＩｎＧａＡｓを成長した構造が用いられてきた。 Next, the Sb composition of the channel layer 103 in the tunnel field effect transistor according to the first embodiment will be described. As described above, a structure in which a material having a small bandgap is stacked as a channel layer on a layer having a large bandgap or a substrate is useful for improving device characteristics of a planar tunnel field effect transistor. Conventionally, as this structure, a structure in which InGaAs is grown on an InP layer (InP substrate) has been used.
　ＩｎＰ層の上にＩｎＧａＡｓよりもバンドギャップが小さい材料を、結晶性を劣化させることなく成長できれば、ＩｎＧａＡｓをチャネル層に用いた場合よりも良好なデバイス特性が得られると考えられる。このバンドギャップが小さい材料としては、ＩｎＧａＡｓＳｂが有用である。これは、ＩｎＧａＡｓＳｂではＩｎＧａＡｓと格子定数が同じ場合でも、バンドギャップを小さくできるためである。これに加えて、ＩｎＧａＡｓＳｂでは、Ｓｂ組成比が少なければ良質な結晶性を得ることも容易である。 If a material having a band gap smaller than that of InGaAs can be grown on the InP layer without deteriorating the crystallinity, it is considered that better device characteristics can be obtained than when InGaAs is used for the channel layer. As a material having a small band gap, InGaAsSb is useful. This is because the band gap of InGaAsSb can be reduced even when the lattice constant is the same as that of InGaAs. In addition, in InGaAsSb, it is easy to obtain good crystallinity if the Sb composition ratio is small.
　以下、ＩｎＧａＡｓＳｂをトンネル電界効果トランジスタのチャネル層に応用する際の条件について述べる。 Hereinafter, conditions for applying InGaAsSb to the channel layer of the tunnel field effect transistor will be described.
　Ｖ族元素としてＳｂを多く含むＩＩＩ－Ｖ族半導体材料は、結晶成長が難しいことが知られている（非特許文献４参照）。ＩｎＧａＡｓＳｂもＶ族元素としてＳｂを含むが、Ｓｂ組成比が少ない場合は良質な結晶性の膜を成長することができる（非特許文献５参照）。さらに、ＩｎＧａＡｓＳｂでは、以下に示すようにＳｂ組成比が少なくてもＩｎＧａＡｓよりバンドギャップを小さくすることができる利点を有する。 It is known that a group III-V semiconductor material containing a large amount of Sb as a group V element has difficulty in crystal growth (see Non-Patent Document 4). InGaAsSb also contains Sb as a group V element, but when the Sb composition ratio is small, a high-quality crystalline film can be grown (see Non-Patent Document 5). Further, InGaAsSb has an advantage that the band gap can be made smaller than that of InGaAs even if the Sb composition ratio is small, as described below.
　図２は、ＩｎＧａＡｓＳｂのＳｂ組成比によるバンドギャップの変化を計算により求めた結果を示している。図２において、ＩｎＰに対する格子不整合が０％となる場合が、ＩｎＰに格子整合する場合のＩｎＧａＡｓＳｂのバンドギャップである。ＩｎＰに格子整合するＩｎＧａＡｓＳｂのバンドギャップは、Ｓｂ組成比を増加させていった場合、Ｓｂ組成比が０から０．２５までは減少、０．２５から０．３０まではほぼ一定、０．３０より大きくなると増加する。すなわち、ＩｎＧａＡｓＳｂではそのＳｂ組成比が０．３０以下の場合に、Ｓｂ組成比の増加によるバンドギャップの低減効果が見られる。 FIG. 2 shows a result obtained by calculating a change in band gap depending on the Sb composition ratio of InGaAsSb. In FIG. 2, the case where the lattice mismatch with InP is 0% is the band gap of InGaAsSb in the case of lattice matching with InP. The bandgap of InGaAsSb lattice-matched to InP is such that when the Sb composition ratio is increased, the Sb composition ratio decreases from 0 to 0.25, is almost constant from 0.25 to 0.30, and is 0.30. It increases when it gets bigger. That is, in the case of InGaAsSb, when the Sb composition ratio is 0.30 or less, an effect of reducing the band gap by increasing the Sb composition ratio is observed.
　上述したＩｎＧａＡｓＳｂのＳｂ組成比は、バンドギャップだけではなく、結晶成長の容易さを考慮して有効な組成比の範囲を決める必要がある。ＩＩＩ－Ｖ族化合物半導体の結晶成長は、含まれるＶ族元素とその組成比に大きく影響される。ＩｎＧａＡｓＳｂに関しては、Ａｓ系材料（ＩｎＧａＡｓ）とＳｂ系材料（ＧａＡｓＳｂ）の混晶と考えることができる。ＩｎＰ層の上のＩｎＧａＡｓは、良質な結晶性を持つ結晶を比較的容易に成長することができる。 Ｓ The above-mentioned Sb composition ratio of InGaAsSb needs to determine an effective composition ratio range in consideration of not only the band gap but also the ease of crystal growth. The crystal growth of a group III-V compound semiconductor is greatly affected by the group V elements contained and their composition ratios. InGaAsSb can be considered as a mixed crystal of an As-based material (InGaAs) and an Sb-based material (GaAsSb). InGaAs on the InP layer can grow a crystal having good crystallinity relatively easily.
　一方、ＩｎＰ層の上のＧａＡｓＳｂは、ＩｎＧａＡｓに比べて結晶成長が困難である。この大きな要因の１つは、Ｓｂは結晶成長時に表面に残留する傾向があり、良好な結晶性を得るための原料供給量や成長温度の範囲が狭いことによる（非特許文献４参照）。 On the other hand, GaAsSb on the InP layer is more difficult to grow as compared with InGaAs. One of the major factors is that Sb tends to remain on the surface during crystal growth, and the range of the raw material supply amount and growth temperature for obtaining good crystallinity is narrow (see Non-Patent Document 4).
　ＩｎＧａＡｓＳｂは、Ｓｂ組成比が少ない場合はＩｎＧａＡｓに近い成長条件となり、Ｓｂ組成比が多い場合はＧａＡｓＳｂに近い成長条件となる。このために、ＩｎＧａＡｓＳｂで良質な結晶性を得ようとした場合、Ｓｂ組成比は少ない方が望ましい。ＩｎＧａＡｓＳｂにおいて、Ｓｂ組成比を０．３より増加させた場合、図２に示すようにバンドギャップは増大し、さらに結晶成長も難しくなる。このため、トンネル電界効果トランジスタのチャネル層に用いるＩｎＧａＡｓＳｂのＳｂ組成比は、０．３以下であることが望ましい。 InGaAsSb has a growth condition close to InGaAs when the Sb composition ratio is small, and a growth condition close to GaAsSb when the Sb composition ratio is large. For this reason, when trying to obtain good crystallinity with InGaAsSb, it is desirable that the Sb composition ratio is small. In InGaAsSb, when the Sb composition ratio is increased beyond 0.3, the band gap increases as shown in FIG. 2, and the crystal growth becomes difficult. Therefore, the Sb composition ratio of InGaAsSb used for the channel layer of the tunnel field effect transistor is desirably 0.3 or less.
　次に、ＩｎＧａＡｓＳｂのＳｂ組成の下限について説明する。ＩｎＧａＡｓＳｂにおいて、Ｓｂ組成比を正確に制御するためには、層中にＳｂがドーパントレベル（＜１０21ｃｍ-3）ではなく、組成レベル（一般的な組成比の最小単位は０．０１）で層中に含まれている必要がある。このため、チャネル層１０３（ＩｎＧａＡｓＳｂ層）に用いるＩｎＧａＡｓＳｂのＳｂ組成比は、０．０１以上であることが望ましい。以上のことから、チャネル層１０３に用いるＩｎＧａＡｓＳｂのＳｂ組成比としては、０．０１以上、０．３以下が有用である。 Next, the lower limit of the Sb composition of InGaAsSb will be described. In InGaAsSb, in order to accurately control the Sb composition ratio, Sb is not contained in the layer at the composition level (the minimum unit of the general composition ratio is 0.01) instead of the dopant level (<10 21 cm −3 ). Must be included in the layer. Therefore, the Sb composition ratio of InGaAsSb used for the channel layer 103 (InGaAsSb layer) is desirably 0.01 or more. From the above, it is useful that the Sb composition ratio of InGaAsSb used for the channel layer 103 is 0.01 or more and 0.3 or less.
　図２では、ＩｎＰに格子整合する場合だけでなく、ＩｎＰよりも大きな格子定数を持つＩｎＧａＡｓＳｂ（ＩｎＰに対する格子不整合：＋０．２％、＋０．５％、＋１．０％、＋１．５％）についても、バンドギャップのＳｂ組成比による変化を示してある。この結果より、ＩｎＰよりも大きな格子定数を持つＩｎＧａＡｓＳｂでも、バンドギャップのＳｂ組成比による変化は、ＩｎＰに格子整合する場合と同様な傾向を持つ。すなわち、Ｓｂ組成比を０．３より増加させると、バンドギャップも増加する。このため、ＩｎＧａＡｓＳｂがＩｎＰに格子整合しない場合においても、ＩｎＧａＡｓＳｂをトンネル電界効果トランジスタのチャネル層に応用する場合、Ｓｂ組成比を０．０１以上、０．３以下にすることが望ましい。 In FIG. 2, InGaAsSb having a lattice constant larger than that of InP (lattice mismatch with InP: + 0.2%, + 0.5%, + 1.0%, + 1.5%) as well as the case of lattice matching with InP 3 also shows a change in the band gap depending on the Sb composition ratio. From this result, even in InGaAsSb having a larger lattice constant than InP, the change in the band gap due to the Sb composition ratio has the same tendency as in the case of lattice matching with InP. That is, when the Sb composition ratio is increased beyond 0.3, the band gap also increases. Therefore, even when InGaAsSb is not lattice-matched to InP, when InGaAsSb is applied to the channel layer of the tunnel field effect transistor, the Sb composition ratio is desirably 0.01 or more and 0.3 or less.
　トンネル電界効果トランジスタにおいて、オン電流を増加させるためにはチャネル領域１０６のトンネル電流密度を増加させる必要がある。トンネル電流の密度は、チャネル層１０３のバンドギャップと有効質量が分かれば、トンネル接合における電界強度の関数として見積もることが可能である（非特許文献１参照）。 In the tunnel field effect transistor, it is necessary to increase the tunnel current density in the channel region 106 in order to increase the on-current. If the band gap and the effective mass of the channel layer 103 are known, the density of the tunnel current can be estimated as a function of the electric field strength at the tunnel junction (see Non-Patent Document 1).
　図３は、非特許文献１に記載の算出方法を用いて、チャネル層をＳｉから構成する場合、チャネル層をＩｎＰに格子整合するＩｎＧａＡｓから構成する場合、およびチャネル層をＩｎＰに格子整合するＩｎＧａＡｓＳｂから構成する場合の各々について、トンネル電流密度を計算し、比較した結果を示している。図３の横軸は、トンネル接合界面における電界強度である。また、図３では、外部から加える逆バイアスの電圧値を０．３Ｖとして計算した。ＩｎＧａＡｓＳｂに関しては、Ｓｂ組成が０．１、０．２、０．３、０．４の場合について調べた。 FIG. 3 shows the calculation method described in Non-Patent Document 1 when the channel layer is made of Si, when the channel layer is made of InGaAs lattice-matched to InP, and when the channel layer is made of InGaAs lattice-matched to InP. , The tunnel current density is calculated for each of the cases where the configuration is made from FIG. The horizontal axis in FIG. 3 is the electric field intensity at the tunnel junction interface. In FIG. 3, the calculation was performed with the reverse bias voltage applied from the outside set to 0.3V. Regarding InGaAsSb, cases where the Sb composition was 0.1, 0.2, 0.3, and 0.4 were examined.
　図３に示されているように、ＩｎＰに格子整合するＩｎＧａＡｓやＩｎＧａＡｓＳｂをチャネル層に用いることで、Ｓｉを用いた場合より大きなトンネル電流密度が得られることが分かる。これは、主としてＩｎＧａＡｓやＩｎＧａＡｓＳｂのバンドギャップがＳｉ（バンドギャップ～１．１２ｅＶ）よりも小さいことによる。
　次に、チャネル層を、ＩｎＧａＡｓ、ＩｎＧａＡｓＳｂから構成した場合の比較について述べる。 As shown in FIG. 3, it can be seen that a higher tunnel current density can be obtained by using InGaAs or InGaAsSb lattice-matched to InP for the channel layer than using Si. This is mainly because the band gap of InGaAs or InGaAsSb is smaller than Si (band gapＳｉ1.12 eV).
Next, a comparison in the case where the channel layer is made of InGaAs and InGaAsSb will be described.
　図４は、図３に示したチャネル層をＩｎＧａＡｓから構成した場合と、チャネル層をＩｎＧａＡｓＳｂから構成した場合との各々の結果の一部を拡大して示している。図４に示されているように、チャネル層をＩｎＧａＡｓＳｂから構成した場合のトンネル接合では、ＩｎＧａＡｓに比べて大きなトンネル電流密度を得られることが分かる。詳しく見ると、ＩｎＧａＡｓＳｂではＳｂ組成比によりトンネル電流密度が変化している。 FIG. 4 is an enlarged view showing a part of each result of the case where the channel layer shown in FIG. 3 is made of InGaAs and the case where the channel layer is made of InGaAsSb. As shown in FIG. 4, it can be seen that a tunnel junction having a channel layer made of InGaAsSb can obtain a larger tunnel current density than InGaAs. More specifically, in InGaAsSb, the tunnel current density changes depending on the Sb composition ratio.
　トンネル電流密度は、ＩｎＧａＡｓＳｂのＳｂ組成比を０．１から０．２に増やすことで増加するが、０．２から０．３に増やしてもほとんど変化しない。さらにＳｂ組成比を０．３から０．４に増やすと、トンネル電流密度は急激に減少してＳｂ組成比が０．１の場合よりも小さくなる。これらのことから、チャネル層１０３に用いるＩｎＧａＡｓＳｂのＳｂ組成比は、トンネル電流密度を増加させる上でも０．３以下であることが望ましいことが分かる。 (4) The tunnel current density increases by increasing the Sb composition ratio of InGaAsSb from 0.1 to 0.2, but hardly changes even when it is increased from 0.2 to 0.3. When the Sb composition ratio is further increased from 0.3 to 0.4, the tunnel current density decreases sharply and becomes smaller than when the Sb composition ratio is 0.1. From these facts, it is understood that the Sb composition ratio of InGaAsSb used for the channel layer 103 is desirably 0.3 or less in order to increase the tunnel current density.
［実施の形態２］
　次に、本発明の実施の形態２について、図５を参照して説明する。このトンネル電界効果トランジスタは、基板１０１の上に形成されたＩｎＰ層１０２と、ＩｎＰ層１０２の上に形成されたチャネル層１０３とを備える。また、チャネル層１０３には、所定の間隔を開けてソース領域１０４およびドレイン領域１０５が形成されている。ソース領域１０４は、例えばｐ型とされ、ドレイン領域１０５は、例えばｎ型とされている。 [Embodiment 2]
Next, a second embodiment of the present invention will be described with reference to FIG. This tunnel field effect transistor includes an InP layer 102 formed on a substrate 101, and a channel layer 103 formed on the InP layer 102. In the channel layer 103, a source region 104 and a drain region 105 are formed at predetermined intervals. The source region 104 is, for example, p-type, and the drain region 105 is, for example, n-type.
　また、ソース領域１０４には、ソース電極１０７が電気的に接続して形成され、ドレイン領域１０５には、ドレイン電極１０８が電気的に接続して形成されている。また、ソース領域１０４とドレイン領域１０５との間のチャネル領域１０６の上には、ゲート絶縁層１１０を介してゲート電極１０９が形成されている。これらの構成は、前述した実施の形態１と同様である。 {Circle around (2)} In the source region 104, a source electrode 107 is formed so as to be electrically connected, and in the drain region 105, a drain electrode 108 is formed so as to be electrically connected. Further, a gate electrode 109 is formed on the channel region 106 between the source region 104 and the drain region 105 with a gate insulating layer 110 interposed therebetween. These configurations are the same as in the first embodiment.
　実施の形態２では、チャネル層１０３を、ＩｎＧａＡｓＳｂ層を井戸層１１２とし、ＩｎＧａＡｓまたはＩｎＧａＡｓＳｂからなる層を障壁層１１１とする量子井戸構造としている。また、この量子井戸構造は、ＩｎＧａＡｓＳｂからなる下地層１１３の上に形成している。実施の形態２では、チャネル層１０３を、下地層１１３と、この上に形成した障壁層１１１および井戸層１１２からなる量子井戸構造とから構成している。 In the second embodiment, the channel layer 103 has a quantum well structure in which the InGaAsSb layer is the well layer 112 and the layer made of InGaAs or InGaAsSb is the barrier layer 111. Further, this quantum well structure is formed on an underlayer 113 made of InGaAsSb. In the second embodiment, the channel layer 103 includes the underlying layer 113 and a quantum well structure including the barrier layer 111 and the well layer 112 formed thereon.
　ここで、井戸層１１２は、厚さが４ｎｍ以上２０ｎｍ以下とし、ＩｎＰより格子定数が大きく、３．５％以下の圧縮歪みを有する状態としてもよい。また、障壁層１１１は、ＩｎＧａＡｓＳｂから構成し、ＩｎＰより格子定数が小さく、引っ張り歪みを有する状態としてもよい。 Here, the well layer 112 may have a thickness of 4 nm to 20 nm, a lattice constant larger than that of InP, and a compressive strain of 3.5% or less. Further, the barrier layer 111 may be made of InGaAsSb and have a smaller lattice constant than InP and have a tensile strain.
　実施の形態２におけるトンネル電界効果トランジスタも、チャネル領域１０６とソース領域１０４との界面がトンネル接合領域１２１となる。このトンネル電界効果トランジスタは、トンネル接合領域１２１に加わる電界を、ゲート電圧によって制御することで、ドレイン領域１０５へと流れる電流を変化させ、オン・オフ動作を実現している。 も Also in the tunnel field effect transistor according to the second embodiment, the interface between the channel region 106 and the source region 104 becomes the tunnel junction region 121. In this tunnel field effect transistor, an electric field applied to the tunnel junction region 121 is controlled by a gate voltage, so that a current flowing to the drain region 105 is changed to realize an on / off operation.
　以下、実施の形態２におけるトンネル電界効果トランジスタの製造方法について説明する。まず、半絶縁性ＩｎＰからなる基板１０１の上に、層厚０．１μｍのＩｎＰ層１０２を成長し、この上にＳｂ組成比０．０７でＩｎＰと格子整合するＩｎＧａＡｓＳｂからなる層厚７０ｎｍの下地層１１３を成長する。 Hereinafter, a method for manufacturing the tunnel field effect transistor according to the second embodiment will be described. First, an InP layer 102 having a layer thickness of 0.1 μm is grown on a substrate 101 made of semi-insulating InP, and an InP layer 102 made of InGaAsSb lattice-matched to InP with an Sb composition ratio of 0.07 is formed thereon. The stratum 113 is grown.
　引き続き、下地層１１３の上に、Ｓｂ組成比０．１、引っ張り歪１．０４％、層厚１５ｎｍのＩｎＧａＡｓＳｂからなる障壁層１１１、Ｓｂ組成比０．２、圧縮歪１．６３％、層厚１２ｎｍのＩｎＧａＡｓＳｂからなる井戸層１１２、Ｓｂ組成比０．１、引っ張り歪１．０４％、層厚３ｎｍのＩｎＧａＡｓＳｂからなる障壁層１１１を成長する。この後、層厚２０ｎｍのＩｎＰ表面保護層を成長する。 Subsequently, on the underlayer 113, a barrier layer 111 made of InGaAsSb having a Sb composition ratio of 0.1, a tensile strain of 1.04%, and a layer thickness of 15 nm, an Sb composition ratio of 0.2, a compressive strain of 1.63%, and a layer thickness of A well layer 112 made of InGaAsSb having a thickness of 12 nm, a barrier layer 111 made of InGaAsSb having a composition ratio of Sb of 0.1, a tensile strain of 1.04%, and a thickness of 3 nm are grown. Thereafter, an InP surface protection layer having a thickness of 20 nm is grown.
　この後、前述した実施の形態１と同様にすることで、ソース領域１０４およびドレイン領域１０５を形成し、ゲート絶縁層１１０，ゲート電極１０９を形成し、ソース電極１０７，ドレイン電極１０８を形成する。ソース領域１０４およびドレイン領域１０５は、例えば、下地層１１３に到達する深さに形成すればよい。 Then, the source region 104 and the drain region 105 are formed, the gate insulating layer 110 and the gate electrode 109 are formed, and the source electrode 107 and the drain electrode 108 are formed in the same manner as in the first embodiment. The source region 104 and the drain region 105 may be formed to a depth reaching the base layer 113, for example.
　実施の形態２におけるＩｎＧａＡｓＳｂの歪補償量子井戸構造をチャネル層１０３に用いたプレーナ型のトンネル電界トランジスタは、ソース電圧６０ｍＶ、（ゲート電圧－しきい値電圧）１Ｖの条件において、ドレイン電流が１．９×１０-1μＡ／μｍであり、Ｓ値の最小値が５１ｍＶ／ｄｅｃ．である。 The planar-type tunneling electric field transistor using the strain-compensated quantum well structure of InGaAsSb according to the second embodiment for the channel layer 103 has a drain current of 1.0 m under the conditions of a source voltage of 60 mV and (gate voltage-threshold voltage) of 1 V. 9 × 10 −1 μA / μm, and the minimum value of the S value is 51 mV / dec. It is.
　上述した実施の形態２におけるプレーナ型のトンネル電界トランジスタは、実施の形態１のトンネル電界トランジスタよりもドレイン電流が高く、Ｓ値の最小値が低い。このように、チャネル層１０３にＩｎＧａＡｓＳｂの歪補償量子井戸構造を用いることで、チャネル層１０３のバンドギャップを小さくでき、トンネル電界効果トランジスタのデバイス特性を向上させることができる。 {Circle around (2)} The planar-type tunnel electric field transistor according to the second embodiment has a higher drain current and a lower minimum S value than the tunnel electric field transistor according to the first embodiment. As described above, by using the strain-compensated quantum well structure of InGaAsSb for the channel layer 103, the band gap of the channel layer 103 can be reduced, and the device characteristics of the tunnel field effect transistor can be improved.
　なお上述では、チャネル層１０３に歪補償量子井戸構造を用いた例について説明したが、ＩｎＧａＡｓＳｂから構成した井戸層１１２が用いられていれば、チャネル層１０３のバンドギャップを小さくできることに変わりはない。このため、障壁層１１１に引っ張り歪が加わっていない歪量子井戸構造や、障壁層１１１をＩｎＧａＡｓから構成した量子井戸構造をチャネル層１０３に用いた場合でも、前述同様にデバイス特性が改善されることは明らかである。 In the above description, the example in which the strain compensation quantum well structure is used for the channel layer 103 has been described. However, if the well layer 112 made of InGaAsSb is used, the band gap of the channel layer 103 can be reduced. Therefore, even when a strained quantum well structure in which tensile strain is not applied to the barrier layer 111 or a quantum well structure in which the barrier layer 111 is made of InGaAs is used for the channel layer 103, device characteristics are improved as described above. Is clear.
　次に、実施の形態２におけるトンネル電界効果トランジスタにおけるチャネル層１０３の、井戸層１１２についてより詳細に説明する。 Next, the well layer 112 of the channel layer 103 in the tunnel field effect transistor according to the second embodiment will be described in more detail.
　実施の形態１において図２を用いて説明したように、ＩｎＰよりも大きな格子定数を持つＩｎＧａＡｓＳｂでは、Ｓｂ組成比が同じでもＩｎＰに格子整合するＩｎＧａＡｓＳｂよりバンドギャップを小さくできる。しかし、ＩｎＰとは格子定数が異なるＩｎＧａＡｓＳｂを結晶成長する場合、格子歪に起因した結晶欠陥の発生が問題となる。この結晶欠陥の発生を抑えるためには、ＩｎＧａＡｓＳｂの層厚を小さくした歪量子井戸構造を用いることが有効である。 As described in Embodiment 1 with reference to FIG. 2, InGaAsSb having a larger lattice constant than InP can have a smaller band gap than InGaAsSb lattice-matched to InP even with the same Sb composition ratio. However, when InGaAsSb having a lattice constant different from that of InP is crystal-grown, the generation of crystal defects due to lattice distortion becomes a problem. In order to suppress the occurrence of the crystal defects, it is effective to use a strained quantum well structure in which the thickness of InGaAsSb is reduced.
　しかし、ＩｎＧａＡｓＳｂ歪量子井戸構造で井戸層の層厚を小さくし過ぎると、量子サイズ効果によりバンドギャップが増加する。この場合、トンネル電界トランジスタにおけるトンネル電流は減少する。以下では、ＩｎＧａＡｓＳｂ歪量子井戸を用いたトンネル接合において、トンネル電流密度を顕著に減少させないために必要となる井戸層の層厚の範囲について説明する。 However, if the thickness of the well layer is too small in the InGaAsSb strained quantum well structure, the band gap increases due to the quantum size effect. In this case, the tunnel current in the tunnel field transistor decreases. In the following, a description will be given of a range of the thickness of the well layer necessary for not significantly reducing the tunnel current density in the tunnel junction using the InGaAsSb strained quantum well.
　図６は、ＩｎＧａＡｓＳｂを用いた歪量子井戸構造において、井戸層の層厚を２，４，６，８，１０，１２ｎｍとした場合について、この歪量子井戸構造を用いたトンネル接合におけるトンネル電流密度の電界強度依存性を示している。ＩｎＧａＡｓＳｂ歪量子井戸構造において、ＩｎＧａＡｓＳｂ井戸層のＳｂ組成を０．１、ＩｎＰに対する格子不整合を＋１．５％とし、障壁層はＳｂ組成比が０．１でＩｎＰに格子整合するＩｎＧａＡｓＳｂとした。図６には、比較のために図３で示したＩｎＧａＡｓを用いたトンネル接合の結果も示してある。 FIG. 6 shows a tunnel current density in a tunnel junction using the strained quantum well structure when the well layer has a thickness of 2, 4, 6, 8, 10, 12 nm in the strained quantum well structure using InGaAsSb. Of FIG. In the InGaAsSb strained quantum well structure, the Sb composition of the InGaAsSb well layer was 0.1, the lattice mismatch with InP was + 1.5%, and the barrier layer was InGaAsSb with an Sb composition ratio of 0.1 and lattice matching with InP. FIG. 6 also shows the result of the tunnel junction using InGaAs shown in FIG. 3 for comparison.
　ＩｎＧａＡｓＳｂ歪量子井戸を用いたトンネル接合では、ＩｎＧａＡｓを用いた場合より大きなトンネル電流密度が得られる。このＩｎＧａＡｓＳｂ歪量子井戸を用いたトンネル接合の電流密度は、井戸層の層厚により変化する。図６に示すように、ＩｎＧａＡｓＳｂ歪量子井戸を用いた場合のトンネル電流密度は、井戸層の層厚を２ｎｍから４ｎｍに増やすことで急激に増加するが、この後、４ｎｍ以上で層厚を増やしても急激には増加しない。このことから、ＩｎＧａＡｓＳｂ歪量子井戸層の層厚は、４ｎｍ以上であることが望ましいことが分かる。井戸層の層厚の上限については、量子井戸としての量子サイズ効果がある層厚であれば良く、具体的には２０ｎｍ以下であれば良い。 ト ン ネ ル In a tunnel junction using an InGaAsSb strained quantum well, a larger tunnel current density can be obtained than in the case of using InGaAs. The current density of the tunnel junction using the InGaAsSb strained quantum well changes depending on the thickness of the well layer. As shown in FIG. 6, the tunnel current density when the InGaAsSb strained quantum well is used increases sharply by increasing the layer thickness of the well layer from 2 nm to 4 nm. But it does not increase rapidly. This indicates that the thickness of the strained InGaAsSb quantum well layer is desirably 4 nm or more. The upper limit of the thickness of the well layer may be a thickness having a quantum size effect as a quantum well, specifically, 20 nm or less.
　図６では、井戸層にＳｂ組成比が０．１であり、ＩｎＰに対する格子不整合が＋１．５％のＩｎＧａＡｓＳｂを用いた例について示したが、後述するようにＳｂ組成比が０．１以外の場合や、ＩｎＰに対する格子不整合が＋１．５％以外の場合でも、トンネル電流密度は絶対値が異なるのみで井戸層の層厚として４ｎｍ以上が有効であることに変わりはない。 FIG. 6 shows an example in which the Sb composition ratio of the well layer is 0.1 and the lattice mismatch with InP is + 1.5%, but the Sb composition ratio is other than 0.1 as described later. And the lattice mismatch with InP is other than + 1.5%, the tunnel current density is different only in absolute value, and 4 nm or more is still effective as the well layer thickness.
　上記の例では、障壁層にＩｎＰに格子整合するＩｎＧａＡｓＳｂを用いた歪量子井戸構造について説明したが、本発明は格子整合しない障壁層を用いた場合においても有効である。以下に、井戸層とは反対の格子歪（引っ張り歪）を加えた障壁層を用いた量子井戸の例について説明する。障壁層に井戸層とは反対の格子歪を加えた量子井戸は、井戸層の格子歪を補償する効果があるため、歪補償量子井戸と呼ばれる。本発明（実施の形態２）における井戸層は、圧縮歪が加わったＩｎＧａＡｓＳｂであるため、歪補償量子井戸構造にするためには障壁層に引っ張り歪を加える必要がある。 In the above example, the strain quantum well structure using InGaAsSb lattice-matched to InP is described as the barrier layer, but the present invention is also effective when a barrier layer that does not lattice-match is used. Hereinafter, an example of a quantum well using a barrier layer to which lattice strain (tensile strain) opposite to that of the well layer is applied will be described. A quantum well in which a barrier layer has lattice strain opposite to that of a well layer has an effect of compensating for lattice strain in the well layer, and is therefore called a strain-compensated quantum well. Since the well layer in the present invention (Embodiment 2) is made of InGaAsSb to which a compressive strain is applied, it is necessary to apply a tensile strain to the barrier layer in order to form a strain compensation quantum well structure.
　ＩｎＧａＡｓＳｂでは、Ｇａ組成比を増加させることで容易に引っ張り歪を加えることができる。Ｇａ組成比が高いＩｎＧａＡｓＳｂを障壁層に用いることで、伝導帯におけるバンド不連続が変化し、ＩｎＧａＡｓＳｂ井戸層への電子の閉じ込めが増大する。この電子の閉じ込めの増大は、以下のようにデバイス特性を向上させる上でも有用である。 In InGaAsSb, tensile strain can be easily applied by increasing the Ga composition ratio. By using InGaAsSb having a high Ga composition ratio for the barrier layer, band discontinuity in the conduction band changes, and confinement of electrons in the InGaAsSb well layer increases. This increase in electron confinement is also useful for improving device characteristics as described below.
　プレーナ型のトンネル電界効果トランジスタにおいて、電子は井戸層内に閉じ込められた状態で、ソース領域からドレイン領域へと電子が移動する。引っ張り歪を加えるためにＧａ組成比を高くしたＩｎＧａＡｓＳｂを障壁層に用いることで、電子が移動の際に井戸層から漏れ出すことを抑制できる。 In a planar tunnel field effect transistor, electrons move from the source region to the drain region while electrons are confined in the well layer. By using InGaAsSb with a high Ga composition ratio for the barrier layer to apply a tensile strain, it is possible to prevent electrons from leaking from the well layer during movement.
　次に、歪補償量子構造をトンネル電界トランジスタのチャネル層に用いる場合の井戸層の層厚について説明する。 Next, the thickness of the well layer when the strain compensation quantum structure is used for the channel layer of the tunnel electric field transistor will be described.
　図７は、ＩｎＧａＡｓＳｂを用いた歪補償量子井戸構造において、井戸層の層厚を２，４，６，８，１０，１２ｎｍとした場合について、この歪補償量子井戸構造を用いたトンネル接合のトンネル電流密度の電界強度依存性を示している。歪補償量子井戸構造において、ＩｎＧａＡｓＳｂ井戸層のＳｂ組成を０．２、ＩｎＰに対する格子不整合を＋１４４％とし、障壁層はＳｂ組成比が０．１でＩｎＰに対する格子不整合が－０．８７％（符号が負、引っ張り歪）のＩｎＧａＡｓＳｂとした。図７には、図６と同様、比較のためにＩｎＧａＡｓを用いたトンネル接合の結果も示してある。 FIG. 7 shows the tunneling of the tunnel junction using the strain-compensated quantum well structure in the case where the thickness of the well layer is 2, 4, 6, 8, 10, and 12 nm in the strain-compensated quantum well structure using InGaAsSb. The electric field strength dependence of the current density is shown. In the strain-compensated quantum well structure, the Sb composition of the InGaAsSb well layer is 0.2, the lattice mismatch with InP is + 144%, and the Sb composition ratio of the barrier layer is 0.1 and the lattice mismatch with InP is -0.87%. (Sign is negative, tensile strain) InGaAsSb. FIG. 7 also shows the result of the tunnel junction using InGaAs for comparison, as in FIG.
　図７に示すように、歪補償量子井戸構造を用いた場合も、図６を用いて説明した歪量子井戸構造を用いた場合と同様の傾向を示す。具体的には、トンネル電流密度は、井戸層の層厚を２ｎｍから４ｎｍに増加させることにより急激に増加するが、この後は層厚を増加させても電流密度は急激には増加しない。従って、歪補償量子井戸構造をチャネル層に用いた場合でも、井戸層としては４ｎｍ以上の層厚が有効である。 示 す As shown in FIG. 7, the tendency when the strain-compensated quantum well structure is used also shows the same tendency as when the strain-quantum well structure described with reference to FIG. 6 is used. Specifically, the tunnel current density increases sharply by increasing the layer thickness of the well layer from 2 nm to 4 nm, but thereafter, even if the layer thickness is increased, the current density does not increase sharply. Therefore, even when the strain compensation quantum well structure is used for the channel layer, a layer thickness of 4 nm or more is effective as the well layer.
　図７に示す結果は、井戸層の上下の障壁層に引っ張り歪が加わった例だが、上下のどちらか一方の障壁層に引っ張り歪が加わった場合でも、量子サイズ効果が存在し、ＩｎＧａＡｓＳｂ井戸層を用いることで小さいバンドギャップが得られることに変わりはないため、上述の井戸層の層厚の有効範囲に変わりはない。 The result shown in FIG. 7 is an example in which tensile strain is applied to the upper and lower barrier layers above the well layer. However, even when tensile strain is applied to one of the upper and lower barrier layers, the quantum size effect exists and the InGaAsSb well layer Is used to obtain a small band gap, so that the effective range of the well layer thickness described above does not change.
　前述したように、ＩｎＰとは格子定数が異なるＩｎＧａＡｓＳｂを結晶成長する場合、格子歪に起因した結晶欠陥の発生が問題となる。具体的には、層厚が一定値以上になると歪応力に起因した結晶欠陥が発生し易くなり、良質の結晶を得ることが難しくなる。この結晶欠陥が発生し始める層厚は、臨界層厚と呼ばれる。トンネル電界トランジスタに用いる量子井戸の層厚は４ｎｍ以上にすることが望ましく、井戸層を層厚は４ｎｍ以上にするには井戸層に加える圧縮歪を一定の値以下にする必要がある。言い換えると、臨界層厚が４ｎｍとなる格子歪が、井戸層に加えることのできる格子歪の上限である。 As described above, when InGaAsSb having a different lattice constant from InP is crystal-grown, generation of crystal defects due to lattice distortion becomes a problem. Specifically, when the layer thickness exceeds a certain value, crystal defects due to strain stress are likely to occur, and it becomes difficult to obtain high-quality crystals. The layer thickness at which the crystal defects begin to occur is called the critical layer thickness. It is desirable that the layer thickness of the quantum well used for the tunnel electric field transistor is 4 nm or more, and in order to make the layer thickness of the well layer 4 nm or more, the compressive strain applied to the well layer needs to be a certain value or less. In other words, the lattice strain at which the critical layer thickness becomes 4 nm is the upper limit of the lattice strain that can be applied to the well layer.
　図８は、Ｓｂ組成比が０．１のＩｎＧａＡｓＳｂについて、格子歪（圧縮歪）を変化させた場合の臨界層厚を、非特許文献７に記載の計算方法を用いて求めた結果を示している。また、図９は、Ｓｂ組成比が０．２のＩｎＧａＡｓＳｂについて、格子歪（圧縮歪）を変化させた場合の臨界層厚を、非特許文献７に記載の計算方法を用いて求めた結果を示している。 FIG. 8 shows the results obtained by using the calculation method described in Non-Patent Document 7 for the critical layer thickness when lattice strain (compression strain) is changed for InGaAsSb having an Sb composition ratio of 0.1. I have. FIG. 9 shows the result of calculating the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.2 by changing the lattice strain (compression strain) using the calculation method described in Non-Patent Document 7. Is shown.
　井戸層の層厚が、図８、図９に示された曲線より大きくなると結晶欠陥が発生し易くなる。図８、図９から、ＩｎＧａＡｓＳｂのＳｂ組成比が０．１、０．２のいずれの場合においても、臨界層厚が４ｎｍとなる格子歪は＋３．５％である。従って、ＩｎＧａＡｓＳｂ量子井戸をトンネル電界トランジスタのチャネル層に用いる場合、井戸層の圧縮歪を＋３．５％以下にすることが望ましい。 と If the thickness of the well layer is larger than the curves shown in FIGS. 8 and 9, crystal defects are likely to occur. 8 and 9, the lattice strain at which the critical layer thickness is 4 nm is + 3.5% in both cases where the Sb composition ratio of InGaAsSb is 0.1 or 0.2. Therefore, when the InGaAsSb quantum well is used for the channel layer of the tunnel electric field transistor, the compressive strain of the well layer is desirably set to + 3.5% or less.
　ＩｎＧａＡｓＳｂを井戸層に用いれば、ＩｎＧａＡｓを用いた場合よりも容易に歪補償量子井戸構造を作製することができる（非特許文献８参照）。歪補償量子井戸構造をトンネル電界トランジスタに応用するにあたり、各層の層厚、歪量をチェックするために、以下のような多重量子井戸構造を作製した。 (4) When InGaAsSb is used for the well layer, a strain-compensated quantum well structure can be manufactured more easily than when InGaAs is used (see Non-Patent Document 8). In applying the strain-compensated quantum well structure to a tunnel electric field transistor, the following multiple quantum well structure was fabricated to check the thickness of each layer and the amount of strain.
　トンネル電界トランジスタでは、単一量子井戸を用いるが、井戸層と障壁層の層厚、歪量は、多重量子井戸構造にした方が解析が容易である。この解析のため、多重量子井戸構造を前述の有機金属分子線エピタキシー法を用いて作製した。図１０は、作製した多重量子井戸構造の層構造を示した断面図である。この多重量子井戸構造は、まず、ＩｎＰ基板２０１の上にＩｎＰからなる層厚０．１μｍのバッファ層２０２を成長する。引き続き、バッファ層２０２の上に、歪補償多重量子井戸構造として、ＩｎＧａＡｓＳｂからなる１１層の障壁層２０３と、ＩｎＧａＡｓＳｂからなる１０層の井戸層２０４とを交互に積層させた。井戸層２０４のＳｂ組成比は０．２、障壁層２０３のＳｂ組成比は０．１になるように原料供給量を調整した。 (4) Although a single quantum well is used in the tunnel field transistor, the layer thickness and the strain amount of the well layer and the barrier layer can be easily analyzed by using a multiple quantum well structure. For this analysis, a multiple quantum well structure was fabricated by using the above-mentioned metalorganic molecular beam epitaxy method. FIG. 10 is a sectional view showing a layer structure of the manufactured multiple quantum well structure. In this multiple quantum well structure, first, a buffer layer 202 of InP having a thickness of 0.1 μm is grown on an InP substrate 201. Subsequently, eleven barrier layers 203 made of InGaAsSb and ten well layers 204 made of InGaAsSb were alternately stacked on the buffer layer 202 as a strain-compensated multiple quantum well structure. The raw material supply amounts were adjusted so that the Sb composition ratio of the well layer 204 was 0.2 and the Sb composition ratio of the barrier layer 203 was 0.1.
　図１１は、上述した多重量子井戸構造のＸ線回折パターンの測定結果（実験）とシミュレーション結果とを比較して示している。この比較から、井戸層２０４は、圧縮歪が１．６３％、層厚が１２．９ｎｍのＩｎＧａＡｓＳｂ、障壁層２０３は引っ張り歪が１．０４％、層厚が１９．０ｎｍのＩｎＧａＡｓＳｂであることが分かった。 FIG. 11 shows a comparison between a measurement result (experiment) and a simulation result of the X-ray diffraction pattern of the above-described multiple quantum well structure. From this comparison, the well layer 204 may be made of InGaAsSb with a compressive strain of 1.63% and a layer thickness of 12.9 nm, and the barrier layer 203 may be made of InGaAsSb with a tensile strain of 1.04% and a layer thickness of 19.0 nm. Do you get it.
　図１２は、上述した多重量子井戸構造の室温におけるフォトルミネッセンス発光スペクトルを示している。フォトルミネッセンスの発光ピークのエネルギーは、０．５７ｅＶである。量子井戸構造では、発光ピークのエネルギーと井戸層のバンドギャップがほぼ一致する。このため、このＩｎＧａＡｓＳｂを用いた歪補償量子井戸構造（多重量子井戸構造）のバンドギャップは、ＩｎＰに格子整合するＩｎＧａＡｓ（０．７４ｅＶ）よりも小さいことが確認された。 FIG. 12 shows a photoluminescence emission spectrum of the above-described multiple quantum well structure at room temperature. The energy of the emission peak of photoluminescence is 0.57 eV. In the quantum well structure, the energy of the emission peak substantially matches the band gap of the well layer. For this reason, it was confirmed that the band gap of the strain compensation quantum well structure (multiple quantum well structure) using InGaAsSb was smaller than that of InGaAs (0.74 eV) lattice-matched to InP.
　以上に説明したように、本発明によれば、チャネル層を、ＩｎＰからなるＩｎＰ層の上に形成されたＩｎＧａＡｓＳｂからなるＩｎＧａＡｓＳｂ層を備える構成としたので、プレーナ型のトンネル電界効果トランジスタのデバイス特性を向上させることができるようになる。本発明によれば、プレーナ型のトンネル電界効果トランジスタにおいて、オン状態における電流の増加が可能にするとともに、小さなゲート電圧で動作させることも可能になる。これにより、トンネル電界効果トランジスタを電子回路に用いた電子部品では、消費電力を低減でき、結果として電子機器の省エネルギー化を実現できるようになる。 As described above, according to the present invention, since the channel layer is configured to include the InGaAsSb layer made of InGaAsSb formed on the InP layer made of InP, the device characteristics of the planar tunnel field effect transistor Can be improved. According to the present invention, in a planar tunnel field effect transistor, it is possible to increase the current in the ON state and to operate the transistor with a small gate voltage. Thus, in an electronic component using a tunnel field effect transistor in an electronic circuit, power consumption can be reduced, and as a result, energy saving of an electronic device can be realized.
　なお、本発明は以上に説明した実施の形態に限定されるものではなく、本発明の技術的思想内で、当分野において通常の知識を有する者により、多くの変形および組み合わせが実施可能であることは明白である。 Note that the present invention is not limited to the above-described embodiments, and many modifications and combinations can be made by those having ordinary knowledge in the art without departing from the technical concept of the present invention. That is clear.
　１０１…基板、１０２…ＩｎＰ層、１０３…チャネル層、１０４…ソース領域、１０５…ドレイン領域、１０６…チャネル領域、１０７…ソース電極、１０８…ドレイン電極、１０９…ゲート電極、１１０…ゲート絶縁層、１２１…トンネル接合領域。 DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... InP layer, 103 ... Channel layer, 104 ... Source region, 105 ... Drain region, 106 ... Channel region, 107 ... Source electrode, 108 ... Drain electrode, 109 ... Gate electrode, 110 ... Gate insulating layer, 121 ... Tunnel junction area.

Claims (4)

  1. 　ＩｎＰからなるＩｎＰ層の上に形成されたＩｎＧａＡｓＳｂからなるＩｎＧａＡｓＳｂ層を備えるチャネル層と、
    　前記チャネル層に形成された第１導電型のソース領域と、
    　前記ソース領域と所定の間隔を開けて前記チャネル層に形成された第２導電型のドレイン領域と、
    　前記ソース領域に接続して形成されたソース電極と、
    　前記ドレイン領域に接続して形成されたドレイン電極と、
    　前記ソース領域と前記ドレイン領域との間のチャネル領域の上に形成されたゲート電極と
    　を備え、
    　前記ＩｎＧａＡｓＳｂ層は、Ｖ族元素におけるＳｂの組成比が０．０１以上０．３以下とされている
    　ことを特徴とするトンネル電界効果トランジスタ。     A channel layer including an InGaAsSb layer made of InGaAsSb formed on the InP layer made of InP;
    A first conductivity type source region formed in the channel layer;
    A second conductivity type drain region formed in the channel layer at a predetermined distance from the source region;
    A source electrode formed by connecting to the source region;
    A drain electrode formed by connecting to the drain region;
    A gate electrode formed on a channel region between the source region and the drain region,
    The tunneling field effect transistor, wherein the InGaAsSb layer has a composition ratio of Sb in a group V element of 0.01 to 0.3.
  2. 　請求項１記載のトンネル電界効果トランジスタにおいて、
    　前記チャネル層は、前記ＩｎＧａＡｓＳｂ層を井戸層とし、ＩｎＧａＡｓまたはＩｎＧａＡｓＳｂからなる層を障壁層とする量子井戸構造とされている
    　ことを特徴とするトンネル電界効果トランジスタ。     The tunnel field effect transistor according to claim 1,
    A tunnel field effect transistor, wherein the channel layer has a quantum well structure using the InGaAsSb layer as a well layer and a layer made of InGaAs or InGaAsSb as a barrier layer.
  3. 　請求項２記載のトンネル電界効果トランジスタにおいて、
    　前記井戸層は、厚さが４ｎｍ以上２０ｎｍ以下とされ、ＩｎＰより格子定数が大きく、３．５％以下の圧縮歪みを有している
    　ことを特徴とするトンネル電界効果トランジスタ。     The tunnel field effect transistor according to claim 2,
    The tunnel field effect transistor, wherein the well layer has a thickness of 4 nm or more and 20 nm or less, has a larger lattice constant than InP, and has a compressive strain of 3.5% or less.
  4. 　請求項２または３記載のトンネル電界効果トランジスタにおいて、
    　前記障壁層は、ＩｎＧａＡｓＳｂから構成され、ＩｎＰより格子定数が小さく、引っ張り歪みを有している
    　ことを特徴とするトンネル電界効果トランジスタ。     The tunnel field effect transistor according to claim 2 or 3,
    The tunnel field effect transistor, wherein the barrier layer is made of InGaAsSb, has a smaller lattice constant than InP, and has tensile strain.
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Publication number Priority date Publication date Assignee Title
JP2006278397A (en) * 2005-03-28 2006-10-12 Nippon Telegr & Teleph Corp <Ntt> Pseudomorphic quantum well structure and manufacturing method thereof
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