JP6531243B2 - Tunnel field effect transistor and method of manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a tunnel field effect transistor and a method of manufacturing the field effect transistor.

  In order to make semiconductor integrated circuits have higher performance and lower power consumption, it is necessary to miniaturize the current core device, MOSFET (metal-oxide-semiconductor field-effect transistor), to enable low voltage operation. However, when the MOSFET is miniaturized, leakage current increases due to the short channel effect, and it becomes difficult to further reduce the power supply voltage. The reason for this is that the subthreshold swing (S.S.) at room temperature approaches the physical limit and 60 mV / dec. It is difficult to reduce below. Therefore, 60 mV / dec. The following S. S. There is a need for new devices that allow for

  60 mV / dec. The following S. S. A tunnel field effect transistor (TFET) is attracting attention as a device that enables the use of tunneling in the junction region between the source region and the channel region. For example, Non-Patent Document 1 describes a TFET with InGaAs in which carbon is added to a source region by a molecular beam epitaxy (MBE) method, S. S. Is 60 mV / dec. It has been reported. Further, Patent Document 1 discloses a technique for forming a tunnel region and a channel region with different materials in a configuration of a lateral TFET and realizing a lateral TFET from the relationship of the energy band structure of each region.

JP 2012-514345 gazette

G. Dewey et al., IEDM, p 785, 2011

  However, since the TFET described in Non-Patent Document 1 has a vertical structure, it has low affinity with existing complementary field effect transistors (CMOSFETs), and integration with CMOS circuits is also difficult. In that respect, although the TFET described in Patent Document 1 has a lateral structure, such problems are small, but in the lateral TFET described in Patent Document 1, the source region is GaAsSb and the channel region is InGaAs, Since it comprises with different materials, the additional process of an etching process, the formation process of a mask material, and the regrowth process is needed, and the subject that the increase in a manufacturing cost is caused significantly occurs.

  An object of the present invention is to provide a technique for manufacturing a lateral structure TFET without causing a significant increase in cost.

In addition, TFET has a structural problem that the on current can not be sufficiently increased because the drain current is controlled by utilizing the tunnel phenomenon between the source region and the channel region. Therefore, the present inventors, as a material capable of obtaining a large tunneling current, considered InGaAs interband transition is a direct transition and the narrow band gap and promising, an In _0.53 which is lattice matched to the InP substrate We examined planar TFETs using Ga _0.47 As and realized that although we could get some increase in on current, we needed more on current. Although larger on current can be obtained by increasing the In composition of InGaAs to narrow the band gap, it has been recognized that there is a problem that the off current is increased.

  An object of the present invention is to provide a technique for increasing the on current without increasing the off current.

  Furthermore, the device characteristics of TFETs, in particular S.I. S. To 60 mV / dec. In order to reduce to the following, a channel region having a high tunneling probability, a source region having a low defect density, and a tunnel junction region having a steep impurity concentration gradient are required.

  An object of the present invention is to provide a technique for manufacturing a channel region having a high tunneling probability, a source region having a low defect density, and a tunnel junction region having a steep impurity concentration gradient without causing a significant increase in cost.

  In order to solve the above problems, according to a first aspect of the present invention, a substrate, a laminated semiconductor layer located on the substrate, and a source region exhibiting a first conductivity type formed in the laminated semiconductor layer A drain region formed in the stacked semiconductor layer and exhibiting a second conductivity type opposite to the first conductivity type, and a gate structure for applying an electric field to a channel region between the source region and the drain region A tunnel field effect transistor in which the source region, the channel region, and the drain region are aligned in a direction along the surface of the laminated semiconductor layer, and the laminated semiconductor layer is a first semiconductor And a second layer made of a second semiconductor which is located farther from the substrate than the first layer, and the band gap of the second semiconductor is a band gap of the first semiconductor. Providing a smaller tunnel field effect transistor.

When the first conductivity type is n-type, the electron energy level at the upper end of the valence band of the second semiconductor is higher than that of the first semiconductor, and when the first conductivity type is p-type, the first semiconductor is more than the first semiconductor The electron energy level at the lower end of the conduction band of the second semiconductor may be low. The first semiconductor and the second semiconductor may be III-V group semiconductors. The first semiconductor is made of _{Inx1Ga1 -x1As} , the second semiconductor is made of _{Inx2Ga1 -x2As} , and the In composition x1 of the first semiconductor is the In composition x2 of the second semiconductor. It may be smaller. The laminated semiconductor layer further includes a third layer made of a third semiconductor, which is located farther from the substrate than the second layer, and the band gap of the third semiconductor is the band gap of the second semiconductor It may be different. The third semiconductor and the second semiconductor may have different electron energy levels at the top of the valence band or at the bottom of the conduction band. The first semiconductor, the second semiconductor and the third semiconductor may be III-V group semiconductors. The first semiconductor comprises _{Inx1Ga1 -x1As} , the second semiconductor comprises _{Inx2Ga1 -x2As} , the third semiconductor comprises _{Inx3Ga1 -x3As, and the first} semiconductor comprises The In composition x1 of one semiconductor may be smaller than the In composition x2 of the second semiconductor, and the In composition x3 of the third semiconductor may be different from the In composition x2 of the second semiconductor. The concentration of impurity atoms introduced into the source region is 1 × 10 ¹⁹ cm ⁻³ or more, and the concentration gradient of the impurity atoms is 10 nm / dec. It may be the following.

  In a second aspect of the present invention, in the method of manufacturing a tunnel field effect transistor described above, the laminated semiconductor layer including the first layer and the second layer is formed on the substrate by an epitaxial growth method. And a step of forming the source region in part of the laminated semiconductor layer, a step of forming an insulating layer on the laminated semiconductor layer, and the source region adjacent to the source region in plan view Forming the gate structure on the insulating layer, and facing the source region and the source region sandwiching the gate structure when the source region and the gate structure are viewed in plan. And a step of forming the drain region in a part of the laminated semiconductor layer. In the step of forming the source region, the source region is formed by thermally diffusing impurity atoms, and as the impurity atoms, the diffusion coefficient in the high concentration portion shows a value higher than the diffusion coefficient of the low concentration portion Atoms may be used.

FIG. 2 is a cross-sectional view of a TFET 100. The cross-sectional structure of the laminated semiconductor layer 120 of TFET100 is shown. FIG. 6 is a process diagram illustrating a method of manufacturing the TFET 100. It is a figure for demonstrating the current-voltage characteristic of TFET100. The S. S. It is a figure for demonstrating the dependence to the electric current of.

  Embodiments will be described below with reference to the drawings. The drawings are merely schematics for explaining the configuration of the invention, and the sizes, shapes, numbers, ratios of sizes of different members, and the like of the respective members are not limited to those illustrated.

  FIG. 1 is a cross-sectional view of a tunnel field effect transistor (TFET) 100 according to the present embodiment. The TFET 100 has a substrate 105, and a buffer layer 110 and a laminated semiconductor layer 120 are formed on the substrate 105. A channel region 125, a source region 130, and a drain region 160 are formed in the stacked semiconductor layer 120, and a tunnel junction region 140 is formed at an end of the channel region 125 closer to the source region 130. The source region 130, the channel region 125, and the drain region 160 are aligned in the direction along the surface of the stacked semiconductor layer 120. That is, TFET 100 has a lateral structure.

  A gate structure 150 is formed adjacent to channel region 125, and a metal source electrode 135 and a metal drain electrode 165 are formed in contact with source region 130 and drain region 160, respectively. Gate structure 150 applies an electric field to channel region 125 between source region 130 and drain region 160. Gate structure 150 includes metal gate electrode 155 and gate insulator 151, which is electrically isolated from source region 130, channel region 125 and drain region 160 by gate insulator 151.

  The source region 130 exhibits a first conductivity type, and the drain region 160 exhibits a second conductivity type opposite to the first conductivity type. When source region 130 is p-type doped, drain region 160 is n-type doped and TFET 100 becomes an n-channel TFET (NTFET). When source region 130 is n-doped, drain region 160 is p-doped and TFET 100 becomes a p-channel TFET (PTFE).

  As the substrate 105, for example, a silicon (Si) wafer, a silicon on insulator (SOI) wafer, a germanium (Ge) wafer, a germanium on insulator (GOI) wafer, a gallium arsenide (GaAs) wafer, an indium phosphide (InP) A semiconductor member such as a wafer, an indium arsenide (InAs) wafer, a gallium antimonide (GaSb) wafer, or a gallium nitride (GaN) wafer can be exemplified. For example, a substrate made of a member other than a semiconductor such as a glass member, a plastic member, a ceramic member, etc., or a substrate of a multilayer structure in which a plurality of layers made of various members are laminated may be applied.

The buffer layer 110 is formed between the substrate 105 and the stacked semiconductor layer 120 for the purpose of improving the quality of the stacked semiconductor layer 120. The buffer layer 110 may be the same material as the stacked semiconductor layer 120 or may be a different material. When the stacked semiconductor layer 120 is a material including In _x Ga _1-x As (0 ≦ x ≦ 1), GaAs, InGaAs, InAlAs, InP or the like may be applied as the buffer layer 110. The formation of the buffer layer 110 is optional. The buffer layer 110 is not essential to the present invention.

  The stacked semiconductor layer 120 is located on the substrate 105. As materials of the stacked semiconductor layer 120, Si, Ge, SiGe, SnGe, SiSnGe, GaAs, InAs, InAs, InGaAs, InAlAs, InAlAs, InGaAlAs, InP, GaP, InSb, GaSb, AlSb, AlSb, InGaSb, GaN, InGaN, AlGaN, and mixed crystals thereof It can contain a compound.

  FIG. 2 shows a cross-sectional structure of the laminated semiconductor layer 120. As shown in FIG. The laminated semiconductor layer 120 includes a first layer 120a made of a first semiconductor, and a second layer 120b made of a second semiconductor, which is located farther from the substrate 105 than the first layer 120a. The laminated semiconductor layer 120 may further include a third layer 120c made of a third semiconductor, which is located farther from the substrate 105 than the second layer 120b, and further has a fourth layer made of a fourth semiconductor not shown. May be

  The first layer 120 a is a material that performs the function of improving the quality of the channel region 125. The band gap of the second semiconductor constituting the second layer 120b is smaller than the band gap of the first semiconductor constituting the first layer 120a. When the first conductivity type is n-type, the electron energy level of the upper end of the valence band of the second semiconductor constituting the second layer 120b is higher than that of the first semiconductor constituting the first layer 120a. When the p-type is p-type, the electron energy level at the lower end of the conduction band of the second semiconductor constituting the second layer 120b is lower than that of the first semiconductor constituting the first layer 120a. This can reduce the tunnel barrier height and increase the tunneling probability.

  The third layer 120 c and the optional fourth layer (not shown) made of a fourth semiconductor serve to improve the quality of the channel region 125 and the gate structure 150. The band gap of the third semiconductor constituting the third layer 120c is preferably different from the band gap of the second semiconductor. The third semiconductor and the second semiconductor preferably have different electron energy levels at the top of the valence band or the electron energy at the bottom of the conduction band.

A III-V group semiconductor can be mentioned as a 1st semiconductor, a 2nd semiconductor, and a 3rd semiconductor. As the first semiconductor _may include In _{x1 Ga 1-x1} As, the second _{semiconductor,} mention may be made of In _{x2 Ga 1-x2} As, a third _{semiconductor,} cited In _{x3 Ga 1-x3} As be able to. Here, the In composition x1 of the first semiconductor is smaller than the In composition x2 of the second semiconductor. The In composition x3 of the third semiconductor can be different from the In composition x2 of the second semiconductor. For example, the first semiconductor _In 0.53 _{Ga 0.47} As can be exemplified, as the second semiconductor _In 0.7 _{Ga 0.3} As can be exemplified, the _In 0.53 _{Ga 0.47} As a third semiconductor It can be illustrated.

  The film thickness of the first layer 120a is in the range of 1 to 1000 nm, preferably in the range of 5 to 500 nm, and more preferably in the range of 10 to 100 nm. The band gap of the first layer 120a is in the range of 0.1 to 3.4 eV, preferably in the range of 0.1 to 1.4 eV, and more preferably in the range of 0.1 to 1.0 eV. Have a range. In a particular embodiment, when the first layer 120a is InGaAs, its In composition has a range of 0.1 to 1.0, preferably 0.3 to 1.0.

  The thickness of the second layer 120b is in the range of 1 to 100 nm, preferably in the range of 1 to 50 nm, and more preferably in the range of 1 to 20 nm. The band gap of the second layer 120b is in the range of 0.1 to 1.0 eV, preferably in the range of 0.1 to 0.7 eV, and more preferably in the range of 0.1 to 0.6 eV. Have a range. In a particular embodiment, when the second layer 120b is InGaAs, its In composition has a range of 0.3 to 1.0, preferably a range of 0.58 to 1.0, Preferably, it has a range of 0.68 to 1.0.

  The material of the third layer 120c and the fourth layer (not shown) may be the same as the material constituting the first layer 120a or the second layer 120b. The film thickness thereof is in the range of 1 to 100 nm, preferably in the range of 1 to 50 nm, and more preferably in the range of 1 to 10 nm. In addition, the band gap has a range of 0.1 to 3.4 eV, preferably has a range of 0.1 to 1.4 eV, and more preferably has a range of 0.1 to 1.0 eV. In a particular embodiment, when the third layer 120c is InGaAs, its In composition has a range of 0.1 to 1.0, preferably 0.3 to 1.0.

  The source region 130 can be formed by doping the stacked semiconductor layer 120 with an impurity. The higher the absolute concentration of the added impurity and the steeper the concentration gradient, the better the TFET characteristics can be obtained. For example, as NTFET, an impurity showing p-type conductivity can be added. Examples of p-type impurity atoms for III-V semiconductors include Be, Mg, Ca, Sr, Ba, Zn, Cd, and Hg. Be is a light element, and is characterized in that impurity addition by ion implantation method and recovery of defects introduced into the crystal by a process by activation heat treatment are easy. An example of another p-type impurity atom for InGaAs can be Zn. When Zn is solid-phase diffused to InGaAs, the diffusion coefficient of Zn is proportional to the square of the Zn concentration, so that a steep Zn concentration profile can be realized. Thereby, good TFET characteristics can be obtained.

The absolute concentration of the impurity in the source region 130 is in the range of 5 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , preferably in the range of 1 × 10 ^{19 to} 7 × 10 ²⁰ cm ⁻³ , and more preferably 4 in the range of ^{× 10 19 ~5 × 10 20 cm} -3.

  Here, when the concentration gradient of the impurity in the source region 130 is defined as a film thickness value at which the concentration changes by one digit, the concentration gradient of the impurity in the source region 130 in the direction perpendicular to the substrate 105 is 0.1 to 30 nm /. dec. And preferably 0.1 to 10 nm / dec. And more preferably 0.1 to 5 nm / dec. Have a range of

  The tunnel junction region 140 is a junction region formed between the source region 130 and the channel region 125. When the TFET is off, the carrier tunneling probability is low, and when it is on, the carrier tunneling probability is high. The concentration gradient of impurities in the tunnel junction region 140 in the direction horizontal to the substrate 105 is 0.1 to 30 nm / dec. And preferably 0.1 to 10 nm / dec. And more preferably 0.1 to 5 nm / dec. Have a range of

The gate insulator 151 is an insulating layer which insulates the metal gate electrode 155, and the metal gate electrode 155 applies an electric field to the channel region 125 adjacent to the gate structure 150 to control the carrier tunneling probability of the tunnel junction region 140. Control the on / off of the TFET. For example, an insulator made of Al ₂ O ₃ , SiO ₂ , AIN, SiN, SiON, Ta ₂ O ₅ , ZrO ₂ , HfO ₂ , La ₂ O ₃ or a mixture thereof as the gate insulator 151. Layers may be applied. Examples of the metal gate electrode 155 include Ti, Ta, W, Al, Cu, Au, TiN, TaN, or a laminate of these.

  In the case of an NTFET, the drain region 160 can be doped with an impurity that exhibits n-type conductivity. Examples of n-type impurity atoms for a III-V group semiconductor include Si, S, Se, Ge, and Te.

  FIG. 3 is a flowchart illustrating an example of a method of manufacturing the TFET 100. By the manufacturing method 300 shown in FIG. 3, the TFET 100 shown in FIG. 1 can be formed.

  Step 310 of the manufacturing method 300 is a step of preparing a substrate. The substrate may be similar to the substrate 105 of the TFET 100 or may be another substrate. After forming the laminated semiconductor layer 120 using another substrate (not shown), transfer to the substrate 105 can also be performed using known direct wafer bonding technology. The buffer layer 110 may be included on the substrate 105. The buffer layer 110 may be the same material as the stacked semiconductor layer 120 or may be a different material.

  The process 320 of the manufacturing method 300 is a process of forming the laminated semiconductor layer 120. The process of forming the 1st layer 120a shown in FIG. 2 and the 2nd layer 120b in this order is included. A step of forming the third layer 120c, the fourth layer (not shown), and the like in this order may be included as needed.

  Hereinafter, the process of forming the laminated semiconductor layer 120 will be specifically described. For example, each layer such as the first layer 120a constituting the laminated semiconductor layer 120 can be formed by epitaxial growth using a molecular beam epitaxy (MBE) method or a vapor deposition (CVD) method. As an example, semiconductor layers made of GaAs, InGaAs, InAlAs, InP, GaN, InGaN, AlGaN, and a mixed crystal compound thereof can be formed to form each stacked semiconductor layer 120.

In one embodiment, when the III-V semiconductor crystal layer is formed by a CVD method, TMIn (trimethylindium) is used as an In source, TMGa (trimethylgallium) is used as a Ga source, and an Al source TMAl (trimethylaluminum) for the group V source, AsH ₃ (arsine) for the As source, PH ₃ (phosphine) for the P source, TMSb (trimethylantimony) for the Sb source, NH _{3 for the} N source (Ammonia) can be used. Hydrogen or nitrogen can be used as a carrier gas. The reaction temperature can be appropriately selected in the range of 300 to 900 ° C., preferably in the range of 450 to 750 ° C. In another embodiment, when the group IV semiconductor crystal layer is formed by the CVD method, SiH ₄ (silane) or Si ₂ H ₆ (disilane) is used as the Si source, and GeH ₄ (germane) as the Ge source. The Sn source can be SnCl ₄ (tin tetrachloride) or TBVSn (tributylvinyltin), and a compound in which some of the plural hydrogen atom groups are substituted by chlorine atoms or hydrocarbon groups is used. It can also be done. Hydrogen or nitrogen can be used as a carrier gas. The reaction temperature can be appropriately selected in the range of 300 to 900 ° C., preferably in the range of 450 to 750 ° C. The thickness of the epitaxial growth layer can be controlled by appropriately selecting the source gas supply amount and the reaction time.

  Step 330 of the manufacturing method 300 is a step of forming the source region 130. When the TFET 100 is an NTFET, it includes the step of adding an impurity that exhibits p-type conductivity. Be and Zn can be illustrated as a p-type impurity atom with respect to a III-V group semiconductor.

Hereinafter, an example in which the source region 130 is formed by solid phase diffusion of Zn will be described. First, Al ₂ O ₃ is formed to prevent unnecessary diffusion of Zn, and the source region 130 is coated with a Zn raw material layer by a spin-on-glass method and then subjected to activation heat treatment. The activation heat treatment temperature can be in the range of 400 to 700 ° C., and a temperature of 450 to 700 ° C. is desirable to reduce defects. In addition, the activation heat treatment time can be determined in about 5 seconds to 500 seconds according to the requirement of the device which needs the diffusion depth of Zn.

Step 340 of the manufacturing method 300 is a step of forming the gate insulator 151. An insulating layer is deposited over at least a portion of the gate structure 150 of the TFET 100 shown in FIG. For example, the gate insulator 151 can be formed by depositing an Al ₂ O ₃ layer using atomic layer deposition (ALD). For the formation of Al ₂ O ₃ , for example, TMA and H ₂ O can be used as raw materials.

  Step 350 of the manufacturing method 300 is a step of forming the metal gate electrode 155 on the gate insulator 151. The metal gate electrode 155 can be formed, for example, by vapor deposition or sputtering.

  Step 360 of the manufacturing method 300 is a step of forming the drain region 160. Drain region 160 can be formed, for example, by implanting Si by ion implantation. Also, in a specific embodiment, Ni-doped InGaAs may be formed as the drain region 160.

  Step 370 of the manufacturing method 300 is a step of forming the metal source electrode 135 and the metal drain electrode 165. The metal source electrode 135 and the metal drain electrode 165 can be formed by, for example, a vapor deposition method or a sputtering method.

  According to the TFET 100 and the method of manufacturing the same described above, the source region 130, the channel region 125, and the drain region 160 have a so-called lateral structure in which the source region 130, the channel region 125, and the drain region 160 are arranged side by side along the surface of the laminated semiconductor layer 120. It can be manufactured without causing

  In addition, the laminated semiconductor layer 120 includes the first layer 120 a and the second layer 120 b, and the band gap of the second semiconductor constituting the second layer 120 b is smaller than the band gap of the first semiconductor constituting the first layer 120 a. The on current can be increased without increasing the off current. That is, by introducing an ultrathin channel layer or quantum well structure having a high In composition as the second layer 120b, the band gap of only the region where tunneling occurs is shortened, and the band gap of the portion where tunneling current does not occur is kept high. be able to. As a result, it is possible to improve the on current without increasing the off current. Although the defect density generally increases when the In composition is increased, the defect density in the entire channel region can also be reduced since the defect density in the first layer 120a is sufficiently reduced.

Furthermore, the concentration of impurity atoms introduced into the source region 130 is set to 1 × 10 ¹⁹ cm ⁻³ or more, and the concentration gradient of the impurity atoms is set to 10 nm / dec. By setting it as the following, a steep impurity concentration gradient can be realized.

  Combining the above effects, it is possible to manufacture a channel region with a high tunneling probability, a source region with a low defect density, and a tunnel junction region with a steep impurity concentration gradient without causing a significant cost increase. Become.

Hereafter, TFET of Example 1, 2 and a comparative example was created, and the characteristic was compared. The TFET of the first embodiment is an example in which the stacked semiconductor layer 120 includes the first layer 120a, the second layer 120b, and the third layer 120c, and the In _0.7 Ga _0.3 As layer is formed as the second layer 120b. is there. The TFET according to the second embodiment is an example in which the stacked semiconductor layer 120 includes the first layer 120a, the second layer 120b, and the third layer 120c, and an InAs layer is formed as the second layer 120b. The TFET of the comparative example is an example in which the stacked semiconductor layer 120 does not have the second layer 120 b.

(Preparation of TFET of Example 1)
An In _0.53 Ga _0.47 As layer is used as the first layer 120 a of the stacked semiconductor layer 120, an In _0.7 Ga _0.3 As layer is used as the second layer 120 b, and an InP wafer is used as the substrate 105. As the layer 120c, an In _0.53 Ga _0.47 As layer was formed using the MOCVD method. The thicknesses of the first layer 120a, the second layer 120b, and the third layer 120c were 94 nm, 3 nm, and 3 nm, respectively. The growth temperature in the MOCVD method was 550 ° C., the reaction pressure was 10 kPa, the growth rate was 60 nm / min, and the V group gas / III group gas supply ratio was 100. Zn atoms were added to the formation region of the source region 130 by a spin-on-glass method, and an activation heat treatment was performed at 500 ° C. for 1 minute. An Al ₂ O ₃ layer was deposited to a thickness of 3.5 nm by the ALD method as the gate insulator 151 of the gate structure 150, and a Ta film was formed by the vapor deposition method as the metal gate electrode 155. A Ni film was formed as the drain region 160, and alloying treatment was performed on InGaAs. A Pt film was formed as a metal source electrode 135 and a metal drain electrode 165 by a vapor deposition method.

(Preparation of TFET of Example 2)
Using the InP wafer as a substrate 105, an _In 0.53 _{Ga 0.47} As layer as the first layer 120a of the multilayer semiconductor layer 120, an InAs layer as the second layer 120b, _{an In 0.53} Ga As third layer 120c _{A 0.47} As layer was formed using MOCVD. The thicknesses of the first layer 120a, the second layer 120b, and the third layer 120c were 94 nm, 3 nm, and 3 nm, respectively. The growth temperature in the MOCVD method was 550 ° C., the reaction pressure was 10 kPa, the growth rate was 60 nm / min, and the V group gas / III group gas supply ratio was 100. The source region 130, the gate insulator 151 and the metal gate electrode 155 of the gate structure 150, the drain region 160, the metal source electrode 135, and the metal drain electrode 165 are the same as in the first embodiment.

(Creating TFET of Comparative Example)
An InP wafer was used as the substrate 105, and an In _0.53 Ga _0.47 As layer was formed by MOCVD as a semiconductor corresponding to the stacked semiconductor layer 120. The thickness was 100 nm. The growth temperature in the MOCVD method was 550 ° C., the reaction pressure was 10 kPa, the growth rate was 60 nm / min, and the V group gas / III group gas supply ratio was 100. The source region 130, the gate insulator 151 and the metal gate electrode 155 of the gate structure 150, the drain region 160, the metal source electrode 135, and the metal drain electrode 165 are the same as in the first embodiment.

(Crystal evaluation of Example 1 and Example 2)
The laminated semiconductor layer 120 prepared in Example 1 and Example 2 was observed with a transmission electron microscope (TEM) to evaluate crystal defects. Further, the composition and thickness were measured by a known method.

The first layer _120a in Example _{1 (In 0.53 Ga 0.47 As)} , a second layer _{120b (In 0.7 Ga} 0.3 As) and the third layer _120c (In _{0.53 Ga 0.47} As The film thickness and In composition of (a) were as designed respectively. Further, in the TEM measurement, crystal defects in the first layer 120a, the second layer 120b, and the third layer 120c of Example 1 were not observed.

The first layer _120a in Example _{2 (In 0.53 Ga 0.47 As)} , the thickness and In composition of the second layer 120b (InAs) and a third layer _120c (In _{0.53 Ga 0.47} As) is Each was as designed. Further, in the TEM measurement, crystal defects in the first layer 120a, the second layer 120b, and the third layer 120c of Example 2 were not observed.

(Concentration gradient in source region of Example 1 and Example 2)
The concentration profile of Zn atoms in the source region 130 of Example 1 was measured by secondary ion mass spectrometry (SIMS). As a result, the absolute concentration of Zn atoms is 4 × 10 ¹⁹ cm ⁻³ , and the concentration gradient of Zn atoms in the direction perpendicular to the substrate 105 is 3.5 nm / dec. It was below. Similarly, the concentration profile of Zn atoms in the source region 130 of Example 2 was measured. As a result, the absolute concentration of Zn atoms is 4 × 10 ¹⁹ cm ⁻³ , and the concentration gradient of Zn atoms in the direction perpendicular to the substrate 105 is 3.5 nm / dec. It was below.

(Electrical Properties of TFETs of Example 1, Example 2 and Comparative Example)
The I _d -V _d characteristics and the I _d -V _g characteristics were measured in each of the TFETs manufactured in each of Example 1, Example 2 and Comparative Example. FIG. 4 shows the dependence of I _d on (V _g −V _th ). V _th is conveniently defined as V _g such that I _d is 1 × 10 ⁻¹¹ A / μm. FIG. S. _Shows the dependence of I _d on.

  In each of the TFETs of Example 1, Example 2 and Comparative Example, differential negative resistance was observed, and the operation of the TFET by tunneling was confirmed.

In TFET of Comparative _Example, V d = 50 _mV, the _{I d} in _{(V g -V th) = 1V} , a _{^{1.5 × 10 -7 A / μm,}} I d -V g curve, hysteresis characteristic is sufficiently It was confirmed to be small. S. S. The minimum value of is 64mV / dec. Met.

In TFET of embodiments _1, V d = 50 _mV, the _{I d} in _{(V g -V th) = 1V} , a _{^{1.9 × 10 -7 A / μm,}} I d -V g curve, hysteresis characteristic It was confirmed to be small enough. S. S. The minimum value of is 57 mV / dec. Met. All the S. current value _{I d} is in the range of 1 × ^{10 -13} ~1 × ^{10 -7} S. The value of was lower than that of the comparative example.

In TFET of Example _2, V d = 50 _mV, the _{I d} in _{(V g -V th) = 1V} , a _{^{8 × 10 -7 A / μm,}} I d -V g curve, hysteresis characteristic is sufficiently small That was confirmed. S. S. The minimum value of is 64mV / dec. Met. Also, all S. Within current value _{I d} is 2 × ^{10 -11} ~1 × ^{10 -7} S. The value of was lower than that of the comparative example.

  In Example 1 and Example 2, higher current value Id, lower S.O. S. We will consider the reason why we got

  First, in the comparative example, the example 1, and the example 2, only the In composition of the second material semiconductor 120b in the channel region 125 is changed, and the In composition and the film thickness of the first layer 120a and the third layer 120c. Is the same. From this, the so-called MOS interface between the channel region 125 and the gate insulator 151 is the same in the comparative example, the first embodiment, and the second embodiment. Therefore, the difference in the electrical characteristics of the TFET obtained in the experiment can be considered as the difference in the configuration of the channel region 125.

InGaAs has a characteristic that the band gap and the effective mass of electrons become smaller as the In composition becomes higher. The band gap Eg at room temperature in the In composition x of InGaAs is given by Eg = {0.36 + 0.63 (1-x) +0.43 (1-x) ² } eV. From this formula, the band gap of InGaAs of In composition 0.53 is 0.75 eV, the band gap of InGaAs of In composition 0.7 is 0.59 eV, and the band gap of InAs can be calculated to be 0.36 eV. On the other hand, the effective mass m _e at room temperature in the In composition x of InGaAs is given by m _e = {0.023 + 0.037 (1-x) +0.003 (1-x) ² } m ₀ . From this equation, the effective mass of InGaAs of In composition 0.53 is 0.041 m ₀ , the effective mass of InGaAs of In composition 0.7 is 0.034 m ₀ , and the effective mass of In As is 0.023 m ₀ . It can be calculated. Here, m ₀ is an electron rest mass.

  Therefore, as shown in the first embodiment or the second embodiment, by applying InGaAs or InAs having a high In composition of the second layer 120b, the band gap and the effective mass of electrons are reduced, and a channel region having a high tunneling probability is obtained. It can be considered that a high operating current is realized in the TFET.

  If the film thickness of the second layer 120 b is too thin, a large tunnel current density can not be obtained, and a sufficient effect is not exhibited. On the other hand, when the film thickness is too thick, off current and S.V. cause defects due to lattice relaxation of InGaAs or InAs having a high In composition and InGaAs having a lower In composition than that of the second layer 120b. S. Increase Therefore, in the first layer 120a other than the tunnel junction region 140, it is desirable that the In composition of InGaAs be low.

  Therefore, a multilayer structure constituted of the first layer 120a and the second layer 120b as shown in the first embodiment or the second embodiment is effective.

  Next, the third layer 120c will be described. The third layer 120 c is a material that serves to improve the quality of the channel region 125 and the gate structure 150. When InGaAs whose In composition is lower than that of the second layer 120b is used in the third layer 120c, the channel region 125 (the stacked semiconductor layer 120) has a so-called quantum well structure. In such a configuration, carriers are localized in the quantum well, and an improvement in tunneling current density can be expected. On the other hand, in the quantum well type configuration, when the film thickness of the second layer 120b is in the range of 1 to 20 nm, the effective band gap value is larger than that of the bulk semiconductor due to the quantum effect, so the tunneling probability is increased. Reduce. Therefore, it is necessary to determine the configuration of the first layer 120a, the second layer 120b and the third layer 120c in consideration of various influences.

  Although the embodiment has been described only in the case where the channel region 125 is made of InGaAs, configurations using other materials are also possible. The same effect can be expected by appropriately designing the first layer 120a and the second layer 120b even in a group III-V material or a group IV-IV material in which the channel region 125 is other than InGaAs.

  Specifically, as a combination of the first layer 120a / the second layer 120b in the channel region 125, InAlAs / InGaAs, InP / InGaAs, InP / InAs, GaSb / InSb, InGaSb / InSb, GaSb / InAs, InGaSb / InAs, AlAb / InAs, InGaN / InGaN, InGaN / InN, GaN / InN, Si / SiGe, SiGe / SiGe, SiGe / Ge, Ge / SnGe, SnGe / SnGe, SnGe / Sn, SiSn / SiSn, SiGeSn / Ge / Sn and These mixed crystal compounds are mentioned.

  Further, in Example 1 and Example 2, the current value Id higher than that of the comparative example, the lower S.V. S. We will consider another reason why we got

  The impurity concentration gradient of Zn to InGaAs is a phenomenon that is unique to InGaAs. Therefore, it is sufficiently considered that this impurity concentration gradient depends on the In composition. That is, in the case of a semiconductor material with a high In composition, the concentration gradient in the direction perpendicular to the substrate 105 of Zn impurity atoms in the source region 130 may be steeper than in the case where the In composition is low. In TFET, diffusion of impurity atoms is considered to be spatially equivalent in the vertical and horizontal directions, and concentration gradient of impurity in the tunnel junction region 140 forming the interface between the source region 130 and the channel region 125 in the horizontal direction to the substrate 105 is The concentration gradient of Zn impurity atoms in the source region 130 in the direction perpendicular to the substrate 105 may be considered to be the same. For this reason, in InGaAs with a high In composition, reduction of the tunnel distance of the tunnel junction region 140 and low leakage current due to low defects were realized.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing. Also, that the first layer is "above" the second layer means that the first layer is provided in contact with the upper surface of the second layer, and between the lower surface of the first layer and the upper surface of the second layer And the case where there are intervening layers. Further, the terms such as “upper” and “lower” indicate relative directions in the semiconductor substrate and the semiconductor device, and do not indicate absolute directions with respect to an external reference plane such as the ground.

  DESCRIPTION OF SYMBOLS 100 ... TFET, 105 ... board | substrate, 110 ... Buffer layer, 120 ... Layered semiconductor layer, 120a ... 1st layer, 120b ... 2nd layer, 120c ... 3rd layer, 125 ... Channel area, 130 ... Source area, 135 ... Metal Source electrode 140: Tunnel junction region 150: Gate structure 151: Gate insulator 155: Metal gate electrode 160: Drain region 165: Metal drain electrode

Claims (11)

A substrate,
A stacked semiconductor layer located on the substrate;
A source region exhibiting a first conductivity type formed in the laminated semiconductor layer;
A drain region formed in the stacked semiconductor layer and exhibiting a second conductivity type opposite to the first conductivity type;
A gate structure for applying an electric field to a channel region between the source region and the drain region;
A tunnel field effect transistor in which the source region, the channel region, and the drain region are positioned side by side in a direction along a surface of the laminated semiconductor layer,
The laminated semiconductor layer includes a first layer made of a first semiconductor, and a second layer made of a second semiconductor, which is located farther from the substrate than the first layer, and has a thickness of 1 to 3 nm.
A tunnel field effect transistor, wherein a band gap of the second semiconductor is smaller than a band gap of the first semiconductor. When the first conductivity type is n-type, the electron energy level at the top of the valence band of the second semiconductor is higher than that of the first semiconductor,
When the first conductivity type is p-type, the electron energy level at the lower end of the conduction band of the second semiconductor is lower than that of the first semiconductor.
The tunnel field effect transistor according to claim 1. The tunnel field effect transistor according to claim 1, wherein the first semiconductor and the second semiconductor are group III-V semiconductors. The first semiconductor is made of In _{x 1} Ga _{1-x 1} As,
The second semiconductor is made of In _{x 2} Ga _{1-x 2} As.
The tunnel field effect transistor according to claim 3, wherein an In composition x1 of the first semiconductor is smaller than an In composition x2 of the second semiconductor. The laminated semiconductor layer further includes a third layer made of a third semiconductor, which is located farther from the substrate than the second layer,
The tunnel field effect transistor according to any one of claims 1 to 4, wherein a band gap of the third semiconductor is different from a band gap of the second semiconductor. The tunnel field effect transistor according to claim 5, wherein the third semiconductor and the second semiconductor have different electron energy levels at the upper end of the valence band or the electron energy level at the lower end of the conduction band. The tunnel field effect transistor according to claim 5, wherein the first semiconductor, the second semiconductor, and the third semiconductor are group III-V semiconductors. The first semiconductor is made of In _{x 1} Ga _{1-x 1} As,
The second semiconductor is made of In _{x 2} Ga _{1-x 2} As.
The third semiconductor comprises In _x 3 Ga _{1-x 3} As,
The In composition x1 of the first semiconductor is smaller than the In composition x2 of the second semiconductor,
The tunnel field effect transistor according to claim 7, wherein an In composition x3 of the third semiconductor is different from an In composition x2 of the second semiconductor. The concentration of impurity atoms introduced into the source region is 1 × 10 ¹⁹ cm ⁻³ or more,
In the diffusion direction of the impurity atoms, the concentration gradient of the impurity atoms is 10 nm / dec. The tunnel field effect transistor according to any one of claims 1 to 8, which is as follows. A method of manufacturing a tunnel field effect transistor according to any one of claims 1 to 9, wherein
Forming the laminated semiconductor layer including the first layer and the second layer on the substrate by an epitaxial growth method;
Forming the source region in a part of the laminated semiconductor layer;
Forming an insulating layer on the laminated semiconductor layer;
Forming the gate structure on the insulating layer at a position adjacent to the source region in plan view of the source region;
Forming the drain region in a part of the laminated semiconductor layer at a position opposite to the source region and the source region sandwiching the gate structure when the source region and the gate structure are viewed in plan;
A method of manufacturing a tunnel field effect transistor. In the step of forming the source region, the source region is formed by thermally diffusing impurity atoms;
The method for manufacturing a tunnel field effect transistor according to claim 10, wherein an atom whose diffusion coefficient in a high concentration part exhibits a value higher than that of a low concentration part is used as the impurity atom.

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