CN208923144U - A kind of silicon germanium tin high electron mobility transistor - Google Patents
A kind of silicon germanium tin high electron mobility transistor Download PDFInfo
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- CN208923144U CN208923144U CN201821596246.XU CN201821596246U CN208923144U CN 208923144 U CN208923144 U CN 208923144U CN 201821596246 U CN201821596246 U CN 201821596246U CN 208923144 U CN208923144 U CN 208923144U
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- KAJBHOLJPAFYGK-UHFFFAOYSA-N [Sn].[Ge].[Si] Chemical compound [Sn].[Ge].[Si] KAJBHOLJPAFYGK-UHFFFAOYSA-N 0.000 title claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 51
- 229910005898 GeSn Inorganic materials 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 239000011435 rock Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 8
- 229910052738 indium Inorganic materials 0.000 claims description 16
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 16
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- URRHWTYOQNLUKY-UHFFFAOYSA-N [AlH3].[P] Chemical compound [AlH3].[P] URRHWTYOQNLUKY-UHFFFAOYSA-N 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- -1 aluminium arsenic Chemical compound 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 238000005516 engineering process Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application provides a kind of silicon germanium tin high electron mobility transistor, which includes: silicon-based substrate；Buffer layer in the silicon-based substrate；Channel layer on the buffer layer, the channel layer are germanium tin (GeSn) material；And the wall on the channel layer, barrier layer and cap rock, the wall, barrier layer and cap rock are III-V group semi-conductor material, wherein the interface of the wall and channel layer forms two-dimensional electron gas, and the buffer layer thickness is greater than 500nm.According to the present embodiment, the high speed performance of transistor can be improved, also, GeSn is easy to integrate with Si base ic manufacturing technology.
Description
Technical field
This application involves technical field of semiconductors more particularly to a kind of silicon germanium tin high electron mobility transistor.
Background technique
High speed that high electron mobility transistor (HEMT, High Electron Mobility Transistor) has,
The excellent properties such as high frequency, low noise are the mainstream microwave devices for realizing 5G communication, high frequency satellite communication.
It is high as the iii-v of representative using GaAs, indium phosphide as semiconductor application is constantly to microwave (high frequency) Duan Tuozhan
Transport factor material shows huge superiority, is able to satisfy high speed, the high frequency demand of information processing.
It should be noted that the above description of the technical background be intended merely to it is convenient to the technical solution of the application carry out it is clear,
Complete explanation, and facilitate the understanding of those skilled in the art and illustrate.Cannot merely because these schemes the application's
Background technology part is expounded and thinks that above-mentioned technical proposal is known to those skilled in the art.
Summary of the invention
In the prior art, III-V material manufacturing cost is all very high, and can cause environmental problem, and be difficult to
It is integrated with silicon (Si) base ic manufacturing technology.
The embodiment of the present application provides a kind of silicon germanium tin (GeSn) high electron mobility transistor and its manufacturing method, in silicon
It is formed on base substrate and high electron mobility transistor is prepared by germanium tin (GeSn) material, thereby, it is possible to improve the high speed of transistor
Performance, also, GeSn is easy to integrate with Si base ic manufacturing technology.
According to the one aspect of the embodiment of the present application, a kind of silicon germanium tin (GeSn) high electron mobility transistor is provided,
Include:
Silicon-based substrate；
Buffer layer in the silicon-based substrate；
Channel layer on the buffer layer, the channel layer are germanium tin (GeSn) material；And
Wall on the channel layer, barrier layer and cap rock, the wall, barrier layer and cap rock are III-V
Race's semiconductor material, wherein the interface of the wall and channel layer forms two-dimensional electron gas, and the buffer layer thickness is greater than
500nm。
According to the other side of the embodiment of the present application, wherein the material of the silicon-based substrate is on silicon or insulator
Silicon, the cushioning layer material are germanium or germanium silicon (SiGe).
According to the other side of the embodiment of the present application, wherein the material of the channel layer is Ge(1-x)Snx, wherein
0.06<x<0.3。
According to the other side of the embodiment of the present application, wherein the material of the wall, barrier layer and cap rock is indium aluminium
Phosphorus (InAlP), indium aluminium arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs).
According to the other side of the embodiment of the present application, wherein the wall is undoped, the barrier layer and the lid
Layer adulterates, also, the doping concentration of the cap rock is higher than the doping concentration of the barrier layer.
According to the other side of the embodiment of the present application, wherein the barrier layer is connect with gate electrode, the cap rock and source
Electrode is connected with drain electrode.
The beneficial effects of the present application are as follows: it is formed in silicon-based substrate and high electron mobility is prepared by germanium tin (GeSn) material
Transistor, thereby, it is possible to improve the high speed performance of transistor, also, GeSn is easy to integrate with Si base ic manufacturing technology.
Referring to following description and accompanying drawings, specific implementations of the present application are disclosed in detail, specify the original of the application
Reason can be in a manner of adopted.It should be understood that presently filed embodiment is not so limited in range.In appended power
In the range of the spirit and terms that benefit requires, presently filed embodiment includes many changes, modifications and is equal.
The feature for describing and/or showing for a kind of embodiment can be in a manner of same or similar one or more
It uses in a other embodiment, is combined with the feature in other embodiment, or the feature in substitution other embodiment.
It should be emphasized that term "comprises/comprising" refers to the presence of feature, one integral piece, step or component when using herein, but simultaneously
It is not excluded for the presence or additional of one or more other features, one integral piece, step or component.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is worked, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a schematic diagram of the silicon germanium tin high electron mobility transistor of the embodiment of the present application 1；
Fig. 2 is a schematic diagram of the manufacturing method of the silicon germanium tin high electron mobility transistor of the embodiment of the present application 2；
Fig. 3 (a)-Fig. 3 (d) is the corresponding device sectional view of each step in the embodiment of the present application 2.
Specific embodiment
Referring to attached drawing, by following specification, the aforementioned and other feature of the application be will be apparent.In specification
In attached drawing, specific implementations of the present application are specifically disclosed, which show wherein can be using the portion of the principle of the application
Divide embodiment, it will thus be appreciated that the application is not limited to described embodiment, on the contrary, the application includes falling into appended power
Whole modifications, modification and equivalent in the range of benefit requirement.
In the explanation of each embodiment of the application, for convenience of description, the direction for being parallel to the main surface of silicon-based substrate is claimed
For " transverse direction ", the direction that will be perpendicular to the main surface of silicon-based substrate is known as " longitudinal direction ".
Embodiment 1
The embodiment of the present application provides a kind of silicon germanium tin (GeSn) high electron mobility transistor.
Fig. 1 is a schematic diagram of silicon germanium tin (GeSn) high electron mobility transistor of the present embodiment, such as Fig. 1 institute
Show, which includes: silicon-based substrate 11；Buffer layer 12 in silicon-based substrate 11；Position
In the channel layer 13 on buffer layer 12, channel layer 13 is the preparation of germanium tin (GeSn) material；Wall 14 on channel layer 13,
Barrier layer 15 and cap rock 16, wherein wall 14, barrier layer 15 and cap rock 16 are III-V group semi-conductor material, and buffer layer 12 is thick
Degree is greater than 500nm.
In the present embodiment, wall 14 and channel layer 13 form III-V/GeSn hetero-junctions, and in the III-V/GeSn
Conduction band band rank is formed in hetero-junctions, and III- is controlled by the Schottky barrier under gate electrode 17 to generate two-dimensional electron gas
Two-dimensional electron gas in V/GeSn hetero-junctions, to realize the control of electric current.Since there is GeSn material high electronics to move
Shifting rate, and two-dimensional electron gas is spatially separated with the impurity center that is in III-V layers, and not by ionized impurity scattering
Influence, it is possible to realize high mobility.
According to the present embodiment, is formed in silicon-based substrate and high electron mobility transistor is prepared by germanium tin (GeSn) material,
Thereby, it is possible to improve the high speed performance of transistor, also, GeSn is easy to integrate with Si base ic manufacturing technology.And existing
Have in technology, there are no the technical solutions about GeSn high electron mobility transistor, more without silicon substrate GeSn high electron mobility
The relevant report of rate transistor.
In the present embodiment, the material of silicon-based substrate 11 is the silicon (SOI) on silicon (Si) or insulator.The silicon-based substrate 11
Surface be, for example, (111) crystal face.
In the present embodiment, the material of buffer layer 12 is germanium (Ge) or germanium silicon (SiGe).The buffer layer 12 can buffer
Mismatch between the lattice on the surface of silicon-based substrate 11 and the lattice of channel layer 13, to improve the quality of channel layer 13.
In the present embodiment, germanium tin (GeSn) material of channel layer 13 can be expressed as Ge(1-x)Snx, wherein 0.06 < x <
0.3。
The band structure of germanium tin (GeSn) is adjusted with Sn component, and when Sn component is greater than 6%, GeSn will be realized indirectly
Band gap material is to the transformation of direct band gap material, also, when GeSn becomes direct band gap material, electron mobility is much larger than
Si and Ge material.
Therefore, in the present embodiment, the component of Sn in germanium tin (GeSn) material of channel layer 13 is controlled and is arrived 6%
30%, germanium tin (GeSn) material of channel layer 13 can be made to become direct band gap material, so that the electronics improved in channel layer moves
Shifting rate.
In the present embodiment, the III-V material of wall 14, barrier layer 15 and cap rock 16 can be the germanium with channel layer 13
The Lattice Matching of tin (GeSn) material or the material of approximate match, wherein by adjusting the component of each element in III-V material,
It can make III-V material lattice constant and GeSn material lattice is matched or approximate match.The III-V material for example can be with
It is indium aluminium phosphorus (InAlP), indium aluminium arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs).In addition it is also possible to be
Other III-V group materials.
In the present embodiment, wall 14 is undoped, to avoid the movement of two-dimensional electron gas by the scattering of impurity
It influences.
In the present embodiment, barrier layer 15 is connect with gate electrode 17, and cap rock 16 is connect with source electrode 18 and drain electrode 19.
In the present embodiment, barrier layer 15 and cap rock 16 adulterate, consequently facilitating with gate electrode, source electrode, drain electrode shape
At contact.In addition, in the present embodiment, the doping concentration of cap rock 16 can be higher than the doping concentration of barrier layer 15.
According to the present embodiment, is formed in silicon-based substrate and high electron mobility transistor is prepared by germanium tin (GeSn) material,
It is easy and Si base IC manufacturing skill thereby, it is possible to improve the high speed performance of transistor, also, as the GeSn of four race's materials
Art is integrated.
Embodiment 2
Embodiment 2 provides a kind of manufacturing method of silicon germanium tin high electron mobility transistor, for manufacturing 1 institute of embodiment
The silicon germanium tin high electron mobility transistor stated.
Fig. 2 is a schematic diagram of the manufacturing method of the silicon germanium tin high electron mobility transistor of the present embodiment, such as Fig. 2
Shown, in the present embodiment, which may include:
Step 201 forms buffer layer in silicon-based substrate；
Step 202 forms channel layer on the buffer layer, and the channel layer is germanium tin (GeSn) material；And
Step 203 forms wall, barrier layer and cap rock, the wall, barrier layer and cap rock on the channel layer
For III-V group semi-conductor material, wherein the interface of the wall and channel layer is formed with two-dimensional electron gas,
Step 204, the etching cap rock, to expose the barrier layer；
Step 205 forms gate electrode on the barrier layer of exposing；
Step 206 is respectively formed source electrode and drain electrode on the cap rock of the gate electrode two sides.
In the present embodiment, the material of the silicon-based substrate is the silicon on silicon or insulator, the cushioning layer material be germanium or
Germanium silicon (SiGe).
In the present embodiment, the material of channel layer is Ge (1-x) Snx, wherein 0.06 < x < 0.3.
In the present embodiment, the material of wall, barrier layer and cap rock be indium aluminium phosphorus (InAlP), indium aluminium arsenic (InAlAs),
Indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs).Wherein, the wall is undoped, and the barrier layer and the cap rock adulterate, and
And the doping concentration of the cap rock is higher than the doping concentration of the barrier layer.
In the following, illustrating the manufacture of the silicon germanium tin high electron mobility transistor of the application in conjunction with a specific example
Method.
Fig. 3 is the corresponding device sectional view of each step in the example, as shown in figure 3, in this example, silicon germanium tin
(GeSn) manufacturing method of high electron mobility transistor includes the following steps:
Step 1: as shown in Fig. 3 (a), 11 surface of Si substrate after cleaning, using two step chemical gaseous phase of low temperature and high temperature
Deposition method, successively epitaxial growth Ge buffer layer 12 and GeSn channel layer 13, wherein 12 thickness of Ge buffer layer > 500nm, GeSn
Sn group is divided into 10%, GeSn channel layer, 13 thickness > 300nm in channel layer 13, wherein GeSn channel layer 13 undopes.
Step 2: as shown in Fig. 3 (b), epitaxial growth eigen I n1-yAlyAs wall 14, y=0.72, thickness~2nm；Outside
Prolong growing n-type In1-yAlyAs barrier layer 15, y=0.72, thickness about 30nm, doping concentration 1*1018cm-3；Epitaxial growth heavy doping
N-shaped In1-yAlyAs cap rock 16, y=0.72, thickness about 50nm, doping concentration 1*1019cm-3。
Step 3: as shown in Fig. 3 (c), defining source and drain areas in cap rock 16 using photoetching and reactive ion etching technology
16a；In the barrier layer 15 exposed between source and drain areas 16a, area of grid is defined by photoetching and etching；Deposit gate electrode material
Material, and gate electrode 17 is prepared by chemical wet etching.
Step 4: as shown in Fig. 3 (d), deposit source-drain electrode electrode material, and by chemical wet etching prepare source-drain electrode electrode 18,
19, complete device preparation.
According to the present embodiment, is formed in silicon-based substrate and high electron mobility transistor is prepared by germanium tin (GeSn) material,
It is easy and Si base IC manufacturing skill thereby, it is possible to improve the high speed performance of transistor, also, as the GeSn of four race's materials
Art is integrated.
Combine specific embodiment that the application is described above, it will be appreciated by those skilled in the art that this
A little descriptions are all exemplary, and are not the limitation to the application protection scope.Those skilled in the art can be according to the application
Spirit and principle various variants and modifications are made to the application, these variants and modifications are also within the scope of application.
Claims (6)
1. a kind of silicon germanium tin (GeSn) high electron mobility transistor, which is characterized in that the high electricity of the silicon germanium tin (GeSn)
Transport factor transistor includes:
Silicon-based substrate；
Buffer layer in the silicon-based substrate；
Channel layer on the buffer layer, the channel layer are germanium tin (GeSn) material；And
Wall on the channel layer, barrier layer and cap rock, the wall, barrier layer and cap rock are iii-v half
Conductor material,
Wherein,
The interface of the wall and channel layer forms two-dimensional electron gas,
The buffer layer thickness is greater than 500nm.
2. silicon germanium tin (GeSn) high electron mobility transistor as described in claim 1, which is characterized in that
The material of the silicon-based substrate is the silicon on silicon or insulator,
The cushioning layer material is germanium or germanium silicon (SiGe).
3. silicon germanium tin (GeSn) high electron mobility transistor as described in claim 1, which is characterized in that
The material of the channel layer is Ge(1-x)Snx, wherein 0.06 < x < 0.3.
4. silicon germanium tin (GeSn) high electron mobility transistor as described in claim 1, which is characterized in that
The material of the wall, barrier layer and cap rock is indium aluminium phosphorus (InAlP), indium aluminium arsenic (InAlAs), indium gallium phosphorus (InGaP)
Or indium gallium arsenic (InGaAs).
5. silicon germanium tin (GeSn) high electron mobility transistor as described in claim 1, which is characterized in that
The wall is undoped, and the barrier layer and the cap rock adulterate, also, the doping concentration of the cap rock is higher than institute
State the doping concentration of barrier layer.
6. silicon germanium tin (GeSn) high electron mobility transistor as described in claim 1, which is characterized in that the barrier layer
It is connect with gate electrode,
The cap rock is connect with source electrode and drain electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821596246.XU CN208923144U (en) | 2018-09-27 | 2018-09-27 | A kind of silicon germanium tin high electron mobility transistor |
| PCT/CN2019/070518 WO2020062706A1 (en) | 2018-09-27 | 2019-01-05 | Silicon-based germanium-tin transistor with high electron mobility |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821596246.XU CN208923144U (en) | 2018-09-27 | 2018-09-27 | A kind of silicon germanium tin high electron mobility transistor |
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| CN208923144U true CN208923144U (en) | 2019-05-31 |
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| CN100511706C (en) * | 2007-09-29 | 2009-07-08 | 西安电子科技大学 | GaN device based on component-gradient GaN MISFET and preparing method thereof |
| KR101890749B1 (en) * | 2011-10-27 | 2018-08-23 | 삼성전자주식회사 | Electrode structure, gallium nitride based semiconductor device including the same and methods of manufacturing the same |
| CN103594506B (en) * | 2012-08-16 | 2017-03-08 | 中国科学院微电子研究所 | Semiconductor device |
| CN103311306A (en) * | 2013-06-26 | 2013-09-18 | 重庆大学 | GeSn channel metal-oxide-semiconductor field-effect transistor with InAlP cover layer |
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Effective date of registration: 20221111 Address after: 201800 Building 1, No. 235, Chengbei Road, Jiading District, Shanghai Patentee after: Shanghai Industrial UTechnology Research Institute Address before: 201800 Building 2, No. 235, Chengbei Road, Jiading District, Shanghai Patentee before: SHANGHAI INTERNATIONAL MICRO-TECH AFFILIATION CENTER |