CN110957360A - Silicon-based germanium-tin high-electron-mobility transistor and manufacturing method thereof - Google Patents
Silicon-based germanium-tin high-electron-mobility transistor and manufacturing method thereof Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 239000010703 silicon Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910005898 GeSn Inorganic materials 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 52
- 230000004888 barrier function Effects 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims description 17
- KAJBHOLJPAFYGK-UHFFFAOYSA-N [Sn].[Ge].[Si] Chemical compound [Sn].[Ge].[Si] KAJBHOLJPAFYGK-UHFFFAOYSA-N 0.000 claims description 16
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 229910052738 indium Inorganic materials 0.000 claims description 10
- -1 indium aluminum phosphorus Chemical compound 0.000 claims description 10
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The application provides a silicon-based germanium tin high electron mobility transistor and a manufacturing method thereof, and the silicon-based germanium tin high electron mobility transistor comprises: a silicon-based substrate; the buffer layer is positioned on the silicon-based substrate; the channel layer is positioned on the buffer layer and made of germanium tin (GeSn) materials; and the spacing layer, the barrier layer and the cover layer are made of III-V semiconductor materials, wherein two-dimensional electron gas is formed on the interface of the spacing layer and the channel layer, the barrier layer is connected with the gate electrode, and the cover layer is connected with the source electrode and the drain electrode. According to the present embodiment, high-speed performance of the transistor can be improved, and GeSn is easily integrated with a Si-based integrated circuit manufacturing technology.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a silicon-based germanium tin high electron mobility transistor and a manufacturing method thereof.
Background
A High Electron Mobility Transistor (HEMT) has excellent performance such as High speed, High frequency, and low noise, and is a mainstream microwave device for realizing 5G communication and High frequency satellite communication.
With the continuous expansion of semiconductor application to the microwave (high frequency) range, III-V group high mobility semiconductor materials represented by gallium arsenide and indium phosphide have great superiority and can meet the requirements of high speed and high frequency of information processing.
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present application.
Disclosure of Invention
In the prior art, group III-V materials are very costly to manufacture, cause environmental problems, and are difficult to integrate with silicon (Si) -based integrated circuit fabrication techniques.
The embodiment of the application provides a silicon-based germanium tin (GeSn) high electron mobility transistor and a manufacturing method thereof, wherein the high electron mobility transistor is prepared by germanium tin (GeSn) materials on a silicon-based substrate, so that the high-speed performance of the transistor can be improved, and GeSn is easily integrated with a Si-based integrated circuit manufacturing technology.
According to an aspect of an embodiment of the present application, there is provided a silicon germanium tin (GeSn) high electron mobility transistor, including:
a silicon-based substrate;
the buffer layer is positioned on the silicon-based substrate;
the channel layer is positioned on the buffer layer and made of germanium tin (GeSn) materials; and
the spacer layer, the barrier layer and the cover layer are made of III-V semiconductor materials, two-dimensional electron gas is formed on the interface of the spacer layer and the channel layer, the barrier layer is connected with the gate electrode, and the cover layer is connected with the source electrode and the drain electrode.
According to another aspect of the embodiments of the present application, the material of the silicon-based substrate is silicon or silicon on insulator, and the material of the buffer layer is germanium or silicon germanium (SiGe).
According to another aspect of the embodiments of the present application, wherein the material of the channel layer is Ge(1-x)SnxWherein, 0.06<x<0.3。
According to another aspect of the embodiments of the present application, wherein the material of the spacer layer, the barrier layer and the cap layer is indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs).
According to another aspect of an embodiment of the present application, wherein the spacer layer is undoped, the barrier layer and the cap layer are both doped, and a doping concentration of the cap layer is higher than a doping concentration of the barrier layer.
According to another aspect of the embodiments of the present application, there is provided a method of manufacturing a silicon germanium tin (GeSn) high electron mobility transistor, including:
forming a buffer layer on a silicon-based substrate;
forming a channel layer on the buffer layer, wherein the channel layer is made of germanium tin (GeSn) material;
forming a spacing layer, a barrier layer and a cover layer on the channel layer, wherein the spacing layer, the barrier layer and the cover layer are made of III-V semiconductor materials, two-dimensional electron gas is formed at the interface of the spacing layer and the channel layer,
etching the cover layer to expose the barrier layer;
forming a gate electrode on the exposed barrier layer; and
and respectively forming a source electrode and a drain electrode on the cover layers at two sides of the gate electrode.
The beneficial effect of this application lies in: high electron mobility transistors made of germanium tin (GeSn) materials are formed on silicon-based substrates, whereby high speed performance of the transistors can be improved, and GeSn is easily integrated with Si-based integrated circuit fabrication techniques.
Specific embodiments of the present application are disclosed in detail with reference to the following description and drawings, indicating the manner in which the principles of the application may be employed. It should be understood that the embodiments of the present application are not so limited in scope. The embodiments of the application include many variations, modifications and equivalents within the spirit and scope of the appended claims.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.
It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a sige-sn-based hemt of embodiment 1 of the present application;
fig. 2 is a schematic diagram of a method for manufacturing a sige-sn-based hemt according to embodiment 2 of the present application;
fig. 3(a) -3 (d) are cross-sectional views of devices corresponding to the steps in example 2 of the present application.
Detailed Description
The foregoing and other features of the present application will become apparent from the following description, taken in conjunction with the accompanying drawings. In the description and drawings, particular embodiments of the application are disclosed in detail as being indicative of some of the embodiments in which the principles of the application may be employed, it being understood that the application is not limited to the described embodiments, but, on the contrary, is intended to cover all modifications, variations, and equivalents falling within the scope of the appended claims.
In the description of the embodiments of the present application, a direction parallel to the main surface of the silicon-based substrate is referred to as "lateral direction" and a direction perpendicular to the main surface of the silicon-based substrate is referred to as "longitudinal direction" for the convenience of description.
Example 1
The embodiment of the application provides a silicon germanium tin (GeSn) high-electron-mobility transistor.
Fig. 1 is a schematic diagram of a silicon germanium tin (GeSn) hemt according to the present embodiment, where, as shown in fig. 1, the silicon germanium tin hemt 1 includes: a silicon-based substrate 11; a buffer layer 12 on the silicon-based substrate 11; the channel layer 13 is positioned on the buffer layer, and the channel layer 13 is made of germanium tin (GeSn) material; a spacer layer 14, a barrier layer 15, and a cap layer 16 on the channel layer 13, wherein the spacer layer 14, the barrier layer 15, and the cap layer 16 are III-V semiconductor materials.
In this embodiment, the barrier layer 15 is connected to the gate electrode 17, and the cap layer 16 is connected to the source electrode 18 and the drain electrode 19.
In the present embodiment, the spacer layer 14 forms a III-V/GeSn heterojunction with the channel layer 13, and a conduction band step is formed in the III-V/GeSn heterojunction, thereby generating a two-dimensional electron gas, and the concentration of the two-dimensional electron gas in the III-V/GeSn heterojunction is controlled by a Schottky barrier under the gate electrode 17, thereby realizing the control of the current. Since GeSn materials have high electron mobility, and the two-dimensional electron gas is spatially separated from the impurity centers in the III-V layer and is not affected by scattering of ionized impurities, high mobility can be achieved.
According to the present embodiment, a high electron mobility transistor made of germanium tin (GeSn) material is formed on a silicon-based substrate, whereby high speed performance of the transistor can be improved, and GeSn is easily integrated with a Si-based integrated circuit manufacturing technology. However, in the prior art, no technical scheme about GeSn high electron mobility transistors exists, and no reports about silicon-based GeSn high electron mobility transistors exist.
In the present embodiment, the material of the silicon-based substrate 11 is silicon (Si) or Silicon On Insulator (SOI). The surface of the silicon-based substrate 11 is, for example, a (111) crystal plane.
In the present embodiment, the material of the buffer layer 12 is germanium (Ge) or silicon germanium (SiGe). The buffer layer 12 can buffer a mismatch between a lattice of the surface of the silicon-based substrate 11 and a lattice of the channel layer 13, thereby improving the quality of the channel layer 13.
In the present embodiment, the germanium tin (GeSn) material of the channel layer 13 may be represented as Ge(1-x)SnxWherein, 0.06<x<0.3。
The band structure of germanium tin (GeSn) is adjusted with the Sn composition, when the Sn composition is greater than 6%, GeSn will realize the conversion of an indirect bandgap material to a direct bandgap material, and when GeSn becomes a direct bandgap material, its electron mobility is much greater than that of Si and Ge materials.
Therefore, in the present embodiment, controlling the composition of Sn in the germanium tin (GeSn) material of the channel layer 13 to 6% to 30% enables the germanium tin (GeSn) material of the channel layer 13 to be a direct bandgap material, thereby improving electron mobility in the channel layer.
In this embodiment, the III-V materials of the spacer layer 14, the barrier layer 15, and the cap layer 16 may be lattice matched or approximately matched to the germanium-tin (GeSn) material of the channel layer 13, wherein the III-V material lattice constant may be lattice matched or approximately matched to the GeSn material by adjusting the composition of each element in the III-V material. The III-V material may be, for example, indium aluminum phosphorous (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorous (InGaP), or indium gallium arsenic (InGaAs). Other group III-V materials are also possible.
In this embodiment, the spacer layer 14 is undoped, thereby preventing the movement of the two-dimensional electron gas from being affected by scattering of impurities.
In this embodiment, the barrier layer 15 and the cap layer 16 are doped to facilitate contact with the gate electrode, the source electrode, and the drain electrode. In addition, in the present embodiment, the doping concentration of the cap layer 16 may be higher than that of the barrier layer 15.
According to the present embodiment, a high electron mobility transistor made of germanium tin (GeSn) material is formed on a silicon-based substrate, whereby high-speed performance of the transistor can be improved, and GeSn, which is a group iv material, is easily integrated with a Si-based integrated circuit manufacturing technology.
Example 2
Embodiment 2 provides a method for manufacturing a silicon-based germanium tin high electron mobility transistor, which is used for manufacturing the silicon-based germanium tin high electron mobility transistor described in embodiment 1.
Fig. 2 is a schematic diagram of a method for manufacturing a sige-sn-based hemt of this embodiment, as shown in fig. 2, in this embodiment, the method may include:
and 206, respectively forming a source electrode and a drain electrode on the cover layers on two sides of the gate electrode.
In this embodiment, the material of the si-based substrate is si or si on insulator, and the material of the buffer layer is ge or silicon germanium (SiGe).
In the present embodiment, the material of the channel layer is Ge (1-x) Snx, where 0.06< x < 0.3.
In this embodiment, the spacer layer, the barrier layer and the cap layer are made of indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs). The spacer layer is undoped, the barrier layer and the cap layer are doped, and the doping concentration of the cap layer is higher than that of the barrier layer.
The following describes a method for manufacturing a silicon germanium tin germanium high electron mobility transistor according to the present application with reference to a specific example.
Fig. 3 is a cross-sectional view of the device corresponding to the steps in this example, as shown in fig. 3, in this example, the method for manufacturing a silicon germanium tin (GeSn) -based high electron mobility transistor includes the following steps:
step 1: as shown in fig. 3(a), on the surface of the cleaned Si substrate 11, a Ge buffer layer 12 and a GeSn channel layer 13 are sequentially epitaxially grown by a low-temperature and high-temperature two-step chemical vapor deposition method, wherein the thickness of the Ge buffer layer 12 is greater than 500nm, the Sn component in the GeSn channel layer 13 is 10%, the thickness of the GeSn channel layer 13 is greater than 300nm, and the GeSn channel layer 13 is undoped.
Step 2: as shown In FIG. 3(b), intrinsic In is epitaxially grown1-yAlyAn As spacer layer 14, y 0.72, thickness 2 nm; epitaxially grown n-type In1-yAlyAs barrier layer 15, y 0.72, thickness about 30nm, doping concentration 1 x 1018cm-3(ii) a Epitaxially growing heavily doped n-type In1-yAlyAs cap layer 16, y 0.72, thickness about 50nm, doping concentration 1 x 1019cm-3。
And step 3: as shown in fig. 3(c), a source/drain region 16a is defined in the cap layer 16 by photolithography and reactive ion etching; defining a gate region in the barrier layer 15 exposed between the source and drain regions 16a by photolithography and etching; a gate electrode material is deposited and a gate electrode 17 is prepared by photolithographic etching.
And 4, step 4: as shown in fig. 3(d), a source/drain electrode material is deposited, and source/ drain electrodes 18 and 19 are prepared by photolithography and etching, thereby completing the device fabrication.
According to the present embodiment, a high electron mobility transistor made of germanium tin (GeSn) material is formed on a silicon-based substrate, whereby high-speed performance of the transistor can be improved, and GeSn, which is a group iv material, is easily integrated with a Si-based integrated circuit manufacturing technology.
The present application has been described in conjunction with specific embodiments, but it should be understood by those skilled in the art that these descriptions are intended to be illustrative, and not limiting. Various modifications and adaptations of the present application may occur to those skilled in the art based on the spirit and principles of the application and are within the scope of the application.
Claims (10)
1. A silicon germanium tin (GeSn) high electron mobility transistor, comprising:
a silicon-based substrate;
the buffer layer is positioned on the silicon-based substrate;
the channel layer is positioned on the buffer layer and made of germanium tin (GeSn) materials; and
a spacer layer, a barrier layer and a cap layer on the channel layer, the spacer layer, barrier layer and cap layer being III-V semiconductor material,
wherein,
the interface of the spacer layer and the channel layer forms a two-dimensional electron gas,
the barrier layer is connected to the gate electrode,
the cap layer is connected to the source electrode and the drain electrode.
2. The silicon germanium tin (GeSn) high electron mobility transistor of claim 1, wherein,
the silicon-based substrate is made of silicon or silicon on insulator,
the buffer layer is made of germanium or silicon germanium (SiGe).
3. The silicon germanium tin (GeSn) high electron mobility transistor of claim 1, wherein,
the material of the channel layer is Ge(1-x)SnxWherein, 0.06<x<0.3。
4. The silicon germanium tin (GeSn) high electron mobility transistor of claim 1, wherein,
the materials of the spacing layer, the barrier layer and the cover layer are indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs).
5. The silicon germanium tin (GeSn) high electron mobility transistor of claim 1, wherein,
the spacer layer is undoped, the barrier layer and the cap layer are both doped, and the cap layer has a doping concentration higher than the barrier layer.
6. A method of fabricating a silicon germanium tin (GeSn) high electron mobility transistor, comprising:
forming a buffer layer on a silicon-based substrate;
forming a channel layer on the buffer layer, wherein the channel layer is made of germanium tin (GeSn) material;
forming a spacing layer, a barrier layer and a cover layer on the channel layer, wherein the spacing layer, the barrier layer and the cover layer are made of III-V semiconductor materials, two-dimensional electron gas is formed at the interface of the spacing layer and the channel layer,
etching the cover layer to expose the barrier layer;
forming a gate electrode on the exposed barrier layer; and
and respectively forming a source electrode and a drain electrode on the cover layers at two sides of the gate electrode.
7. The method of manufacturing a silicon germanium tin (GeSn) high electron mobility transistor according to claim 6, wherein,
the silicon-based substrate is made of silicon or silicon on insulator,
the buffer layer is made of germanium or silicon germanium (SiGe).
8. The method of manufacturing a silicon germanium tin (GeSn) high electron mobility transistor according to claim 6, wherein,
the material of the channel layer is Ge (1-x) Snx, wherein x is more than 0.06< x < 0.3.
9. The method of manufacturing a silicon germanium tin (GeSn) high electron mobility transistor according to claim 6, wherein,
the materials of the spacing layer, the barrier layer and the cover layer are indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenic (InGaAs).
10. The method of manufacturing a silicon germanium tin (GeSn) high electron mobility transistor according to claim 6, wherein,
the spacer layer is undoped, the barrier layer and the cap layer are both doped, and the cap layer has a doping concentration higher than the barrier layer.
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