US20140197376A1 - Semiconductor Device - Google Patents
Semiconductor Device Download PDFInfo
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- US20140197376A1 US20140197376A1 US13/812,504 US201213812504A US2014197376A1 US 20140197376 A1 US20140197376 A1 US 20140197376A1 US 201213812504 A US201213812504 A US 201213812504A US 2014197376 A1 US2014197376 A1 US 2014197376A1
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 24
- 239000000956 alloy Substances 0.000 claims abstract description 24
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910005898 GeSn Inorganic materials 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 17
- 239000000969 carrier Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 123
- 238000000151 deposition Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 8
- 238000001451 molecular beam epitaxy Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000009413 insulation Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910002058 ternary alloy Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 229910015846 BaxSr1-xTiO3 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910020696 PbZrxTi1−xO3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- -1 SiN Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66409—Unipolar field-effect transistors
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Definitions
- the present invention relates to the field of manufacturing of a semiconductor integrated circuit, in particular to a field effect transistor having a GeSn quantum well.
- each of the key parameters e.g. the threshold voltage of the device is reduced accordingly, and such advantages as reduced power consumption and increased integration promote the improvement of the overall performance of the device.
- the driving capability of the device is restricted by the conventional silicon material technology, wherein the carrier mobility is low, thus the driving capability of the device is comparatively insufficient to be used in high-speed and high-frequency application fields. Therefore, high mobility devices, especially high mobility transistors (HEMT) will be extensively used in the future.
- HEMT high mobility transistors
- a kind of existing high mobility field effect transistor is AlGaAs/GaAs-based, which comprises, for example, a GaAs substrate, an intrinsic GaAs layer formed on the GaAs substrate (used as a buffer layer and/or a lower cap layer), an intrinsic AlxGal-xAs layer formed on the intrinsic GaAs layer (used as a potential well layer, an active layer and a control layer), an n-doped AlxGal-xAs layer formed on the intrinsic AlxGal-xAs layer (used as an upper cap layer), a gate stack formed on the upper cap layer and source and drain (contact) regions at both sides of the gate stack.
- FET high mobility field effect transistor
- an object of the present invention is to provide a field effect transistor having a GeSn quantum well so as to greatly increase the carrier mobility while simplifying the process and reducing the cost.
- a semiconductor device which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy.
- the concentration of Ge in the buffer layer and/or the barrier layer and/or the inversely doped isolation layer is greater than 50%.
- the concentration of Sn in the buffer layer and/or the barrier layer and/or the inversely doped isolation layer is less than 25%.
- the thickness of the buffer layer is 100 nm-2 ⁇ m.
- the concentration of Sn in the channel layer is greater than 1% and less than 25%.
- the thickness of the channel layer is 5 nm-200 nm.
- a cap layer formed of SiGe alloy is disposed between the channel layer and the gate stack structure.
- the source and drain regions are formed of SiGeSn alloy.
- the source and drain regions have a first conductivity type
- the inversely doped isolation layer, the barrier layer and the channel region have a second conductivity type opposite to the first conductivity type
- the forbidden-band width of the material of the barrier layer is greater than the band gap width of material of the channel layer.
- the semiconductor device uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
- FIG. 1 is a sectional view of the semiconductor device according to an embodiment of the present invention.
- FIG. 1 is a sectional view of the semiconductor device according to an embodiment of the present invention.
- a substrate 1 is provided, which can be formed of (bulk) Si (e.g. monocrystalline Si wafer), SOI, and GeOI (Ge on Insulator).
- the substrate 1 is formed of bulk Si or SOI so as to be compatible with the CMOS process.
- a buffer layer 2 is formed on substrate 1 by a deposition method such as PECVD, MOCVD, MBE and ALD so as to reduce the lattice mis-match between the substrate 1 and the upper GeSn channel layer.
- the lattice constant of the material of the buffer layer 2 is between the Si/Ge of substrate 1 and the upper layer GeSn, which is preferably a SiGe alloy, and specifically it can be Sil-xGex, with the concentration (atomic number percentage) x of Ge being greater than 50%, i.e. x>0.5.
- the thickness of the buffer layer 2 is, for example, about 100 nm-2 ⁇ m.
- the buffer layer 2 can also be a SiGeSn ternary alloy, such as Sil-u-vGeuSnv, wherein the concentration u of Ge is greater than 50% and is preferably between 60%-70%, i.e. 0.6 ⁇ u ⁇ 0.7, and the concentration v of Sn is less than 25% and is preferably between 1%-10%, i.e. 0.01 ⁇ v ⁇ 0.1.
- SiGeSn ternary alloy such as Sil-u-vGeuSnv
- An inversely doped isolation layer 3 is formed on the buffer layer 2 by a deposition method such as PECVD, MOCVD, MBE and ALD, whose conductivity type is the same as that of the buffer layer 2 and/or the later formed barrier layer 4 but different from that of the later formed source and drain regions 8 (having a first conductivity type, e.g. n or p), for example, the inversely doped isolation layer 3 has a second conductivity type (p or n) for adjusting and controlling potential barrier and threshold voltage by doping.
- the material of the inversely doped isolation layer 3 can be a SiGe alloy, specifically Sil-yGey, wherein a concentration (atomic number percentage) y of Ge is between 55%-75%, i.e.
- the thickness of the inversely doped isolation layer 3 is, for example, about 50 nm-500 nm. In-situ doping may be performed in the process of forming the inversely doped isolation layer 3 , or an implantation doping may be performed after forming the inversely doped isolation layer 3 , and the dopants include, for example, B, P, N, Al, Ga, etc. for adjusting the conductivity type.
- a barrier layer 4 is formed on the inversely doped isolation layer 3 by a deposition method such as PECVD, MOCVD, MBE and ALD, which is used for restricting the two-dimensional electron gas serving as carriers within the channel layer thereon.
- the material of the barrier layer 4 can be a SiGe alloy, specifically Sil-yGey, wherein the concentration (atomic number percentage) y of Ge is greater than 50% and preferably between 55%-75%, i.e. 0.55 ⁇ y ⁇ 0.75.
- the thickness of the barrier layer is, for example, about 50 nm-500 nm.
- the barrier layer 4 may also be the above-mentioned SiGeSn ternary alloy.
- the barrier layer 4 has a second conductivity type and a low doping concentration, i.e. it is of a p- or n-type. Particularly, the forbidden-band width E2 of the material of the barrier layer 4 is greater than the band gap width E1 of the material of the later formed channel layer 5 .
- a quantum well 5 is formed on the barrier layer 4 by deposition, so that it serves as the channel layer of the device.
- the material of the quantum well 5 is a GeSn alloy, specifically Gel-zSnz, wherein the concentration (atomic number percentage) z of Sn is between 1%-25%, i.e. 0.01 ⁇ z ⁇ 0.25.
- the thickness of the quantum well is, for example, about 5 nm-200 nm.
- the GeSn-based quantum well layer can be formed by conventional methods like MBE, MOCVD and ALD, or it can be formed by depositing an amorphous Ge layer and a metal Sn layer sequentially and making them react to each other by performing a laser fast annealing.
- a cap layer 6 is formed on the quantum well layer 5 by deposition method such as PECVD, MOCVD, MBE and ALD, which is used for restricting the two-dimensional electron gas serving as the carriers within the channel layer 5 thereunder.
- the material of the cap layer 6 can be a SiGe alloy, specifically Sil-wGew, wherein the concentration (atom number percentage) w of Ge is greater than 50% and preferably between 60%-85%, i.e. 0.60 ⁇ w ⁇ 0.85.
- the thickness of the cap layer 6 is, for example, 100 nm-500 nm.
- a gate stack structure 7 is formed on the channel layer 5 , that is, the quantum well (and the cap layer 6 ).
- a gate insulating layer 7 A and a gate conductive layer 7 B are formed by depositing sequentially by means of such conventional deposition methods like LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation and sputtering, and by etching subsequently.
- the gate insulation layer 7 A is a high-K material, which includes but is not limited to nitrides (e.g. SiN, AlN, TiN), metal oxides (mainly oxides of sub-group or lanthanide metal elements, e.g.
- the gate conductive layer 7 B is a metal, a metal nitride or a combination thereof, wherein the metal includes Al, Ti, Cu, Mo, W and Ta to be used as the gate filling layer, and the metal nitride includes TiN, TaN to be used as the work function regulating layer.
- the gate stack structure When the gate stack structure employs a gate-last process, it is used as a dummy gate stack structure, so the dummy gate insulation layer is silicon oxide, and the dummy gate conductive layer is polysilicon or amorphous silicon, then in the subsequent process, the dummy gate stack structure is removed by etching to form a gate trench, wherein a gate insulation layer 7 A of a high-K material as mentioned above and the gate conductive layer 7 B of a metal material as mentioned above are filled in sequence, thus the gate insulation layer 7 A surrounds the bottom and sides of the gate conductive layer 7 B.
- Gate spacers 7 C formed of silicon nitride, silicon oxynitride and diamond like carbon (DLC) are formed at both sides of the gate insulation layer 7 A/the gate conductive layer 7 B by deposition and etching, and they together form a gate stack structure 6 .
- Source and drain regions 8 are formed at both sides of the gate stack structure 7 .
- the source and drain regions 8 are directly formed on the channel layer 5 by a deposition method such as MBE, MOCVD and ALD, which are formed of an SiGeSn alloy.
- the source and drain regions 8 include Sil-u-vGeuSnv, wherein the concentration u of Ge is greater than 50% and preferably between 60%-70%, i.e. 0.6 ⁇ u ⁇ 0.7, and the concentration v of Sn is less than 25% and preferably between 1%-10%, i.e. 0.01 ⁇ v ⁇ 0.1.
- the thickness of the source and drain regions 8 can be about 500 nm-2 ⁇ m.
- source and drain regions 8 of a SiGeSn ternary alloy can also be formed by implanting Si in the channel layer 5 of GeSn at both sides of the gate stack structure 7 and performing annealing, in this case, the source and drain regions 8 will extend into the channel layer 5 , unlike what is shown in FIG. 1 , without contacting the lower barrier layer 4 , namely, the depth of extension (not shown) is no more than the thickness of the channel layer 5 .
- raised source and drain regions 8 are formed by an epitaxial technique, such that the upper surfaces of the source and drain regions 8 are higher than the upper surface of the gate insulation layer 6 A.
- a trench may be formed first by etching, and the etching may stop either at the interface between the channel layer 5 and the cap layer 6 or in the channel layer 5 without reaching the barrier layer 4 .
- source and drain regions 8 of a SiGeSn ternary alloy as mentioned above are formed by a deposition method such as MBE, MOCVD and ALD.
- an in-situ doping or an implantation doping can be performed so that the source and drain regions 8 have a first conductivity type.
- the dopants may include B, P, Al, Ga, etc. for adjusting the conductivity type and concentration of the source and drain regions.
- a source/drain contact layer 9 e.g. a metal silicide, may be formed on the source and drain regions 8 to reduce the source/drain resistance.
- An inter-layer dielectric (ILD) 10 is formed on the entire device, and the ILD 10 is etched to form source/drain contact holes which will be then filled by such metals as W, Al and Mo to form a source/drain contact plugs 11 .
- the semiconductor device comprises a substrate 1 , a buffer layer 2 on the substrate 1 , a SiGe inversely doped isolation layer 3 on the buffer layer 2 , a barrier layer 4 formed of a SiGe alloy on the inversely doped isolation layer 3 , a channel layer 5 formed of a GeSn alloy on the barrier layer 4 , a gate stack structure 7 on the channel layer 5 , and source and drain regions at both sides of the gate stack structure 7 .
- a cap layer formed of a SiGe alloy is disposed between the channel layer 5 and the gate stack structure 7 .
- the buffer layer 2 , the inversely doped isolation layer 3 , the barrier layer 4 , and the cap layer 6 can be formed of a SiGe alloy or a SiGeSn ternary alloy that is the same as or similar to the source and drain regions 8 , for example, the above-mentioned Sil-u-vGeuSnv. Parameters like the material proportions and thickness of the rest of the components have been described in the above manufacturing method, so they will not be elaborated any more.
- the semiconductor device uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
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Abstract
Description
- This application is a National Phase application of, and claims priority to, PCT Application No. PCT/CN2012/001379, filed on Oct. 12, 2012, entitled ‘Semiconductor Device’, which claimed priority to Chinese Application No. CN 201210293234.0, filed on Aug. 16, 2012. Both the PCT Application and Chinese Application are incorporated herein by reference in their entireties.
- The present invention relates to the field of manufacturing of a semiconductor integrated circuit, in particular to a field effect transistor having a GeSn quantum well.
- With the continuous development of the integrated circuit technology, especially the continuous reduction of device size in scale, each of the key parameters, e.g. the threshold voltage of the device is reduced accordingly, and such advantages as reduced power consumption and increased integration promote the improvement of the overall performance of the device. But at the same time, the driving capability of the device is restricted by the conventional silicon material technology, wherein the carrier mobility is low, thus the driving capability of the device is comparatively insufficient to be used in high-speed and high-frequency application fields. Therefore, high mobility devices, especially high mobility transistors (HEMT) will be extensively used in the future.
- A kind of existing high mobility field effect transistor (FET) is AlGaAs/GaAs-based, which comprises, for example, a GaAs substrate, an intrinsic GaAs layer formed on the GaAs substrate (used as a buffer layer and/or a lower cap layer), an intrinsic AlxGal-xAs layer formed on the intrinsic GaAs layer (used as a potential well layer, an active layer and a control layer), an n-doped AlxGal-xAs layer formed on the intrinsic AlxGal-xAs layer (used as an upper cap layer), a gate stack formed on the upper cap layer and source and drain (contact) regions at both sides of the gate stack. During operation of the device, electrons that function as the carriers are generally limited in the potential well layer to form two-dimensional electron gas, so the carrier mobility in the layer is greatly increased, thereby improving the driving capability of the device.
- However, the above-mentioned materials and technologies are not quite compatible with the existing Si-based CMOS technology, therefore a lot of extra processes and facilities are needed when manufacturing high mobility devices, which result in a high cost. As an alternative, another kind of existing high mobility field effect transistor is made by depositing SiGe alloys of different proportions on a Si substrate as a quantum layer and using Si or SiGe as a buffer layer, a barrier layer and a cap layer. Such SiGe/Si-based high mobility FET reduces the cost, but only a limited increase of the mobility is achieved due to the limitation of the material itself.
- Thus there is the need for a FET which can be manufactured simply and be of higher carrier mobility.
- In view of the above, an object of the present invention is to provide a field effect transistor having a GeSn quantum well so as to greatly increase the carrier mobility while simplifying the process and reducing the cost.
- The above-mentioned object of the present invention is achieved by providing a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy.
- Wherein, the concentration of Ge in the buffer layer and/or the barrier layer and/or the inversely doped isolation layer is greater than 50%.
- Wherein, the concentration of Sn in the buffer layer and/or the barrier layer and/or the inversely doped isolation layer is less than 25%.
- Wherein, the thickness of the buffer layer is 100 nm-2 μm.
- Wherein, the concentration of Sn in the channel layer is greater than 1% and less than 25%.
- Wherein, the thickness of the channel layer is 5 nm-200 nm.
- Wherein, a cap layer formed of SiGe alloy is disposed between the channel layer and the gate stack structure.
- Wherein, the source and drain regions are formed of SiGeSn alloy.
- Wherein, the source and drain regions have a first conductivity type, and the inversely doped isolation layer, the barrier layer and the channel region have a second conductivity type opposite to the first conductivity type.
- Wherein, the forbidden-band width of the material of the barrier layer is greater than the band gap width of material of the channel layer.
- The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
- The technical solution of the present invention will be described below in details with reference to the drawing, wherein,
-
FIG. 1 is a sectional view of the semiconductor device according to an embodiment of the present invention. - The features and technical effects of the technical solution of the present invention will be described in details below with reference to the drawing and in conjunction with the exemplary embodiment. It shall be noted that similar reference signs are used to denote similar structures, and the terms “first”, “second”, “on”, “under”, “thick”, “thin” and the like can be used to modify various device structures, but such modifications do not imply the spatial, sequential or hierarchical relations of the modified device structure unless otherwise specified.
-
FIG. 1 is a sectional view of the semiconductor device according to an embodiment of the present invention. - A
substrate 1 is provided, which can be formed of (bulk) Si (e.g. monocrystalline Si wafer), SOI, and GeOI (Ge on Insulator). Preferably, thesubstrate 1 is formed of bulk Si or SOI so as to be compatible with the CMOS process. - A
buffer layer 2 is formed onsubstrate 1 by a deposition method such as PECVD, MOCVD, MBE and ALD so as to reduce the lattice mis-match between thesubstrate 1 and the upper GeSn channel layer. The lattice constant of the material of thebuffer layer 2 is between the Si/Ge ofsubstrate 1 and the upper layer GeSn, which is preferably a SiGe alloy, and specifically it can be Sil-xGex, with the concentration (atomic number percentage) x of Ge being greater than 50%, i.e. x>0.5. The thickness of thebuffer layer 2 is, for example, about 100 nm-2 μm. In addition, thebuffer layer 2 can also be a SiGeSn ternary alloy, such as Sil-u-vGeuSnv, wherein the concentration u of Ge is greater than 50% and is preferably between 60%-70%, i.e. 0.6<u<0.7, and the concentration v of Sn is less than 25% and is preferably between 1%-10%, i.e. 0.01<v<0.1. - An inversely doped
isolation layer 3 is formed on thebuffer layer 2 by a deposition method such as PECVD, MOCVD, MBE and ALD, whose conductivity type is the same as that of thebuffer layer 2 and/or the later formedbarrier layer 4 but different from that of the later formed source and drain regions 8 (having a first conductivity type, e.g. n or p), for example, the inversely dopedisolation layer 3 has a second conductivity type (p or n) for adjusting and controlling potential barrier and threshold voltage by doping. The material of the inversely dopedisolation layer 3 can be a SiGe alloy, specifically Sil-yGey, wherein a concentration (atomic number percentage) y of Ge is between 55%-75%, i.e. 0.55<y<0.75. The thickness of the inversely dopedisolation layer 3 is, for example, about 50 nm-500 nm. In-situ doping may be performed in the process of forming the inversely dopedisolation layer 3, or an implantation doping may be performed after forming the inversely dopedisolation layer 3, and the dopants include, for example, B, P, N, Al, Ga, etc. for adjusting the conductivity type. - Similarly, a
barrier layer 4 is formed on the inversely dopedisolation layer 3 by a deposition method such as PECVD, MOCVD, MBE and ALD, which is used for restricting the two-dimensional electron gas serving as carriers within the channel layer thereon. The material of thebarrier layer 4 can be a SiGe alloy, specifically Sil-yGey, wherein the concentration (atomic number percentage) y of Ge is greater than 50% and preferably between 55%-75%, i.e. 0.55<y<0.75. The thickness of the barrier layer is, for example, about 50 nm-500 nm. In addition, thebarrier layer 4 may also be the above-mentioned SiGeSn ternary alloy. Thebarrier layer 4 has a second conductivity type and a low doping concentration, i.e. it is of a p- or n-type. Particularly, the forbidden-band width E2 of the material of thebarrier layer 4 is greater than the band gap width E1 of the material of the later formedchannel layer 5. - A
quantum well 5 is formed on thebarrier layer 4 by deposition, so that it serves as the channel layer of the device. The material of thequantum well 5 is a GeSn alloy, specifically Gel-zSnz, wherein the concentration (atomic number percentage) z of Sn is between 1%-25%, i.e. 0.01<z<0.25. The thickness of the quantum well is, for example, about 5 nm-200 nm. The GeSn-based quantum well layer can be formed by conventional methods like MBE, MOCVD and ALD, or it can be formed by depositing an amorphous Ge layer and a metal Sn layer sequentially and making them react to each other by performing a laser fast annealing. - Optionally, a
cap layer 6 is formed on thequantum well layer 5 by deposition method such as PECVD, MOCVD, MBE and ALD, which is used for restricting the two-dimensional electron gas serving as the carriers within thechannel layer 5 thereunder. The material of thecap layer 6 can be a SiGe alloy, specifically Sil-wGew, wherein the concentration (atom number percentage) w of Ge is greater than 50% and preferably between 60%-85%, i.e. 0.60<w<0.85. The thickness of thecap layer 6 is, for example, 100 nm-500 nm. - Afterwards, a gate stack structure 7 is formed on the
channel layer 5, that is, the quantum well (and the cap layer 6). For example, agate insulating layer 7A and a gateconductive layer 7B are formed by depositing sequentially by means of such conventional deposition methods like LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation and sputtering, and by etching subsequently. When the gate stack structure employs a gate-first process, thegate insulation layer 7A is a high-K material, which includes but is not limited to nitrides (e.g. SiN, AlN, TiN), metal oxides (mainly oxides of sub-group or lanthanide metal elements, e.g. Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, La2O3), perovskite phase oxides (e.g. PbZrxTi1-xO3(PZT), BaxSr1-xTiO3 (BST)); the gateconductive layer 7B is a metal, a metal nitride or a combination thereof, wherein the metal includes Al, Ti, Cu, Mo, W and Ta to be used as the gate filling layer, and the metal nitride includes TiN, TaN to be used as the work function regulating layer. When the gate stack structure employs a gate-last process, it is used as a dummy gate stack structure, so the dummy gate insulation layer is silicon oxide, and the dummy gate conductive layer is polysilicon or amorphous silicon, then in the subsequent process, the dummy gate stack structure is removed by etching to form a gate trench, wherein agate insulation layer 7A of a high-K material as mentioned above and the gateconductive layer 7B of a metal material as mentioned above are filled in sequence, thus thegate insulation layer 7A surrounds the bottom and sides of the gateconductive layer 7B.Gate spacers 7C formed of silicon nitride, silicon oxynitride and diamond like carbon (DLC) are formed at both sides of thegate insulation layer 7A/the gateconductive layer 7B by deposition and etching, and they together form agate stack structure 6. - Source and
drain regions 8 are formed at both sides of the gate stack structure 7. - When there is no cap layer 6 (not shown), the source and
drain regions 8 are directly formed on thechannel layer 5 by a deposition method such as MBE, MOCVD and ALD, which are formed of an SiGeSn alloy. Specifically, the source anddrain regions 8 include Sil-u-vGeuSnv, wherein the concentration u of Ge is greater than 50% and preferably between 60%-70%, i.e. 0.6<u<0.7, and the concentration v of Sn is less than 25% and preferably between 1%-10%, i.e. 0.01<v<0.1. The thickness of the source anddrain regions 8 can be about 500 nm-2 μm. Alternatively, source anddrain regions 8 of a SiGeSn ternary alloy can also be formed by implanting Si in thechannel layer 5 of GeSn at both sides of the gate stack structure 7 and performing annealing, in this case, the source anddrain regions 8 will extend into thechannel layer 5, unlike what is shown inFIG. 1 , without contacting thelower barrier layer 4, namely, the depth of extension (not shown) is no more than the thickness of thechannel layer 5. Preferably, raised source anddrain regions 8 are formed by an epitaxial technique, such that the upper surfaces of the source anddrain regions 8 are higher than the upper surface of the gate insulation layer 6A. - As shown in
FIG. 1 , when acap layer 6 exists on thechannel layer 5, a trench may be formed first by etching, and the etching may stop either at the interface between thechannel layer 5 and thecap layer 6 or in thechannel layer 5 without reaching thebarrier layer 4. Then, source anddrain regions 8 of a SiGeSn ternary alloy as mentioned above are formed by a deposition method such as MBE, MOCVD and ALD. - Preferably, when or after forming the source and
drain regions 8, an in-situ doping or an implantation doping can be performed so that the source anddrain regions 8 have a first conductivity type. The dopants may include B, P, Al, Ga, etc. for adjusting the conductivity type and concentration of the source and drain regions. - Finally, a source/
drain contact layer 9, e.g. a metal silicide, may be formed on the source anddrain regions 8 to reduce the source/drain resistance. An inter-layer dielectric (ILD) 10 is formed on the entire device, and theILD 10 is etched to form source/drain contact holes which will be then filled by such metals as W, Al and Mo to form a source/drain contact plugs 11. - Therefore, according to the first embodiment of the present invention, the semiconductor device comprises a
substrate 1, abuffer layer 2 on thesubstrate 1, a SiGe inversely dopedisolation layer 3 on thebuffer layer 2, abarrier layer 4 formed of a SiGe alloy on the inversely dopedisolation layer 3, achannel layer 5 formed of a GeSn alloy on thebarrier layer 4, a gate stack structure 7 on thechannel layer 5, and source and drain regions at both sides of the gate stack structure 7. Wherein a cap layer formed of a SiGe alloy is disposed between thechannel layer 5 and the gate stack structure 7. Wherein, thebuffer layer 2, the inversely dopedisolation layer 3, thebarrier layer 4, and thecap layer 6 can be formed of a SiGe alloy or a SiGeSn ternary alloy that is the same as or similar to the source anddrain regions 8, for example, the above-mentioned Sil-u-vGeuSnv. Parameters like the material proportions and thickness of the rest of the components have been described in the above manufacturing method, so they will not be elaborated any more. - The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
- While the invention has been described in conjunction with one or more exemplary embodiments, those skilled in the art are aware that various appropriate changes and equivalents can be made to the method for forming the device structure without departing from the scope of the present invention. In addition, on the basis of the disclosed teaching, many modifications may be adapted to specific situations or materials without departing from the scope of the present invention. Therefore, it is not intended to limit the present invention to the specific embodiments that are disclosed as the best ways of implementing the present invention, and the disclosed device structure and its manufacturing method shall include all embodiments that fall within the scope of the present invention.
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140054547A1 (en) * | 2012-08-24 | 2014-02-27 | Globalfoundries Inc. | Device with strained layer for quantum well confinement and method for manufacturing thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000031469A (en) * | 1998-07-14 | 2000-01-28 | Hitachi Ltd | Semiconductor device and production method thereof |
ATE394794T1 (en) * | 1999-03-12 | 2008-05-15 | Ibm | HIGH VELOCITY GE CHANNEL HETEROSTRUCTURE FOR FIELD EFFECT ARRANGEMENTS |
US7416605B2 (en) * | 2007-01-08 | 2008-08-26 | Freescale Semiconductor, Inc. | Anneal of epitaxial layer in a semiconductor device |
US7435987B1 (en) * | 2007-03-27 | 2008-10-14 | Intel Corporation | Forming a type I heterostructure in a group IV semiconductor |
CN102640269B (en) * | 2009-09-30 | 2015-08-12 | 苏沃塔公司 | Electronic installation and system and production and preparation method thereof |
-
2012
- 2012-08-16 CN CN201210293234.0A patent/CN103594506B/en active Active
- 2012-10-12 US US13/812,504 patent/US8796744B1/en active Active
- 2012-10-12 WO PCT/CN2012/001379 patent/WO2014026308A1/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140054547A1 (en) * | 2012-08-24 | 2014-02-27 | Globalfoundries Inc. | Device with strained layer for quantum well confinement and method for manufacturing thereof |
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