CN103824885B

CN103824885B - GeSnn channel tunneling field effect transistor with source strain source

Info

Publication number: CN103824885B
Application number: CN201410057722.0A
Authority: CN
Inventors: 刘艳; 韩根全; 王洪娟
Original assignee: Chongqing University
Current assignee: Chongqing University
Priority date: 2014-02-20
Filing date: 2014-02-20
Publication date: 2015-05-20
Anticipated expiration: 2034-02-20
Also published as: CN103824885A

Abstract

The invention provides a GeSnn channel tunneling field effect transistor (10) with a source strain source. The GeSnn channel tunneling field effect transistor structurally comprises a GeSnn channel, a source electrode, a drain electrode, the source strain source, an insulating dielectric film and a gate electrode. The source strain source (102) grows in a source electrode area (101), the insulating dielectric film (105) grows on the GeSnn channel, and the insulating dielectric film is covered with a layer of gate (104). The lattice constant of the source strain source (102) is larger than that of the source electrode area (101), the strain on a channel area is formed, the strain is double-axis tensile strain in the yz-plane, and the strain is single-axis compression strain in the x direction. The strain enables n channel GeSn to be changed into a direct band gap from an indirect band gap, therefore, direct quantum tunneling is formed, tunneling currents are increased, and then the performance of the TFET is improved.

Description

With the GeSn n raceway groove tunneling field-effect transistor of active strained source

Technical field

The present invention relates to a kind of GeSn n raceway groove TFET (Tunneling Field-Effect Transistor: tunneling field-effect transistor) with active strained source.

Background technology

Along with further developing of integrated circuit, reducing further of chip feature sizes, increasing of device count integrated on one single chip, power consumption more and more becomes the problem that people pay close attention to.According to the display of ITRS data, when feature size downsizing is to 32nm node, power consumption can be 8 times of expectation trend, progressively reducing namely along with characteristic size, traditional MOS device can not satisfy the demands (Nature, vol479 with regard to power consumption aspect, 329-337,2011).In addition, the reduction of MOSFET size is faced with the minimum restriction for 60mv/decade of sub-threshold slope under room temperature.It is the restriction of 60mv/decade that tunneling field-effect transistor based on tunneling effect does not have sub-threshold slope minimum compared with MOSFET, and can effectively reduce power consumption.How to increase tunnelling probability, increase the emphasis that tunnelling current becomes TFET research.Theoretical and experiment has shown direct tunnelling and has had larger tunnelling probability than indirect tunnelling, and then produces larger tunnelling current (Journal of applied physics 113,194507,2013).

Theoretical confirmation, when the component of Sn reaches 6.5% ~ 11%, the GeSn material of relaxation can change direct band gap (Journal of Applied Physics113,073707,2013) into.Now then can form direct tunnelling between source and raceway groove, effectively increase tunnelling probability, increase tunnelling current, improve the performance of device.But the increase of Sn component can make the quality of whole material and thermal stability be deteriorated, and the GeSn that the component just by increasing Sn obtains direct band gap is difficult.Theory calculate shows, and introduces twin shaft tensile strain and be conducive to the transformation (Appl.Phys.Lett., vol.98, no.1, pp.011111-1-011111-3,2011) of material to direct band gap in GeSn.

Summary of the invention

The object of the invention is the structure proposing a kind of GeSn n raceway groove tunneling field-effect transistor (TFET) with active strained source.Wherein the material of source electrode, n raceway groove is identical, is all monocrystalline GeSn, and general formula is Ge _{1-
x}sn _x(0≤ x≤ 0.25), the lattice constant of source strained source is larger than the lattice constant of raceway groove GeSn, forms the single shaft compressive strain along channel direction, forms twin shaft tensile strain along in the plane of vertical-channel.This strain regime is conducive to GeSn material and changes to direct band gap, and direct tunnelling occurs, and increases tunnelling current, improves device performance.

The present invention is as follows in order to the technical scheme realizing above-mentioned purpose:

Mos field effect transistor proposed by the invention has a GeSn n raceway groove, one source pole, a drain electrode, a source strained source, an insulative dielectric matter film, a gate electrode.Wherein, source electrode and n raceway groove are monocrystalline GeSn material, and insulative dielectric matter film is positioned on n raceway groove, and gate electrode covers on insulative dielectric matter film, and the growth of source electrode strained source is on source electrode.Its key is, source strained source GeSn lattice constant is larger than the lattice constant of n raceway groove GeSn, thus produces the single shaft compressive strain along channel direction, the twin shaft tensile strain in the plane in vertical-channel direction.This strain is conducive to raceway groove GeSn and changes direct band gap into, and direct tunnelling occurs, and increases tunnelling current.

Benefit analysis of the present invention is as follows:

Because source electrode of the present invention, n raceway groove, strained source material are monocrystalline GeSn, by changing the component of Sn in GeSn, make the lattice constant of source strained source larger than the lattice constant of the material of source, channel region, thus the strain formed channel region, being twin shaft tensile strain in yz plane, is single shaft compressive strain in x direction, this strain is conducive to raceway groove GeSn and changes to direct band gap, there is direct tunnelling, increase tunnelling current, improve device performance.

Accompanying drawing explanation

Fig. 1 is the three-dimensional pattern figure of GeSn n raceway groove TFET.

Fig. 2 is the XY face profile of GeSn n raceway groove TFET.

Fig. 3 is the first step that GeSn n raceway groove TFET manufactures.

Fig. 4 is the second step that GeSn n raceway groove TFET manufactures.

Fig. 5 is the 3rd step that GeSn n raceway groove TFET manufactures.

Fig. 6 is the 4th step that GeSn n raceway groove TFET manufactures.

Embodiment

In order to help those skilled in the art more clearly to understand technical spirit of the present invention, describing Structure and energy of the present invention in detail below in conjunction with drawings and Examples and realizing:

See the GeSn n raceway groove tunneling field-effect transistor of the active strained source of the band shown in Fig. 1 and Fig. 2, it comprises:

One n raceway groove 103, material is monocrystalline GeSn, and general formula is Ge _{1-
x}sn _x(0≤ x≤ 0.25), as can Ge be adopted _0.95sn _0.05;

One insulative dielectric matter film 105, grows on raceway groove, as adopted H-k(high-k) material silica hafnium H _fo ₂;

One gate electrode 104, covers on described insulative dielectric matter film;

One source pole 101, material is monocrystalline GeSn, and general formula is Ge _{1-
x}sn _x(0≤ x≤ 0.25), as adopted Ge _0.95sn _0.05;

One drain electrode 106, material is monocrystalline GeSn, and general formula is Ge _{1-
x}sn _x(0≤ x≤ 0.25), as adopted Ge _0.95sn _0.05;

One source pole strained source 102, grows on source electrode, and material is GeSn, and general formula is Ge _{1-
y}sn _y(0< y≤ 0.25, y> x), as with containing Sn component be the Ge of 10% _0.9sn _0.1.

See Fig. 3-Fig. 6, the GeSn n raceway groove TFET(10 for active strained source) manufacture process:

The first step as shown in Figure 3, prepares a GeSn material (Ge _{1-
x}sn _x) nano wire, wherein mid portion is GeSn n raceway groove (103).

Second step as shown in Figure 4, is formed at GeSn nano wire and encloses grid structure, namely on GeSn n raceway groove, grow insulative dielectric matter film 105, covering grid electrode 104 on insulative dielectric matter film.

3rd step as shown in Figure 5, to source region (i.e. the GeSn nano wire of raceway groove left end) etching, forms source electrode 101.The GeSn nano wire of right-hand member is then as drain electrode 106.

4th step as shown in Figure 6, utilizes epitaxially grown method growth strain material in source region, form source electrode strained source 102, the lattice constant of its material is greater than the lattice constant of source electrode, n raceway groove GeSn material.

Although the present invention with example openly as above; so itself and be not used to limit that this is clearly demarcated; if do not depart from the spirit and scope of the present invention to the various change of inventing or distortion; these are changed and are out of shape within claim of the present invention and equivalent technologies scope; then the present invention is also intended to comprise these changes and distortion, and protection scope of the present invention is when being as the criterion depending on claim.

Claims

1. be with a GeSn n raceway groove tunneling field-effect transistor for active strained source, it is characterized in that, comprising:

One n raceway groove (103) is GeSn monocrystal material;

One insulative dielectric matter film (105), is positioned on raceway groove;

One gate electrode (104), is positioned on described insulative dielectric matter film;

One source pole (101) and a drain electrode (106), be monocrystalline GeSn material;

One source strained source (102), is positioned on source electrode;

Wherein, the lattice constant of source strained source is larger than the lattice constant of source electrode, forms the single shaft compressive strain along channel direction, forms twin shaft tensile strain along in the plane of vertical-channel;

The monocrystalline GeSn material general formula of described n raceway groove is Ge _{1-
x}sn _x,wherein 0≤ x≤ 0.25;

The monocrystalline GeSn material general formula of described source electrode is Ge _{1-
x}sn _x,wherein 0≤ x≤ 0.25;

The general formula of the single-crystal semiconductor material GeSn that described source strained source adopts is Ge _{1-
y}sn _y,wherein 0≤ y≤ 0.25, y>x.

2. the GeSn n raceway groove tunneling field-effect transistor of the active strained source of band as claimed in claim 1, is characterized in that, wherein source strained source passes through the technology growth of semiconductor epitaxial growth in source region.