CN104425269B - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN104425269B CN104425269B CN201310379961.3A CN201310379961A CN104425269B CN 104425269 B CN104425269 B CN 104425269B CN 201310379961 A CN201310379961 A CN 201310379961A CN 104425269 B CN104425269 B CN 104425269B
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 230000005669 field effect Effects 0.000 title claims abstract description 48
- 239000012212 insulator Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 248
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 53
- 230000004888 barrier function Effects 0.000 claims description 38
- 230000003647 oxidation Effects 0.000 claims description 32
- 238000007254 oxidation reaction Methods 0.000 claims description 32
- 229910052757 nitrogen Inorganic materials 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 23
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052719 titanium Inorganic materials 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 15
- 229910052799 carbon Inorganic materials 0.000 claims description 14
- 239000012774 insulation material Substances 0.000 claims description 14
- 239000011133 lead Substances 0.000 claims description 14
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 13
- 229910052726 zirconium Inorganic materials 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 229910017052 cobalt Inorganic materials 0.000 claims description 12
- 239000010941 cobalt Substances 0.000 claims description 12
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 12
- 229910052746 lanthanum Inorganic materials 0.000 claims description 12
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 12
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229910002899 Bi2Te3 Inorganic materials 0.000 claims description 7
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical group [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 241000209094 Oryza Species 0.000 claims description 6
- 235000007164 Oryza sativa Nutrition 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910017629 Sb2Te3 Inorganic materials 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- WOIHABYNKOEWFG-UHFFFAOYSA-N [Sr].[Ba] Chemical compound [Sr].[Ba] WOIHABYNKOEWFG-UHFFFAOYSA-N 0.000 claims description 6
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 6
- 229910002113 barium titanate Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 6
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 6
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 235000009566 rice Nutrition 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052706 scandium Inorganic materials 0.000 claims description 6
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
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- 239000004332 silver Substances 0.000 claims description 6
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- 239000011135 tin Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 6
- -1 tungsten nitride Chemical class 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- 229910052727 yttrium Inorganic materials 0.000 claims description 6
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 239000011701 zinc Substances 0.000 claims description 6
- RPEUFVJJAJYJSS-UHFFFAOYSA-N zinc;oxido(dioxo)niobium Chemical compound [Zn+2].[O-][Nb](=O)=O.[O-][Nb](=O)=O RPEUFVJJAJYJSS-UHFFFAOYSA-N 0.000 claims description 6
- BOIGHUSRADNYQR-UHFFFAOYSA-N aluminum;lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Al+3].[La+3] BOIGHUSRADNYQR-UHFFFAOYSA-N 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- RGZQGGVFIISIHZ-UHFFFAOYSA-N strontium titanium Chemical compound [Ti].[Sr] RGZQGGVFIISIHZ-UHFFFAOYSA-N 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims 2
- 239000002253 acid Substances 0.000 claims 1
- UZQSJWBBQOJUOT-UHFFFAOYSA-N alumane;lanthanum Chemical compound [AlH3].[La] UZQSJWBBQOJUOT-UHFFFAOYSA-N 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 description 8
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- 229910052751 metal Inorganic materials 0.000 description 5
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- 230000002452 interceptive effect Effects 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of fin formula field effect transistor and forming method thereof, wherein, the forming method of fin formula field effect transistor includes：Substrate is provided, fin is formed with substrate；In fin portion surface selective growth topological insulator layer；Gate dielectric layer is formed, gate dielectric layer Overlay Topology insulator layer is developed across the first grid of gate dielectric layer；The gate dielectric layer and topological insulator layer at fin two ends are removed respectively, in exposed epitaxial layer of the fin portion surface formation with doping, separated between epitaxial layer and first grid by remaining gate dielectric layer and topological insulator layer, fin two ends have the epitaxial layer of doping respectively as source electrode, drain electrode.Apply voltage between the source and drain, topological insulator layer surface conducting, topological insulator layer surface is used as channel region；Apply voltage between grid and source electrode, the electric field that the voltage triggers can adjust the carrier concentration of topological insulator layer surface.Carrier in channel region will not be collided, disturbed, and improve the mobility of carrier.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of fin formula field effect transistor and forming method thereof.
Background technology
In technical field of semiconductors, constantly reduce with the characteristic size of integrated circuit, and to the higher letter of integrated circuit
The requirement of number transmission speed, transistor is needed while size is gradually reduced with higher driving current.It is this to comply with
It is required that, traditional complementary metal oxide semiconductor（Complementary Metal Oxide Semiconductor, CMOS）
The length of transistor becomes shorter than ever, however, this is still difficult to the need for meeting high integration.
Therefore, in the prior art, it is proposed that fin formula field effect transistor（FinFET）.Reference picture 1, fin field effect is brilliant
Body pipe includes：Insulating barrier 11 on substrate 10；Through insulating barrier 11 and it is higher by the fin 12 of the upper surface of insulating barrier 11；Across
The grid 13 of the fin 12, grid 13 is contacted with the fin upper surface under it and sidewall surfaces；It is respectively formed at 13 liang of grid
The source electrode in lateral fin portion, drain electrode（It is not shown）, between source electrode and grid, drain grid between be spaced apart from each other.Compared to mutual
Metal oxide semiconductor transistor is mended, fin formula field effect transistor is the similar stereochemical structure on substrate, its feature
It is smaller, it can more meet the requirement of high integration.
The sidewall surfaces that the grid 13 of fin formula field effect transistor is relative with two with the upper surface of fin 12 are contacted, then are existed
During work, the sidewall surfaces that the upper surface of the fin 12 contacted with grid 13 is relative with two can form channel region, this lifting
The mobility of carrier.
But, as the expansion of the information data of modern society is, it is necessary to data transfer faster, more efficient, and current
The mobility of carrier can not meet this requirement in fin formula field effect transistor.
The content of the invention
The problem of present invention is solved be, with modern society information data expansion, it is necessary to data faster, more efficient
Transmission, and the mobility of carrier can not meet this requirement in current fin formula field effect transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, the fin effect
Answering the forming method of transistor includes：
Substrate is provided, fin is formed with the substrate；
In fin portion surface selective growth topological insulator layer；
Gate dielectric layer is formed, the gate dielectric layer Overlay Topology insulator layer is developed across the first of the gate dielectric layer
Grid；
The gate dielectric layer and topological insulator layer at the fin two ends are removed, there is doping in exposed fin portion surface formation
Epitaxial layer, between the epitaxial layer and first grid by remaining gate dielectric layer and topological insulator layer separate, the fin
Portion two ends have the epitaxial layer of doping respectively as source electrode, drain electrode.
Alternatively, the material of the topological insulator layer is Bi2Te3、Bi2Se3Or Sb2Te3。
Alternatively, the method for the selective growth topological insulator layer is molecular beam epitaxial growth.
Alternatively, the molecular beam epitaxial growth process is located in vacuum environment, and the pressure range of the vacuum environment is
10-7~10-10Torr；The temperature range of vacuum environment is 150~250 DEG C.
Alternatively, it is dry etching to remove the gate dielectric layer at the fin two ends and the method for topological insulator layer.
Alternatively, include in the method for exposed epitaxial layer of the fin portion surface formation with doping：
Epitaxial layer is epitaxially-formed in exposed fin portion surface, in epitaxial growth epitaxial layer, ion in situ is also carried out
Injection, forms the epitaxial layer with doping.
Alternatively, the material of the epitaxial layer is carbon silicon, is doped to n-type doping in the epitaxial layer；Or,
The material of the epitaxial layer is that the p-type that is doped in germanium silicon, the epitaxial layer is adulterated；
Alternatively, the first grid is the grid of preceding grid technique formation.
Alternatively, the first grid is the dummy grid in rear grid technique, and the gate dielectric layer is high-K gate dielectric layer；
After source electrode, drain electrode is formed, interlayer dielectric layer, the interlayer dielectric layer upper surface and puppet are formed on the substrate
Gate upper surface maintains an equal level；
Remove the dummy grid and form pseudo- gate groove；
Second grid is formed in the pseudo- gate groove.
Alternatively, the material of the high-K gate dielectric layer is hafnium oxide, zirconium oxide, lanthana, aluminum oxide, tantalum oxide, oxidation
Titanium, strontium titanates, yittrium oxide, barium strontium, barium titanate, lead titanates scandium, aluminum oxide lanthanum, zinc titanate, zinc niobate lead, nitrogen oxidation hafnium,
Nitrogen oxidation zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen oxidation strontium titanium, nitrogen oxidation lanthanum aluminium, one kind in yttrium oxynitride or
It is a variety of.
Alternatively, the method for forming gate dielectric layer is ald.
Alternatively, the material of the second grid is tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver, gold, nitrogen
Change the one or more that tantalum, titanium nitride, tungsten nitride, tungsten silicide, ruthenium-oxide, cobalt silicide, nickle silicide, carbon rice are received in pipe, conductive carbon.
Alternatively, forming the method for the fin includes：
The graphical substrate, forms the protuberance for being higher by the substrate surface；
The insulation material layer upper surface formed on the substrate in insulation material layer, the substrate is higher than protuberance upper table
Insulation material layer upper surface on face, or the substrate maintains an equal level with projections top surface；
The insulation material layer is etched back to, the insulation material layer of segment thickness is removed, residual insulator material layer is used as insulation
Layer, the protuberance higher than insulating barrier upper surface is used as fin.
Alternatively, the material of the insulating barrier is silica, silicon nitride or silicon oxynitride.
Alternatively, the substrate is silicon-on-insulator substrate, and the silicon-on-insulator substrate includes：Bottom silicon layer, it is located at
Insulating barrier on the bottom silicon layer, the top silicon layer on the insulating barrier；
Forming the method for the fin includes：The graphical top silicon layer formation fin.
The present invention also provides a kind of fin formula field effect transistor, and the fin formula field effect transistor includes：
Substrate；
Fin in the substrate；
The topological insulator layer of the fin portion surface of partial-length between fin two ends；
Gate dielectric layer on topological insulator layer；
Across the grid of the gate dielectric layer；
It is gate dielectric layer and topology insulation between the epitaxial layer and grid positioned at the epitaxial layer of the end surfaces of fin two
Body layer is separated, and has doping in the epitaxial layer, positioned at the epitaxial layer difference with doping of the end surfaces of fin two
It is used as source electrode, drain electrode.
Alternatively, the material of the topological insulator layer is Bi2Te3、Bi2Se3Or Sb2Te3。
Alternatively, the material of the epitaxial layer is carbon silicon, is doped to n-type doping in the epitaxial layer；Or,
The material of the epitaxial layer is that the p-type that is doped in germanium silicon, the epitaxial layer is adulterated.
Alternatively, the material of the grid is polysilicon.
Alternatively, the gate dielectric layer is high-K gate dielectric layer, and the fin formula field effect transistor also includes being located in substrate
Interlayer dielectric layer, the grid is located in interlayer dielectric layer, and the gate upper surface and interlayer dielectric layer upper surface maintain an equal level.
Alternatively, the material of the high-K gate dielectric layer is hafnium oxide, zirconium oxide, lanthana, aluminum oxide, tantalum oxide, oxidation
Titanium, strontium titanates, yittrium oxide, barium strontium, barium titanate, lead titanates scandium, aluminum oxide lanthanum, zinc titanate, zinc niobate lead, nitrogen oxidation hafnium,
Nitrogen oxidation zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen oxidation strontium titanium, nitrogen oxidation lanthanum aluminium, one kind in yttrium oxynitride or
It is a variety of.
Alternatively, the material of the grid be tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver, gold, tantalum nitride,
The one or more that titanium nitride, tungsten nitride, tungsten silicide, ruthenium-oxide, cobalt silicide, nickle silicide, carbon rice are received in pipe, conductive carbon.
Compared with prior art, technical scheme has advantages below：
Technical scheme is using selective growth method in fin portion surface growth topological insulator layer.Different from tradition
Semi-conducting material, topological insulator layer surface is metallic state, when applying voltage between the source and drain, topological insulator layer
The carrier on surface moves to form electric current between the source and drain, fin formula field effect transistor work, topological insulator layer table
Face is used as channel region.When fin formula field effect transistor works, apply voltage between grid and source electrode, the voltage draws electricity
Field can adjust the carrier concentration of topological insulator layer surface.The carrier concentration of the regulation topological insulator layer surface,
Including increase carrier concentration, to improve the mobility of carrier in channel region；With reduce carrier concentration, to realize closing ditch
The purpose in road area.
In addition, when fin formula field effect transistor works, electron spin direction and the electronics of topological insulator layer surface are transported
There is the relation determined in dynamic direction, for example, when the electronics spun up is to left movement, the downward electronics that spins can only be transported to the right
It is dynamic；Accordingly, when the electronics spun up is moved right, spinning downward electronics can only be to left movement.So along not Tongfang
Taken their own roads to the electronics of motion without interfering, colliding, this improves the mobility of carrier in channel region, and
And energy loss is significantly reduced so that source electrode and drain electrode between electric current increase, lifting transistor in signal transmission speed and
The performance of transistor.
Brief description of the drawings
Fig. 1 is the dimensional structure diagram of the fin formula field effect transistor of prior art;
Fig. 2 is dimensional structure diagram of the fin formula field effect transistor of the specific embodiment of the invention in manufacturing process；
Fig. 3 is the cross-sectional view along Fig. 2 AA directions；
Fig. 4 is cross-sectional view of the fin formula field effect transistor of the specific embodiment of the invention in manufacturing process；
Fig. 5 is dimensional structure diagram of the fin formula field effect transistor of the specific embodiment of the invention in manufacturing process；
Fig. 6 is the cross-sectional view along Fig. 5 BB directions；
Fig. 7 is dimensional structure diagram of the fin formula field effect transistor of the specific embodiment of the invention in manufacturing process；
Fig. 8 is the cross-sectional view along Fig. 7 CC directions.
Embodiment
The problem of for background technology, the present invention proposes that existing topological insulator material is applied to fin effect by one kind
Answer the scheme of transistor.
Topological insulator（Topological Insulator, TI）It is a kind of novel substance shape with unusual Quantum Properties
State, is one of important science focus and forward position of physics in recent years.It is totally different from traditional " metal " and " exhausted
Edge body ", it is a kind of built-in electrical insulation and interface allows the metallic state that electric charge is moved.In other words, the body electronics of topological insulator
State is the insulator for having energy gap, and its surface is then the metallic state of no energy gap.But, this surface metal state without energy gap is also complete
It is complete be different from general sense due to surface state caused by surface unsaturated linkage either surface reconstruction, that is, different from passing
Metal in meaning of uniting, the surface metal state of topological insulator is entirely to be determined by the topological structure of the body electronic state of material,
It is to be determined by symmetry, the concrete structure with surface is unrelated.Exactly because also the appearance of the surface metal state is symmetrical by its
What property was determined, so its presence is highly stable, it is substantially not subject to impurity and unordered influence.
In addition, the fundamental property of topological insulator be by " quantum mechanics " and " the theory of relativity " coefficient result,
Due to Effect of Spin-orbit Coupling, the table for the spinning resolving without energy gap protected by Time-reversal symmetry can be produced on the surface
Face electronic state, the movement locus of this electronics has regularity, the same just as the automobile moved on highway, positive and anti-
Different roads are walked respectively to the automobile of traveling, are not interfere with each other.Electronics in such ordered movement state will not be collided mutually,
Therefore energy consumption is very low.
The features described above having just because of topological insulator, technical solution of the present invention is proposed is applied to fin by it
Field-effect transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Reference picture 2, Fig. 3, Fig. 2 are dimensional structure diagram, and Fig. 3 is the cross-sectional view along Fig. 2 AA directions, is carried
For substrate 100.
In a particular embodiment, the material of the substrate 100 can be silicon, GaAs, indium phosphide, gallium nitride or carbon silicon etc.
Well known material.In the present embodiment, the material of substrate 100 is silicon, is formed with the substrate 100 highly doped, is allowed to have
There is preferable electric conductivity.
With continued reference to Fig. 2, Fig. 3, insulating barrier 101 is formed in the substrate 100, is also formed higher than exhausted in substrate 100
It is insulating barrier 101 around the fin 102 of the upper surface of edge layer 101, fin 102.
Specifically, insulating barrier 101 and the method for fin 102 are formed in substrate 100 to be included：
Graphical substrate 100, removes the substrate of fin position peripheral part thickness, and formation is higher by the upper surface of substrate 100
Protuberance 103；
The insulation material layer upper surface formed in substrate 100 in insulation material layer, the substrate and the upper table of protuberance 103
Face maintains an equal level, and in other embodiments, the insulating barrier upper surface in the substrate can also be higher than projections top surface；
Insulation material layer is etched back to, the insulation material layer of segment thickness is removed, residual insulator material layer is used as insulating barrier
101, the protuberance higher than the upper surface of insulating barrier 101 is used as fin 102.
In a particular embodiment, the material of insulating barrier 101 is silica, silicon nitride or silicon oxynitride.In other embodiment
In, the material of the insulating barrier 101 is alternatively other feasible insulating materials.
In the present embodiment, substrate 100 is silicon base.But not limited to this, in other embodiments, the substrate are insulation
Silicon base on body, the silicon-on-insulator substrate includes bottom silicon layer, the insulating barrier on bottom silicon layer and positioned at insulating barrier
On top silicon layer, then formed fin method for graphical top silicon layer formation fin.
Reference picture 4, in the surface selective growth topological insulator layer 104 of fin 102, the surface of fin 102 includes fin
The upper surface in portion 102 and all sides, in this process, the effect mask layer of insulating barrier 101 so that topological insulator layer 104
Only in the superficial growth of fin 102.
In a particular embodiment, the growth of topological insulator layer is relevant with the crystal orientation of fin 102, and crystal orientation lattice constant
Characterize.In the present embodiment, substrate 100 is silicon base, and the crystal orientation of silicon base is Si（111）, topological insulator is along fin 102
Si（111）Direction grows, and the topological insulator layer so formed and the combination of fin portion surface are even closer.In other embodiment
In, when the crystal orientation of substrate is other crystal orientation, topological insulator can also grow along particular crystal orientation.
In a particular embodiment, the material of topological insulator layer 104 is Bi2Te3、Bi2Se3Or Sb2Te3.In the present embodiment
In, the method for the selective growth topological insulator layer 104 is molecular beam epitaxy（Molecular Beam Epitaxy,
MBE）Growth.With Bi2Te3Exemplified by, under UHV condition, the stove equipped with the component needed for various such as Bi, Te is heated and produced
Raw steam, atomic beam or molecular beam that steam is formed after being collimated through aperture are linearly directly injected to the fin of proper temperature
102 surfaces, while controlling atomic beam or molecular beam to be scanned the surface of fin 102, so that it may make the molecule of Bi, Te or they exist
The surface of fin 102 successively grows along crystal orientation, until forming topological insulator layer 104.Molecular beam epitaxy is advantageous in that：Use
Substrate, fin temperature are low, and the growth rate of topological insulator layer 104 is slow, and the injection intensity of molecular beam or atomic beam is easy to accurate
Control, achieves effective control the thickness of topological insulator layer 104, and reduces the mesh of the line width roughness of topological insulator layer 104
's.
In a particular embodiment, the molecular beam epitaxial growth process is located in vacuum environment, the pressure model of vacuum environment
Enclose for 10-7~10-10Torr, in vacuum environment, can avoid impurity contamination, can the fabulous topological insulator layer of long mass；
The temperature range of vacuum environment is 150~250 DEG C, and this can promote Bi, Te molecular beam or atomic beam in the expansion of fin portion surface
Dissipate so that the topological insulator layer surface of fin portion surface formation is more smooth.If temperature is less than 150 DEG C, Bi, Te molecule
Beam or atomic beam can not form uniform, effective diffusion in fin portion surface so that topological insulator layer surface is coarse.If temperature is high
In 250 DEG C, Bi, Te molecular beam or atomic beam can not sublimate into solid completely, cannot also form complete topological insulator
Layer.
Reference picture 5, Fig. 6, Fig. 5 are dimensional structure diagrams, and Fig. 6 is the cross-sectional view along Fig. 5 BB directions, shape
Into gate dielectric layer 105, the covering insulating barrier 101 of gate dielectric layer 105 and topological insulator layer 104 are subsequently formed across gate dielectric layer
105 first grid 106.In other embodiments, gate dielectric layer also can an Overlay Topology insulator layer surface, i.e., formed grid
During dielectric layer, the gate dielectric layer part on insulating barrier 101 is removed, only retains the gate dielectric layer of topological insulator layer surface.
In a particular embodiment, the material of gate dielectric layer 105 is silica.The method of gate dielectric layer 105 is formed in institute
Chemical vapor deposition silicon oxide layer on insulating barrier 101 is stated, the silicon oxide layer is used as gate dielectric layer.In other embodiments, changing
Learn after vapour deposition silicon oxide layer, etching removes the silicon oxide layer on the silicon oxide layer on insulating barrier, remaining topological insulator layer
It is used as gate dielectric layer.
In a particular embodiment, the material of first grid 106 can be polysilicon.Form the method bag of first grid 106
Include：Chemical vapor deposition polysilicon layer；Graphical polysilicon layer, is developed across the first grid 106 of gate dielectric layer 105.
Reference picture 7, Fig. 8, Fig. 7 are dimensional structure diagrams, and Fig. 8 is the cross-sectional view along Fig. 7 CC directions, point
Not Qu Chu the two ends of fin 102 gate dielectric layer 105 and topological insulator layer 104, there is doping in exposed fin portion surface formation
Epitaxial layer 107, epitaxial layer 107 and first grid 106 separate by remaining gate dielectric layer 105 and topological insulator layer 104,
Epitaxial layer 107 is contacted with adjacent topological insulator layer 104, and the epitaxial layer 107 that the two ends of fin 102 have doping is made respectively
For source electrode, drain electrode.
It should be noted that reference picture 7, the upper surface of the covering fin 102 of epitaxial layer 107 and two relative side, are also covered
Fin 102 perpendicular to fin length direction end face, it is but not shown.
In a particular embodiment, the method for the gate dielectric layer 105 at removal fin 102 two ends and topological insulator layer 104 is
Dry etching.Reference picture 7, removes the fin table that the gate dielectric layer 105 at the two ends of fin 102 not only includes removing the two ends of fin 102
The gate dielectric layer in face, also including removing the fin of exposure in the gate dielectric layer of the both sides perpendicular to fin length direction, exposed portion
Divide insulating barrier.In other embodiments, the gate dielectric layer at removal fin two ends can only remove the fin portion surface at fin two ends
Gate dielectric layer.
In a particular embodiment, the method for forming the epitaxial layer 107 with doping on the exposed surface of fin 102 includes：
In the exposed surface epitaxial growth epitaxial layer of fin 102, in epitaxial growth epitaxial layer, ion note in situ is also carried out
Enter, there is doping in the epitaxial layer 107 ultimately formed.In epitaxial process, insulating barrier 101, first grid 106 and gate medium
Layer 105 plays mask effect, and epitaxial layer 107 only grows along the crystal orientation set direction of fin 102.
In a particular embodiment, according to the material of the type selecting epitaxial layer 107 of fin formula field effect transistor to be formed,
The ionic type of ion implanting in situ.When fin formula field effect transistor to be formed is N-type transistor, the material of epitaxial layer 107
For carbon silicon, the ion of ion implanting in situ is to be doped to n-type doping in N-type ion, epitaxial layer 107；When fin to be formed
Field-effect transistor is P-type transistor, and the material of epitaxial layer 107 is germanium silicon, the ionic type of ion implanting in situ for p-type from
P-type doping is doped in son, epitaxial layer 107.
In the present embodiment, first grid is the grid of preceding grid technique formation, and the material of first grid is DOPOS doped polycrystalline silicon,
The material of gate dielectric layer is silica.In other embodiments, first grid can also be the dummy grid in rear grid technique, first
The material of grid is polysilicon, amorphous carbon or non-crystalline silicon.When first grid is dummy grid, the material of gate dielectric layer is situated between for high K
Material, gate dielectric layer is high-K gate dielectric layer.When gate dielectric layer is high-K gate dielectric layer, formed in fin portion surface selective growth
After topological insulator layer, atomic layer deposition method formation high-K gate dielectric layer is used.
In a particular embodiment, the high K dielectric material is hafnium oxide, zirconium oxide, lanthana, aluminum oxide, tantalum oxide, oxygen
Change titanium, strontium titanates, yittrium oxide, barium strontium, barium titanate, lead titanates scandium, aluminum oxide lanthanum, zinc titanate, zinc niobate lead, nitrogen oxidation
One kind in hafnium, nitrogen oxidation zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen oxidation strontium titanium, nitrogen oxidation lanthanum aluminium, yttrium oxynitride
Or it is a variety of.
Further, after source electrode, drain electrode is formed, formed on the insulating barrier on interlayer dielectric layer, interlayer dielectric layer
Remained basically stable with dummy grid upper surface on surface；Remove dummy grid and form pseudo- gate groove；Second grid is formed in pseudo- gate groove.
In a particular embodiment, the material of the second grid be tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin,
Silver, gold, tantalum nitride, titanium nitride, tungsten nitride, tungsten silicide, ruthenium-oxide, cobalt silicide, nickle silicide, carbon rice receive in pipe, conductive carbon one
Plant or a variety of.
Using the technical scheme of the present embodiment, the fin formula field effect transistor with topological insulator layer is formed.It is different from
Traditional semi-conducting material, topological insulator layer surface is metallic state, and when applying voltage between the source and drain, topology insulate
The carrier of body layer surface moves to form leakage current between the source and drain, fin formula field effect transistor work, topology insulation
Body layer surface is used as channel region.When fin formula field effect transistor works, between first grid and source electrode, or second grid
Apply voltage between source electrode, the electric field that the voltage triggers can adjust the carrier concentration of topological insulator layer surface.It is described
The carrier concentration of topological insulator layer surface, including increase carrier concentration are adjusted, to improve moving for carrier in channel region
Shifting rate；With reduce carrier concentration, with realize close channel region purpose.In a particular embodiment, substrate can also be used as the back of the body
Grid, when fin formula field effect transistor works, also applies voltage, back-gate voltage and the first grid between back grid and source electrode
Pole tension adjusts the carrier concentration of topological insulator layer surface jointly, realizes the more preferable control to fin formula field effect transistor.
In addition, when fin formula field effect transistor works, electron spin direction and the electronics of topological insulator layer surface are transported
There is the relation determined in dynamic direction, for example, when the electronics spun up is to left movement, the downward electronics that spins can only be transported to the right
It is dynamic；Accordingly, when the electronics spun up is moved right, spinning downward electronics can only be to left movement.So along not Tongfang
Taken their own roads to the electronics of motion without interfering, colliding, this improves the mobility of carrier in channel region, and
And energy loss is significantly reduced so that the leakage current between source electrode and drain electrode increases, signal transmission speed in lifting transistor
With the performance of transistor.
Reference picture 7, Fig. 8, the present invention also provide a kind of fin formula field effect transistor, and the fin formula field effect transistor includes：
Substrate 100, the substrate 100 has the protuberance 103 for being higher by the upper surface of substrate 100；
Fin 102 in substrate 100, in the present embodiment, the fin formula field effect transistor also include being located at institute
The insulating barrier 101 in substrate 100 is stated, the protuberance 103 passes through insulating barrier 101, and the thickness of the insulating barrier 101 is less than protrusion
The height in portion 103, is higher by the protuberance part of the upper surface of insulating barrier 101 as fin 102；
The topological insulator layer 104 on the surface of fin 102 of partial-length between the two ends of fin 102；
Gate dielectric layer 105 on topological insulator layer 104；
Across the first grid 106 of gate dielectric layer 105；
It is gate dielectric layer positioned at the epitaxial layer 107 of 102 liang of end surfaces of fin, between epitaxial layer 107 and first grid 106
105 and topological insulator layer 104 separated, there is doping in epitaxial layer 107, positioned at 102 liang of end surfaces of fin with mixing
Miscellaneous epitaxial layer 107 is distributed as source electrode, drain electrode.
In a particular embodiment, the material of the topological insulator layer 104 is Bi2Te3、Bi2Se3Or Sb2Te3。
In a particular embodiment, when fin formula field effect transistor is N-type transistor, the material of epitaxial layer 107 is carbon silicon, outside
Prolong in layer 107 and be doped to n-type doping；When fin formula field effect transistor is P-type transistor, the material of epitaxial layer 107 is germanium silicon,
P-type doping is doped in epitaxial layer 107.
In a particular embodiment, first grid 106 is the grid formed using preceding grid technique, the material of first grid 106
For polysilicon.
In other embodiments, first grid can also be is formed by rear grid technique, then gate dielectric layer is that high K grid are situated between
Matter layer, fin formula field effect transistor also includes the interlayer dielectric layer being located on insulating barrier, and first grid is located in interlayer dielectric layer,
Remained basically stable with interlayer dielectric layer upper surface the first grid upper surface.
In a particular embodiment, the high K dielectric material is hafnium oxide, zirconium oxide, lanthana, aluminum oxide, tantalum oxide, oxygen
Change titanium, strontium titanates, yittrium oxide, barium strontium, barium titanate, lead titanates scandium, aluminum oxide lanthanum, zinc titanate, zinc niobate lead, nitrogen oxidation
One kind in hafnium, nitrogen oxidation zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen oxidation strontium titanium, nitrogen oxidation lanthanum aluminium, yttrium oxynitride
Or it is a variety of.
In a particular embodiment, the material of the first grid be tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin,
Silver, gold, tantalum nitride, titanium nitride, tungsten nitride, tungsten silicide, ruthenium-oxide, cobalt silicide, nickle silicide, carbon rice receive in pipe, conductive carbon one
Plant or a variety of.
In the present embodiment, the material of insulating barrier 101 is silica, silicon nitride or silicon oxynitride, and the material of substrate 100 is
Highly doped silicon.In other embodiments, the substrate can also be silicon-on-insulator substrate, and the silicon-on-insulator substrate includes
Bottom silicon layer, the insulating barrier on bottom silicon layer, the top silicon layer on insulating barrier, the fin are graphical top silicon
What layer was formed.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (22)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
Substrate is provided, fin is formed with the substrate；
In fin portion surface selective growth topological insulator layer；
Gate dielectric layer is formed, the gate dielectric layer Overlay Topology insulator layer is developed across the first grid of the gate dielectric layer；
The gate dielectric layer and topological insulator layer at the fin two ends are removed, in exposed fin portion surface formation with the outer of doping
Prolong layer, separated between the epitaxial layer and first grid by remaining gate dielectric layer and topological insulator layer, the fin two
Epitaxial layer of the end with doping is respectively as source electrode, drain electrode.
2. forming method as claimed in claim 1, it is characterised in that the material of the topological insulator layer is Bi2Te3、
Bi2Se3Or Sb2Te3。
3. forming method as claimed in claim 2, it is characterised in that the method for the selective growth topological insulator layer is
Molecular beam epitaxial growth.
4. forming method as claimed in claim 3, it is characterised in that the molecular beam epitaxial growth process is located at vacuum environment
In, the pressure range of the vacuum environment is 10-7~10-10Torr；The temperature range of vacuum environment is 150~250 DEG C.
5. forming method as claimed in claim 1, it is characterised in that the gate dielectric layer and topology for removing the fin two ends are exhausted
The method of edge body layer is dry etching.
6. forming method as claimed in claim 1, it is characterised in that in exposed extension of the fin portion surface formation with doping
The method of layer includes：
Epitaxial layer is epitaxially-formed in exposed fin portion surface, in epitaxial growth epitaxial layer, ion implanting in situ is also carried out,
Form the epitaxial layer with doping.
7. forming method as claimed in claim 1, it is characterised in that the material of the epitaxial layer is carbon silicon, the epitaxial layer
In be doped to n-type doping；Or,
The material of the epitaxial layer is that the p-type that is doped in germanium silicon, the epitaxial layer is adulterated.
8. forming method as claimed in claim 1, it is characterised in that the first grid is the grid formed in preceding grid technique
Pole.
9. forming method as claimed in claim 1, it is characterised in that the first grid is the dummy grid in rear grid technique,
The gate dielectric layer is high-K gate dielectric layer；
After source electrode, drain electrode is formed, interlayer dielectric layer, the interlayer dielectric layer upper surface and dummy grid are formed on the substrate
Upper surface maintains an equal level；
Remove the dummy grid and form pseudo- gate groove；
Second grid is formed in the pseudo- gate groove.
10. forming method as claimed in claim 9, it is characterised in that the material of the high-K gate dielectric layer is hafnium oxide, oxygen
Change zirconium, lanthana, aluminum oxide, tantalum oxide, titanium oxide, strontium titanates, yittrium oxide, barium strontium, barium titanate, lead titanates scandium, oxidation
Aluminium lanthanum, zinc titanate, zinc niobate lead, nitrogen oxidation hafnium, nitrogen oxidation zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen oxidation strontium titanium,
One or more in nitrogen oxidation lanthanum aluminium, yttrium oxynitride.
11. forming method as claimed in claim 10, it is characterised in that the method for the formation gate dielectric layer is atomic layer deposition
Product.
12. forming method as claimed in claim 9, it is characterised in that the material of the second grid be tungsten, titanium, tantalum, ruthenium,
Zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver, gold, tantalum nitride, titanium nitride, tungsten nitride, tungsten silicide, ruthenium-oxide, cobalt silicide, nickle silicide,
The one or more that carbon rice is received in pipe, conductive carbon.
13. forming method as claimed in claim 1, it is characterised in that forming the method for the fin includes：
The graphical substrate, forms the protuberance for being higher by the substrate surface；
The insulation material layer upper surface formed on the substrate in insulation material layer, the substrate is higher than projections top surface,
Or the insulation material layer upper surface in the substrate maintains an equal level with projections top surface；
The insulation material layer is etched back to, the insulation material layer of segment thickness is removed, residual insulator material layer is high as insulating barrier
Protuberance in insulating barrier upper surface is used as fin.
14. forming method as claimed in claim 13, it is characterised in that the material of the insulating barrier is silica, silicon nitride
Or silicon oxynitride.
15. forming method as claimed in claim 1, it is characterised in that the substrate is silicon-on-insulator substrate, the insulation
Silicon base includes on body：Bottom silicon layer, the insulating barrier on the bottom silicon layer, the top silicon on the insulating barrier
Layer；
Forming the method for the fin includes：The graphical top silicon layer formation fin.
16. a kind of fin formula field effect transistor, it is characterised in that including：
Substrate；
Fin in the substrate；
The topological insulator layer of the fin portion surface of partial-length between fin two ends；
Gate dielectric layer on topological insulator layer；
Across the grid of the gate dielectric layer；
It is gate dielectric layer and topological insulator layer between the epitaxial layer and grid positioned at the epitaxial layer of the end surfaces of fin two
Separated, in the epitaxial layer have doping, positioned at the end surfaces of fin two have doping epitaxial layer respectively as
Source electrode, drain electrode.
17. fin formula field effect transistor as claimed in claim 16, it is characterised in that the material of the topological insulator layer is
Bi2Te3、Bi2Se3Or Sb2Te3。
18. fin formula field effect transistor as claimed in claim 16, it is characterised in that the material of the epitaxial layer is carbon silicon,
N-type doping is doped in the epitaxial layer；The material of the epitaxial layer is that the p-type that is doped in germanium silicon, the epitaxial layer is mixed
It is miscellaneous.
19. fin formula field effect transistor as claimed in claim 16, it is characterised in that the material of the grid is polysilicon.
20. fin formula field effect transistor as claimed in claim 16, it is characterised in that the gate dielectric layer is high-K gate dielectric
Layer, the fin formula field effect transistor also includes the interlayer dielectric layer being located in substrate, and the grid is located in interlayer dielectric layer,
The gate upper surface maintains an equal level with interlayer dielectric layer upper surface.
21. fin formula field effect transistor as claimed in claim 20, it is characterised in that the material of the high-K gate dielectric layer is
Hafnium oxide, zirconium oxide, lanthana, aluminum oxide, tantalum oxide, titanium oxide, strontium titanates, yittrium oxide, barium strontium, barium titanate, metatitanic acid
Lead scandium, aluminum oxide lanthanum, zinc titanate, zinc niobate lead, nitrogen oxidation hafnium, nitrogen oxidation zirconium, nitrogen oxidation lanthanum, aluminum oxynitride, titanium oxynitrides, nitrogen
One or more in strontium oxide strontia titanium, nitrogen oxidation lanthanum aluminium, yttrium oxynitride.
22. fin formula field effect transistor as claimed in claim 20, it is characterised in that the material of the grid be tungsten, titanium,
Tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver, gold, tantalum nitride, titanium nitride, tungsten nitride, tungsten silicide, ruthenium-oxide, cobalt silicide, silicon
Change nickel, the one or more that carbon rice is received in pipe, conductive carbon.
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| US10134915B2 (en) * | 2016-12-15 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | 2-D material transistor with vertical structure |
| CN108493234A (en) * | 2018-05-10 | 2018-09-04 | 广东省半导体产业技术研究院 | A kind of gallium oxide vertical field-effect transistor of fin raceway groove and preparation method thereof |
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