CN113517348B - Direct band gap GeSn enhanced nMOS device and preparation method thereof - Google Patents
Direct band gap GeSn enhanced nMOS device and preparation method thereof Download PDFInfo
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- 229910005898 GeSn Inorganic materials 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 40
- 229910002058 ternary alloy Inorganic materials 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 22
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 19
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 19
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 216
- 238000000151 deposition Methods 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 17
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 8
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 7
- 238000001953 recrystallisation Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000001816 cooling Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
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- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000013077 target material Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 4
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- 239000004065 semiconductor Substances 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 125000005842 heteroatom Chemical group 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a direct band gap GeSn enhanced nMOS device, which comprises: the device comprises a substrate layer, a Ge virtual substrate, a modulated Ge doped epitaxial layer, an intrinsic Ge isolation layer, an nMOS channel layer, an intrinsic ternary alloy heterogeneous cap layer, a hafnium oxide layer, a tantalum nitride layer, a source drain region, a dielectric layer, a source electrode, a drain electrode and a passivation layer; the hafnium oxide layer and the tantalum nitride layer form a gate region; the material of the intrinsic ternary alloy heterogeneous cap layer is Si x Ge 1‑x‑y Sn y The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1; the nMOS channel layer is intrinsic DR-Ge 1‑z Sn z A layer; wherein z ranges from 0.12 to 0.18. The invention also provides a preparation method of the direct band gap GeSn enhanced nMOS device. The device solves the problem that the channel on the surface of the Ge-based channel enhanced nMOS is not inverted, eliminates the Fermi pinning effect of the channel region caused by interface states, is beneficial to the opening of the channel of the device, adopts high electron mobility DR-GeSn as a channel material, and has no surface roughness scattering and ionization impurity scattering of electrons when the channel region is transported, so that the performance index of the device is excellent.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a direct band gap GeSn enhanced nMOS device and a preparation method thereof.
Background
Since the advent of integrated circuits, advanced high-speed evolution has been under moore's law. However, with the rapid development of microelectronics technology, feature sizes of Si MOS devices are continuously shrinking, and integrated circuits are approaching their physical and process limits. Therefore, under the current state of the art, the development of new channel materials for MOS or new MOS device structures has become an important technological approach to continue to maintain moore's law.
The Ge semiconductor is an indirect bandgap semiconductor, and can be converted into a direct bandgap GeSn semiconductor, namely DR-GeSn, through Sn alloying modification. The DR-GeSn electron mobility is high, about 2 times that of Ge semiconductor and 4 times that of Si semiconductor. The application of Ge or DR-GeSn as the channel material of the nMOS device greatly improves the performance of the nMOS device and has important application potential and value in the field of integrated circuits.
However, no matter the Ge semiconductor or DR-GeSn is used for manufacturing the channel material of the enhanced surface channel nMOS device, the interface characteristic between the Ge-based channel enhanced nMOS gate dielectric and the P-type Ge-based semiconductor is poor, the Fermi pinning effect caused by the interface state causes that the Ge-based enhanced surface channel nMOS channel cannot be opened reversely, and the performance of the high-performance enhanced surface channel nMOS device is greatly limited.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a direct band gap GeSn enhancement type nMOS device and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
a first aspect of an embodiment of the present invention provides a direct bandgap GeSn-enhanced nMOS device, comprising: the device comprises a substrate layer, a Ge virtual substrate, a modulated Ge doped epitaxial layer, an intrinsic Ge isolation layer, an nMOS channel layer, an intrinsic ternary alloy heterogeneous cap layer, a hafnium oxide layer, a tantalum nitride layer, a source drain region, a dielectric layer, a source electrode, a drain electrode and a passivation layer;
the substrate layer, the Ge virtual substrate, the modulated Ge doped epitaxial layer, the intrinsic Ge isolation layer, the nMOS channel layer and the intrinsic ternary alloy heterogeneous cap layer are sequentially arranged from bottom to top;
the hafnium oxide layer is positioned on the intrinsic ternary alloy heterogeneous cap layer, the tantalum nitride layer is positioned on the hafnium oxide layer, and the hafnium oxide layer and the tantalum nitride layer form a gate region;
the source/drain region is positioned in the Ge virtual substrate, the modulated Ge doped epitaxial layer, the intrinsic Ge isolation layer, the nMOS channel layer and the intrinsic ternary alloy heterogeneous cap layer;
the dielectric layer is positioned on the intrinsic ternary alloy heterogeneous cap layer, the source electrode and the drain electrode are positioned on the dielectric layer and are positioned on two sides of the gate region;
the passivation layer is covered on the source electrode, the drain electrode and the dielectric layer;
the intrinsic ternary alloy heterogeneous cap layer is made of Si x Ge 1-x-y Sn y The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1;
the nMOS channel layer is intrinsic DR-Ge 1-z Sn z A layer; wherein z ranges from 0.12 to 0.18.
In one embodiment of the invention, the thickness of the modulated Ge doped epitaxial layer is 3-5 nm, and the doping concentration is 1 multiplied by 10 15 ～1×10 19 cm -3 。
In one embodiment of the invention, the intrinsic Ge isolating layer has a thickness of 10-15 nm.
In one embodiment of the present invention, the nMOS channel layer has a thickness of 10 to 20nm.
In one embodiment of the invention, the thickness of the intrinsic ternary alloy heterogeneous cap layer is 4-6 nm.
A second aspect of an embodiment of the present invention provides a method for manufacturing a direct bandgap GeSn-enhanced nMOS device, including the steps of:
step 101, selecting a substrate: selecting single crystal Si as a substrate layer;
102, preparing a Ge virtual substrate by using a laser recrystallization method;
step 103, depositing a modulated Ge doped epitaxial layer on the surface of the Ge virtual substrate;
104, depositing an intrinsic Ge isolating layer on the surface of the modulated Ge doped epitaxial layer in a vacuum environment;
step 105, depositing intrinsic direct band gap Ge on the surface of the intrinsic Ge isolating layer in a vacuum environment 1-z Sn z Forming an nMOS channel layer; wherein z ranges from 0.12 to 0.18;
step 106, depositing intrinsic on the surface of the nMOS channel layer in a vacuum environmentSi x Ge 1-x-y Sn y Forming an intrinsic ternary alloy heterogeneous cap layer, wherein x ranges from 0.1 to 0.15, and y ranges from 0.08 to 0.1;
step 107, sequentially depositing a hafnium oxide layer and a tantalum nitride layer on the surface of the intrinsic ternary alloy heterogeneous cap layer, and forming a gate region;
step 108, depositing a protective layer and etching the protective layer except the gate region;
step 109, performing P-type ion implantation on the surface to form a source drain region;
step 110, depositing a dielectric layer on the surface, and forming a source electrode and a drain electrode on the dielectric layer;
and 111, depositing a passivation layer on the surface.
In one embodiment of the present invention, the specific steps of step 102 include:
step 1021, cleaning the substrate layer by using an RCA method, and then cleaning by using 10% hydrofluoric acid to remove the surface oxide layer of the substrate layer;
1022, using magnetic control sputtering method to make the intrinsic Ge target material with 99.999% purity 1.5X10 at 400-500 deg.C -3 The process pressure of mb and the deposition rate of 5nm/min are sputtered and deposited on the substrate layer, and a Ge epitaxial layer film with the thickness of 200-300 nm is deposited;
step 1023, depositing a first SiO with the thickness of 100nm on the Ge epitaxial layer film by using a CVD process of a chemical vapor deposition method 2 A layer;
1024, heating the material prepared in 1023 to 600-650 ℃;
step 1025, laser recrystallization: the material prepared in step 1024 is scanned by a continuous laser, wherein the laser wavelength is 808nm and the laser power density is 2.1kW/cm 2 The laser spot size is 10mm multiplied by 1mm, and the laser moving speed is 20mm/s;
1026, naturally cooling the material prepared in step 1025, and etching the first SiO by using a dry etching process 2 And (5) a layer, namely obtaining the Ge virtual substrate.
In one embodiment of the inventionIn the embodiment, in the step 103, the thickness of the modulated Ge-doped epitaxial layer is 3-5 nm, and the doping concentration is 1×10 15 ～1×10 19 cm -3 。
In one embodiment of the present invention, the specific steps of step 110 include:
1101, depositing BPSG of 20-30 nm to form a dielectric layer;
step 1102, etching BPSG with nitric acid and hydrofluoric acid to form source-drain contact holes;
step 1103, depositing a 10-20 nm thick metal nickel Ni layer around the source-drain contact hole by utilizing electron beam evaporation;
and 1104, etching the metal Ni by using an etching process to form a source electrode and a drain electrode.
The invention has the beneficial effects that:
1. the device solves the problem that the channel on the surface of the Ge-based channel enhanced nMOS is not inverted, and the existence of the intrinsic ternary alloy heterogeneous cap layer avoids the direct contact between the gate region and the channel layer on one hand, thereby eliminating the Fermi pinning effect of the channel region caused by interface states and facilitating the opening of the channel of the device; on the other hand, under the field induction action of the gate voltage and the single-side high barrier blocking action formed by the band offset of the intrinsic ternary alloy heterogeneous cap layer and the deep delta EC conduction band of the channel layer, electrons from the modulated Ge doped epitaxial layer are limited to the channel region and accumulated to form an open channel, so that the Ge-based enhanced nMOS device is realized.
2. When electrons are transported through the nMOS channel layer of the device, the mobility of electrons in the channel is further improved, and the performance of the device is correspondingly enhanced because of no surface roughness scattering (the nMOS channel layer is not in direct contact with a gate dielectric) and ionized impurity scattering (an ionized impurity non-movable charge is positioned on a modulated Ge doped epitaxial layer); the intrinsic ternary alloy heterogeneous cap layer is a ternary alloy with high Ge component, and the Fermi pinning effect enables the layer to be incapable of forming a parasitic channel, so that the subsequent circuit application is facilitated; the whole device is realized on a Si substrate, is compatible with a Si process, and is beneficial to integration and cost control.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 to fig. 22 are process diagrams of a preparation process of a direct bandgap GeSn-enhanced nMOS device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 22, a first aspect of an embodiment of the present invention provides a direct bandgap GeSn-enhanced nMOS device, comprising: the semiconductor device comprises a substrate layer 1, a Ge virtual substrate 4, a modulated Ge doped epitaxial layer 5, an intrinsic Ge isolation layer 6, an nMOS channel layer 7, an intrinsic ternary alloy heterogeneous cap layer 8, a hafnium oxide layer 9, a tantalum nitride layer 10, a source drain region 14, a dielectric layer 15, a source electrode 17, a drain electrode 18 and a passivation layer 19. The substrate layer 1, the Ge virtual substrate 4, the modulated Ge doped epitaxial layer 5, the intrinsic Ge isolating layer 6, the nMOS channel layer 7 and the intrinsic ternary alloy heterogeneous cap layer 8 are sequentially arranged from bottom to top.
A hafnium oxide layer 9 is located on the intrinsic ternary alloy hetero-cap layer 8, a tantalum nitride layer 10 is located on the hafnium oxide layer 9, and the hafnium oxide layer 9 and the tantalum nitride layer 10 form a gate region. The source drain region 14 is located in the Ge virtual substrate 4, the modulated Ge doped epitaxial layer 5, the intrinsic Ge isolating layer 6, the nMOS channel layer 7 and the intrinsic ternary alloy heterogeneous cap layer 8. A dielectric layer 15 is located on the intrinsic ternary alloy hetero cap layer 8, and a source electrode 17 and a drain electrode 18 are located on the dielectric layer 15 and on both sides of the gate region. The source electrode 17, the drain electrode 18 and the dielectric layer 15 are covered with a passivation layer 19.
The material of the intrinsic ternary alloy heterogeneous cap layer 8 is Si x Ge 1-x-y Sn y The method comprises the steps of carrying out a first treatment on the surface of the Wherein x ranges from 0.1 to 0.15 and y ranges from 0.08 to 0.1. The nMOS channel layer 7 is intrinsic DR-Ge 1-z Sn z A layer; wherein z ranges from 0.12 to 0.18.
In this embodiment, high electron mobility DR-GeSn is used as the material of the nMOS channel layer 7, an intrinsic ternary alloy heterogeneous cap layer 8 is inserted between the nMOS channel layer 7 and the gate region, the forbidden band width of the intrinsic ternary alloy heterogeneous cap layer 8 is larger than the forbidden band width of DR-GeSn, and the intrinsic ternary alloy heterogeneous cap layer 8 and the nMOS channel layer 7 form a deep regionΔE C Conduction band bias heterojunction, field sensing at gate voltage, and deep ΔE C Under the single-side high barrier effect formed by the conduction band bias, electrons from the modulated Ge-doped epitaxial layer 5 are limited to a channel region and accumulated to form an open channel. The unilateral high barrier quantum confinement channel eliminates the Fermi pinning effect of the channel region caused by interface states, realizes the Ge-based enhanced nMOS device,
meanwhile, an intrinsic ternary alloy heterogeneous cap layer 8 is inserted between the nMOS channel layer 7 and the gate region, and parasitic channels cannot be formed on the layer due to the Fermi pinning effect, so that subsequent circuit application is facilitated. The high electron mobility DR-GeSn material of the nMOS channel layer 7 and electrons have no surface roughness scattering and ionized impurity scattering when the device works, and the performance indexes such as the driving capability of the device are excellent.
Further, the Ge doped epitaxial layer 5 is modulated to have a thickness of 3-5 nm and a doping concentration of 1×10 15 ～1×10 19 cm -3 。
Preferably, the specific doping concentration depends on the threshold voltage requirements according to the actual needs.
Further, the thickness of the intrinsic Ge isolating layer 6 is 10 to 15nm.
Further, the thickness of the nMOS channel layer 7 is 10 to 20nm.
Further, the thickness of the intrinsic ternary alloy heterogeneous cap layer 8 is 4-6 nm.
Example two
A second aspect of an embodiment of the present invention provides a method for manufacturing a direct bandgap GeSn-enhanced nMOS device, including the steps of:
step 101, selecting a substrate: single crystal Si was selected as the substrate layer 1 as shown in fig. 1.
Step 102, preparing the Ge virtual substrate 4 by using a laser recrystallization method. The specific steps of step 102 include:
step 1021, cleaning the substrate layer 1 by using an RCA method, and then cleaning by using 10% hydrofluoric acid to remove the surface oxide layer of the substrate layer 1.
Step 1022, adopting a magnetron sputtering method to obtain the product with purity at 400-500 DEG C99.999% intrinsic Ge target material at 1.5X10 -3 The process pressure of mb and the deposition rate of 5nm/min are sputtered and deposited on the substrate layer 1, and the Ge epitaxial layer film 2 with the thickness of 200-300 nm is deposited, as shown in figure 2.
Step 1023, depositing a silicon dioxide protective layer: depositing a first SiO with a thickness of 100nm on the Ge epitaxial layer film 2 by using a CVD process of a chemical vapor deposition method 2 Layer 3, as shown in fig. 3.
Step 1024, heating the material prepared in step 1023 to 600-650 ℃.
Step 1025, laser recrystallization: the material prepared in step 1024 is scanned by a continuous laser, wherein the laser wavelength is 808nm and the laser power density is 2.1kW/cm 2 The laser spot size is 10mm multiplied by 1mm, and the laser moving speed is 20mm/s;
1026, naturally cooling the material prepared in 1025, and etching the first SiO by dry etching 2 Layer 3, a Ge virtual substrate 4 is obtained, as shown in fig. 4.
The continuous laser irradiation causes melting and recrystallization after cooling of the Ge epilayer film 2, which greatly reduces the dislocation density of the epilayer.
Step 103, depositing a modulated Ge doped epitaxial layer 5 on the surface of the Ge virtual substrate 4, as shown in fig. 5. An N-type Ge layer with the thickness of 3-5 nm is deposited on the surface of the Ge virtual substrate 4 by utilizing a Molecular Beam Epitaxy (MBE) process to form a modulated Ge doped epitaxial layer 5, and the doping concentration is 1 multiplied by 10 15 ～1×10 19 cm -3 (the specific doping concentration depends on the threshold voltage requirements).
And 104, depositing an intrinsic Ge isolation layer 6 with the thickness of 10-15 nm on the surface of the modulated Ge doped epitaxial layer 5 by utilizing an MBE process in a vacuum environment, as shown in figure 6.
Step 105, depositing the intrinsic direct band gap Ge with the thickness of 10-20 nm on the surface of the intrinsic Ge isolating layer 6 by utilizing an MBE process in a vacuum environment 1-z Sn z An nMOS channel layer 7 is formed as shown in fig. 7; wherein z ranges from 0.12 to 0.18.
Step 106, depositing on the surface of the nMOS channel layer 7 by MBE process in vacuum environmentIntrinsic Si with thickness of 4-6 nm x Ge 1-x-y Sn y The intrinsic ternary alloy hetero cap layer 8 is formed, as shown in FIG. 8, wherein x ranges from 0.1 to 0.15, y ranges from 0.08 to 0.1, and the intrinsic ternary alloy hetero cap layer 8 forms a deep ΔE with the nMOS channel layer 7 C Conduction band bias heterojunction.
And 107, sequentially depositing a hafnium oxide layer 9 and a tantalum nitride layer 10 on the surface of the intrinsic ternary alloy heterogeneous cap layer 8, and forming a gate region. The specific steps of step 107 include:
step 1071, depositing a 3nm thick hafnium oxide layer 9 (HfO) by atomic layer deposition at 250-300 DEG C 2 ) As shown in FIG. 9, the reaction precursor is [ CH ] 3 C 2 H 5 N] 4 Hf, oxidant H 2 O。
Step 1072, a tantalum nitride layer 10 (TaN) having a thickness of 110nm is deposited on the hafnium oxide using a reactive sputtering system, as shown in FIG. 10.
Step 1073, selectively etching out TaN-HfO in the designated area by using etching process 2 A gate region of nMOS is formed as in fig. 11.
Step 108, depositing a protective layer and etching the protective layer except the gate region. The specific steps of step 108 include:
step 1081 depositing a second SiO layer having a thickness of about 10nm on the surface of the material prepared in step 1073 2 Layer 11, as shown in fig. 12.
Step 1082, depositing Si with thickness of 20-30 nm by CVD method 3 N 4 Layer 12 acts as a sacrificial protective layer, as shown in fig. 13, which serves to protect the gate from damage during the source drain region 14 region etch and additionally does not affect the self-aligned process of source drain ion implantation.
Step 1083 etching the second SiO except the gate 2 Layer 11 and Si 3 N 4 Layer 12, as shown in fig. 14.
And 109, performing P-type ion implantation on the surface to form a source drain region 14. The specific steps of step 109 include:
step 1091, photolithography, gumming and selective area exposure. The photoresist 13 remains in the center and the photoresist around is removed as shown in fig. 15.
Step 1092, performing P-type ion implantation on the entire surface by using a self-aligned process, and performing rapid annealing at 250-300 ℃ in a nitrogen atmosphere to form a source drain region 14 of the NMOS, as shown in fig. 16.
Step 1093, removing the photoresist 13 and removing the second SiO covered by the gate by wet etching 2 Layer 11 and Si 3 N 4 Layer 12, as shown in fig. 17.
Step 110, depositing a dielectric layer 15 on the surface, and forming a source electrode 17 and a drain electrode 18 on the dielectric layer 15. The specific steps of step 110 include:
step 1101, depositing 20-30 nm BPSG by CVD method to form dielectric layer 15, as shown in FIG. 18. BPSG can trap mobile ions to prevent them from diffusing to the gate and compromising device performance.
Step 1102, BPSG is etched with nitric acid and hydrofluoric acid to form source drain contact holes, as shown in FIG. 19.
In step 1103, a 10-20 nm thick nickel-metal Ni layer 16 is deposited around the source-drain contact hole by electron beam evaporation, as shown in FIG. 20, so as to form good ohmic contact with the source-drain surface intrinsic ternary alloy heterogeneous cap layer 8.
Step 1104, selectively etching away the metal nickel Ni layer 16 in the designated area by using an etching process to form a source electrode 17 and a drain electrode 18, as shown in fig. 21.
Step 111, depositing SiN material with the thickness of 20-30 nm on the surface of the device prepared in step 1104 by using a CVD process for passivating dielectrics to form a passivation layer 19, and finally forming the single-side high barrier quantum confinement channel direct band gap GeSn enhanced nMOS device as shown in FIG. 22.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (9)
1. A direct bandgap GeSn-enhanced nMOS device, comprising: the device comprises a substrate layer (1), a Ge virtual substrate (4), a modulated Ge doped epitaxial layer (5), an intrinsic Ge isolation layer (6), an nMOS channel layer (7), an intrinsic ternary alloy heterogeneous cap layer (8), a hafnium oxide layer (9), a tantalum nitride layer (10), a source drain region (14), a dielectric layer (15), a source electrode (17), a drain electrode (18) and a passivation layer (19);
the substrate layer (1), the Ge virtual substrate (4), the modulated Ge doped epitaxial layer (5), the intrinsic Ge isolating layer (6), the nMOS channel layer (7) and the intrinsic ternary alloy heterogeneous cap layer (8) are sequentially arranged from bottom to top;
the hafnium oxide layer (9) is positioned on the intrinsic ternary alloy heterogeneous cap layer (8), the tantalum nitride layer (10) is positioned on the hafnium oxide layer (9), and the hafnium oxide layer (9) and the tantalum nitride layer (10) form a gate region;
the source-drain region (14) is positioned in the Ge virtual substrate (4), the modulated Ge doped epitaxial layer (5), the intrinsic Ge isolating layer (6), the nMOS channel layer (7) and the intrinsic ternary alloy heterogeneous cap layer (8);
the dielectric layer (15) is positioned on the intrinsic ternary alloy heterogeneous cap layer (8), and the source electrode (17) and the drain electrode (18) are positioned on the dielectric layer (15) and are positioned on two sides of the gate region;
the source electrode (17), the drain electrode (18) and the dielectric layer (15) are covered with the passivation layer (19);
the material of the intrinsic ternary alloy heterogeneous cap layer (8) is Si x Ge 1-x-y Sn y The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1;
the nMOS channel layer (7) is intrinsic DR-Ge 1-z Sn z A layer; wherein z ranges from 0.12 to 0.18.
2. The direct bandgap GeSn-enhanced nMOS device of claim 1, wherein said modulated Ge-doped epitaxial layer (5) has a thickness of 3-5 nm and a doping concentration of 1 x 10 15 ～1×10 19 cm -3 。
3. A direct bandgap GeSn-enhanced nMOS device according to claim 1, wherein the intrinsic Ge spacer (6) has a thickness of 10-15 nm.
4. A direct bandgap GeSn-enhanced nMOS device according to claim 1, wherein the nMOS channel layer (7) has a thickness of 10-20 nm.
5. A direct bandgap GeSn-enhanced nMOS device according to claim 1, wherein the thickness of the intrinsic ternary alloy hetero-cap layer (8) is 4-6 nm.
6. The preparation method of the direct band gap GeSn enhancement type nMOS device is characterized by comprising the following steps of:
step 101, selecting a substrate: selecting single crystal Si as a substrate layer (1);
102, preparing a Ge virtual substrate (4) by using a laser recrystallization method;
step 103, depositing a modulated Ge doped epitaxial layer (5) on the surface of the Ge virtual substrate (4);
104, depositing an intrinsic Ge isolating layer (6) on the surface of the modulated Ge doped epitaxial layer (5) in a vacuum environment;
step 105, depositing intrinsic direct band gap Ge on the surface of the intrinsic Ge isolating layer (6) in a vacuum environment 1-z Sn z Forming an nMOS channel layer (7); wherein z ranges from 0.12 to 0.18;
step 106, depositing intrinsic Si on the surface of the nMOS channel layer (7) in a vacuum environment x Ge 1-x-y Sn y Forming an intrinsic ternary alloy heterogeneous cap layer (8), wherein x ranges from 0.1 to 0.15, and y ranges from 0.08 to 0.1;
step 107, sequentially depositing a hafnium oxide layer (9) and a tantalum nitride layer (10) on the surface of the intrinsic ternary alloy heterogeneous cap layer (8), and forming a gate region;
step 108, depositing a protective layer and etching the protective layer except the gate region;
step 109, performing P-type ion implantation on the surface to form a source-drain region (14);
step 110, depositing a dielectric layer (15) on the surface, and forming a source electrode (17) and a drain electrode (18) on the dielectric layer (15);
and step 111, depositing a passivation layer (19) on the surface.
7. The method for fabricating a direct bandgap GeSn-enhanced nMOS device of claim 6, wherein said step 102 comprises the specific steps of:
step 1021, cleaning the substrate layer (1) by using an RCA method, and then cleaning by using 10% hydrofluoric acid to remove the surface oxide layer of the substrate layer (1);
1022, using magnetic control sputtering method to make the intrinsic Ge target material with 99.999% purity 1.5X10 at 400-500 deg.C -3 The process pressure of mb and the deposition rate of 5nm/min are sputtered and deposited on the substrate layer (1), and a Ge epitaxial layer film (2) with the thickness of 200-300 nm is deposited;
step 1023, depositing a first SiO with the thickness of 100nm on the Ge epitaxial layer film (2) by using a CVD process of a chemical vapor deposition method 2 A layer (3);
1024, heating the material prepared in 1023 to 600-650 ℃;
step 1025, laser recrystallization: the material prepared in step 1024 is scanned by a continuous laser, wherein the laser wavelength is 808nm and the laser power density is 2.1kW/cm 2 The laser spot size is 10mm multiplied by 1mm, and the laser moving speed is 20mm/s;
1026, naturally cooling the material prepared in step 1025, and etching the first SiO by using a dry etching process 2 And (3) a Ge virtual substrate (4) is obtained.
8. The method for fabricating a direct bandgap GeSn-enhanced nMOS device as claimed in claim 6, wherein in said step 103, said modulated Ge-doped epitaxial layer (5) has a thickness of 3-5 nm and a doping concentration of 1×10 15 ～1×10 19 cm -3 。
9. The method of fabricating a direct bandgap GeSn-enhanced nMOS device of claim 6, wherein the specific steps of step 110 include:
1101, depositing BPSG of 20-30 nm to form a dielectric layer (15);
step 1102, etching BPSG with nitric acid and hydrofluoric acid to form source-drain contact holes;
step 1103, depositing a 10-20 nm thick metal nickel Ni layer (16) around the source-drain contact hole by electron beam evaporation;
step 1104, etching the metal Ni by using an etching process to form a source electrode (17) and a drain electrode (18).
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