JP2000031469A - Semiconductor device and production method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FET transistor having high mobility by using a multi- layer structure consisting of a 4-family semiconductor consisting of Si and Ge. SOLUTION: The FET transistor has a Si substrate; a Si1-XGeX buffer layer (0<x<1) formed on the Si substrate without lattice matching; a Si channel layer formed on the buffer layer; a Si1-XGeX spacer layer (0<x<1) formed on the Si channel layer; a Ge layer doped with 5-family elements such as Sb or the like, which is formed on the spacer layer; a Si1-XGeX cap layer (0<x<1) formed on a delta doped layer; a source area provided at one end of the Si channel layer and a drain area provided at the other end of the Si channel layer; and a gate electrode provide on the cap layer through an insulating film. This n-type FET transistor has a constitution that two dimensional electron gas is generated on the interface of both the Si channel layer and the spacer layer. The mixed crystalline ratio X of the FET transistor is around 0.3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a field effect transistor formed by using a group 4 element of Si and Ge, that is, a high-speed mobility transistor forming a two-dimensional channel. And effective technology applied to the manufacturing technology.

[0002]

2. Description of the Related Art A conventional transistor using Si and Ge (field effect transistor) is disclosed in Extended Abstract of 1993 International.
Conference on solid-state device
And Materials, McHari, 1993, pp 201-203 (Extended Abstravts of the 1993 Internat
ional Conference on Solid State Devices and Materi
als, Makuhari (1993) pp. 201-203).

[0003] The field effect transistor described in this document has a SiGe buffer layer on a Si substrate.
The structure has a Si channel layer and a SiGe layer on the buffer layer. A delta-doped layer (electron supply layer) composed of a single atomic layer doped with sb is provided in the middle of the SiGe layer.

[0004]

In the above-mentioned prior art field effect transistor (high-speed mobility transistor), an impurity-doped SiGe is used as a carrier supply layer for electrons and holes.
A mixed crystal layer is used. The impurity atoms occupy the crystal lattice positions of the semiconductor atoms to form covalent bonds with the semiconductor atoms and supply carriers. However, when an impurity is doped into a mixed crystal layer of SiGe, bonds having different binding energies of impurity-Si and impurity-Ge are formed, and the impurity-
Since the bond energy of the Ge bond is smaller than that of the impurity -Si, the Sb-Si bond is formed preferentially, and around the Ge atom.
There are many broken bonds (unbonded bonds) that are not bonded to Sb, and since these bonds function as carrier trapping centers, the activation rate of Sb is about 1%. The resulting device characteristics were poor.

As described above, the conventional element structure has a low impurity activation rate. Therefore, conventionally, a transistor is manufactured by performing high-concentration doping about two orders of magnitude higher than the carrier concentration. However, a new problem arises in that the carrier mobility is reduced due to the effect of scattering by the high-concentration impurities.

An object of the present invention is to provide a semiconductor device having a field effect transistor having high mobility and a method for manufacturing the same.

Another object of the present invention is to provide a field effect transistor having a mobility that is at least twice as high as that of a conventional device and a method of manufacturing the same. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

(1) An Si substrate and the Si substrate
A Si _1-X Ge _X buffer layer (0 <x <1) formed without lattice matching on the substrate, a Si channel layer formed on the buffer layer, and formed on the Si channel layer A Si _1-X Ge _X spacer layer (0 <x <1), a delta-doped layer composed of a Ge layer doped with a group V element such as Sb formed on the Si _1-X Ge _X spacer layer, Si _1-X Ge _X formed on the layer
A cap layer (0 <x <1), a source region provided at one end of the Si channel layer and a drain region provided at the other end, and provided over the Si _1-X Ge _X cap layer via an insulating film. Having a gate electrode, the Si channel layer and the Si
_The structure has an n-type field effect transistor configured to generate a two-dimensional electron gas at the interface with the _1-X Ge _X spacer layer. The mixed crystal ratio X is about 0.3.

Such a semiconductor device is manufactured by the following method. Si _1-X Ge _X mixed crystal layer (0 <x <1) on Si substrate
Forming a Si _1-X Ge _X buffer layer by growing without lattice matching, and growing an i-Si layer on the Si _1-X Ge _X buffer layer to form a Si channel layer, A Si _1-X Ge _X mixed crystal layer (0 <x <1) is grown on the Si channel layer to form a Si _1-X Ge
Forming a _X spacer layer, the Si _1-X Ge _X a step of the spacer layer on the grown Ge layer doped with Group 5 element such as Sb to form a delta doped layer, Si ₁ on the delta doped layer Forming a Si _1-X Ge _X cap layer by growing a _-X Ge _X mixed crystal layer (0 <x <1); and forming Si on the Si _1-X Ge _X cap layer.
Forming a silicon layer by growing a layer or i-Si layer; forming the silicon layer by thermal oxidation to form a SiO ₂ film; and selectively removing the SiO ₂ film to form an n-type impurity. Forming a source region and a drain region by forming a gate electrode, a source electrode, and a drain electrode on the SiO ₂ film and between the source region and the drain region and on the source region and the drain region. By performing this step, an n-type field effect transistor having a configuration in which a two-dimensional electron gas is generated at the interface between the Si channel layer and the Si _1-x Ge _x spacer layer is manufactured. The Si _1-X Ge _X mixed crystal layer (0 <x <
The mixed crystal ratio X in 1) is controlled to about 0.3.

(2) In the structure of the means (1), the delta-doped layer is constituted by a Si layer doped with a group V element such as Sb. Such a semiconductor device is characterized in that the means (1)
After the formation of the Si _1-X Ge _X spacer layer in the manufacturing method of the above, the Group 1 element such as Sb was doped on the Si _1-X Ge _X spacer layer.
Manufactured by growing a Si layer to form a delta-doped layer.

(3) In the configuration of the means (1), the channel layer is formed of a Ge channel layer instead of the Si channel layer, and the delta-doped layer is formed of B or the like instead of the Ge layer doped with a group V element such as Sb. And a Si layer doped with a Group 3 element. Further, the mixed crystal ratio X of the Si _1-X Ge _X mixed crystal layer (0 <x <1) is 0.3.
It is about 7.

[0012] Such a semiconductor device is characterized in that:
In the manufacturing method, after forming a Si _1-X Ge _X buffer layer and the Si _1-X Ge _X buffer layer is grown i-Ge layer of Ge
A channel layer is formed, and then a Si _1-X Ge _X mixed crystal layer (0 <x <1) is formed to form a Si _1-X Ge _X spacer layer.
It is manufactured by growing a Si layer doped with group elements to form a delta-doped layer. In this production
The mixed crystal ratio X of the Si _1-X Ge _X mixed crystal layer (0 <x <1) is controlled to about 0.7.

(4) In the configuration of the means (1), the channel layer is formed of a Ge channel layer instead of the Si channel layer, and the delta-doped layer is formed of B or the like instead of the Ge layer doped with a group V element such as Sb. And a Ge layer doped with a Group 3 element. Further, the mixed crystal ratio X of the Si _1-X Ge _X mixed crystal layer (0 <x <1) is 0.3.
It is about 7.

[0014] Such a semiconductor device is characterized in that:
In the manufacturing method, after forming a Si _1-X Ge _X buffer layer and the Si _1-X Ge _X buffer layer is grown i-Ge layer of Ge
A channel layer is formed, and then a Si _1-X Ge _X mixed crystal layer (0 <x <1) is formed to form a Si _1-X Ge _X spacer layer.
It is manufactured by growing a Ge layer doped with a group element to form a delta-doped layer. In this production
The mixed crystal ratio X of the Si _1-X Ge _X mixed crystal layer (0 <x <1) is controlled to about 0.7.

According to the means (1), the bulk lattice constant of the Si _1-X Ge _X mixed crystal layer is determined by the difference in atomic radius between Si and Ge and the Ge lattice constant X together with the lattice constant of Si. To the lattice constant of Ge. When this Si _1-X Ge _X mixed crystal (buffer layer) is grown on a Si substrate, if it is thin, it grows lattice-matched to the Si substrate, so it receives biaxial compressive stress from the Si substrate . When the grown film thickness is increased in such a state, strain energy is accumulated in the film in proportion to the film thickness, and dislocation occurs in the film to relax the strain at a certain film thickness (critical film thickness). In this way, dislocations are introduced into the film by growing beyond the critical film thickness, and stress is not applied from the substrate to Si _1-X Ge _X
A mixed crystal (buffer layer) is formed on a Si substrate. Si on it
Layer (Si channel layer) and Si _1-X Ge _X mixed crystal layer (spacer layer)
By growing lattice-matched with the Si _1-X Ge _X buffer layer, 2
An Si layer (Si channel layer) to which the axial tensile stress is applied is formed. The band structure is shown by embedding a Ge layer of about 2 nm doped with a Group 5 impurity such as Sb in the Si _1-X Ge _X mixed crystal of the upper barrier layer (Si _1-X Ge _X spacer layer) of this structure. 1
And electrons are accumulated in the Si channel layer,
A two-dimensional electron gas will be formed. The activation rate of impurities having this structure was almost 100%, and it was possible to manufacture a field-effect transistor having good characteristics. As a result, it has become possible to realize a field effect transistor having a mobility that is at least twice as high as that of the conventional device.

According to the above-mentioned means (2), even when the delta-doped layer is a Si layer doped with a group V element such as Sb, the activation rate of impurities is substantially reduced as in the case of the above-mentioned structure (1). 100%, and a field-effect transistor having good characteristics can be manufactured.

According to the means (3), the channel layer
In the case where the Ge channel layer is formed and the delta-doped layer is formed of a Si layer doped with a Group 3 element such as B, the activation rate of impurities can be made almost 100% as in the case of the above-mentioned (1). It has become possible to manufacture a field-effect transistor having a good quality.

According to the means (4), the channel layer
Also in the case where the Ge channel layer is formed and the delta-doped layer is formed of a Ge layer doped with a group 3 element such as B, the activation rate of impurities can be made almost 100% as in the case of the above-mentioned (1). It has become possible to manufacture a field-effect transistor having a good quality.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIGS. 2 to 5 are diagrams relating to an n-type field effect transistor (high-speed mobility transistor type semiconductor device) according to an embodiment (Embodiment 1) of the present invention.
3 is a schematic cross-sectional view showing a semiconductor device. FIGS. 3 and 4 are schematic cross-sectional views of a Si substrate in each step of manufacturing the semiconductor device.
FIG. 3 is a schematic diagram showing a band structure of a junction portion of the semiconductor device.

As shown in FIG. 2, the semiconductor device 200 of the first embodiment has a structure in which semiconductor layers are sequentially formed on one surface (main surface: (100)) of a p-type Si substrate 211. ing.
The p-type Si substrate 211 is composed of, for example, a substrate having a resistivity of 5Ωcm and a thickness of several hundred μm, and the main surface of the substrate 211 has a thickness of 50 nm.
Is formed. This Si layer 212 may be a genuine semiconductor (i-layer).

On the Si layer 212, the thickness exceeds the critical thickness and becomes 2000 nm,
_{A 1-X} Ge _X buffer layer 213 (0 <x <1) is provided. Said Si
_{The 1-X} Ge _X buffer layer 213 is formed of, for example, a mixed crystal layer having a mixed crystal ratio X of 3, and is an i-Si _0.7 Ge _0.3 buffer layer 213.

On the i-Si _0.7 Ge _0.3 buffer layer 213,
A 20 nm thick genuine semiconductor, and the i-Si _0.7 Ge _0.3
An Si channel layer that receives a biaxial tensile stress by the buffer layer 213, that is, an i-Si channel layer 214 is provided.
On this i-Si channel layer 214, a 10-nm-thick Si _1-X Ge _X spacer layer 215 (0 <x <1) not doped with impurities is provided. The Si _1-X Ge _X spacer layer 215 is formed of a mixed crystal layer having a mixed crystal ratio X of 3 as in the case of the Si _1-X Ge _X buffer layer 213, and is formed on the i-Si _0.7 Ge _0.3 spacer layer 215. Has become.

On the i-Si _0.7 Ge _0.3 spacer layer 215, S
A Ge layer 216 having a thickness of about 2 nm with b-doping is provided. On this Ge layer 216, a Si _1-X Ge _X cap layer 2 having a thickness of 10 nm
17 (0 <x <1) are provided. This Si _1-X Ge _X cap layer 2
Reference numeral 17 denotes a mixed crystal layer having a mixed crystal ratio X of 3 similarly to the Si _1-X Ge _X spacer layer 215, and an i-Si _0.7 Ge _0.3 cap layer 21.
It has become 7.

On the i-Si _0.7 Ge _0.3 cap layer 217,
An SiO ₂ film 220 having a thickness of 5 nm is formed.

Further, the SiO ₂ film 220 is selectively removed, and a part of the removed portion is diffused at a high concentration with an impurity of Group V which becomes an n-type determining impurity, for example, arsenic (As). An impurity implantation region 219 is formed. This impurity-implanted region 219 reaches the surface layer of the i-Si _0.7 Ge _0.3 buffer layer 213 and forms a source region and a drain region of the FET. Therefore, a source region is provided at one end of the i-Si channel layer 214, and a drain region is provided at the other end.

A source electrode 221 is provided on one of the impurity-implanted regions 219, and the other
A drain electrode 222 is provided thereon, and a gate electrode 223 is provided on the SiO ₂ film 220 between the pair of impurity implantation regions 219. Each of the electrodes is formed of, for example, aluminum.

Thus, an n-type field effect transistor (high-speed mobility transistor) configured to generate a two-dimensional electron gas at the interface between the i-Si channel layer 214 and the i-Si _0.7 Ge _0.3 spacer layer 215 is formed. Will be done.

Next, the manufacture of the semiconductor device 200 of the first embodiment will be described. As shown in FIG. 3, the crystal plane of the main surface is (1
(00) is prepared.

Thereafter, the p-type Si substrate 211 is chemically cleaned, and then put into a growth apparatus (MBE apparatus). After surface cleaning, Si is removed from the p-type Si substrate using an Si evaporation source by electron beam heating.
A Si layer 212 is grown to a thickness of 50 nm on the substrate 211 at a substrate temperature of 600 ° C.

Next, a Ge deposition source using heater heating and Si
Simultaneously with the deposition source, furthermore, the undoped i-Si _0.7 Ge _0.3 buffer layer 213 on the Si layer 212 is grown to a thickness of 2000 nm beyond the critical thickness, and is not subjected to stress from the substrate 211. An i-Si _0.7 Ge _0.3 buffer layer 213 is formed.

Next, the i-Si _0.7 Ge _0.3 buffer layer 213 is grown to i-Si channel layer 214 of 20nm on the i-Si _0.7 Ge
_{0.3 The} i-Si channel layer 214 is subjected to biaxial tensile stress from the buffer layer 213.

Next, on the i-Si channel layer 214, a 10-nm i-Si _0.7 Ge _0.3 spacer layer 21 not doped with impurities is formed.
5 is grown in lattice matching with the i-Si channel layer 214. Next, Si and Sb are simultaneously deposited and doped with Sb to a thickness of about 2 nm.
A Ge layer 216 is grown. Next, on the Ge layer 216, i-Si _0.7 G
e A _0.3 nm cap layer 217 is formed. Next, the i-Si _0.7
On the Ge _0.3 cap layer 217, a Si layer 218 is grown to a thickness of 5 nm. S
The i-layer 218 may be an i-Si layer.

Next, the substrate 211 having a multi-layered semiconductor layer formed on the main surface is taken out of the growth apparatus and subjected to a thermal oxidation treatment to change the surface Si layer 218 to a SiO ₂ film 220 as shown in FIG. Let it.

Next, as shown in FIG. 4, the above-described Si
The O ₂ film 220 is selectively removed. Then, arsenic (As) is implanted at a high concentration by a conventional ion implantation technique, and annealing is performed to thereby form the i-Si _0.7 Ge _0.3 buffer layer 21.
A pair of impurity-implanted regions 219 reaching the surface layer 3 is formed. This pair of impurity-implanted regions 219 forms the source region and the drain region of the FET.

Next, a source electrode 221 on the one impurity-implanted region 219 and a drain electrode 222 on the other impurity-implanted region 219 are formed by selective evaporation of aluminum or patterning after the evaporation. A gate electrode 223 is provided on the SiO ₂ film 220 between the impurity implantation regions 219.

Thus, the semiconductor device as shown in FIG.
200 (n using i-Si channel layer 214 as an electron channel
Channel field effect transistor).

The manufacture of the high-speed mobility transistor according to the first embodiment is a schematic description. In practice, a large-diameter Si substrate called a wafer is used. The wafer is divided vertically and horizontally into semiconductor chips. In this semiconductor chip, the above-described high-speed mobility transistor is used alone, or a high-speed mobility transistor and other active elements or passive elements are formed to form circuit elements.

The band structure of the n-channel field-effect transistor (high-speed mobility transistor) according to the first embodiment is as shown in FIG. 5, and the Sb-doped Ge layer 216 forms a barrier layer and is emitted from donor Sb. The electrons immediately move to and accumulate in the electron channel i-Si channel layer 214 to form a two-dimensional electron gas.

According to the first embodiment, the following effects can be obtained. (1) The bulk lattice constant of the Si _1-X Ge _X mixed crystal layer increases from the lattice constant of Si to the lattice constant of Ge with the Ge mixed crystal ratio X due to the difference in the atomic radius of Si and Ge. Therefore, the Si _1-X G
e _X mixed crystal when growing the (buffer layer) on the Si substrate, in order to grow lattice matched to Si substrate when the thickness is thin, Si
It receives biaxial compressive stress from the substrate. When the grown film thickness is increased in such a state, strain energy is accumulated in the film in proportion to the film thickness, and dislocation occurs in the film to relax the strain at a certain film thickness (critical film thickness). By growing beyond the critical film thickness, dislocations are introduced into the film, and a Si _1-X Ge _X mixed crystal (buffer layer) that is not stressed from the substrate can be formed on the Si substrate. .

Further, a Si layer (Si channel layer) and a Si layer
_{The 1-X} Ge _X mixed crystal layer (spacer layer) is grown lattice-matched to the Si _{1- X} Ge _X buffer layer to form a Si layer (Si channel layer) to which biaxial tensile stress is applied. . The band structure is shown by embedding a Ge layer of about 2 nm doped with a Group 5 impurity such as Sb in the Si _1-X Ge _X mixed crystal of the upper barrier layer (Si _1-X Ge _X spacer layer) of this structure. As shown in FIG. 5, a two-dimensional electron gas in which electrons are accumulated in the Si channel layer is formed. The activation rate of impurities of this structure is almost 1
At 00%, a field-effect transistor with good characteristics can be manufactured.

(2) As a result, it has become possible to realize a field effect transistor having a mobility that is at least twice as high as that of a conventional device.

(Embodiment 2) FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 2) of the present invention. FIG. FIG. 4 is a schematic sectional view in which a layer is formed. FIG. 8 is a schematic diagram showing a band structure of a junction portion of the semiconductor device.

In the semiconductor device 300 of the second embodiment, in the structure of the first embodiment, the delta-doped layer is constituted by a Si layer doped with a group V element such as Sb. Such a semiconductor device 300 is obtained by using the Si _1-X
After the Ge _X spacer layer is formed, it is manufactured by growing a Si layer doped with a group V element such as Sb on the Si _1-X Ge _X spacer layer to form a delta-doped layer.

Next, the semiconductor device will be described while explaining the manufacturing method.
The configuration of 300 will be described. As shown in FIG. 7, a p-type Si substrate 311 having a resistivity of 5 Ωcm where the main crystal plane is (100) is provided.
After chemical cleaning of the substrate 31, the substrate is put into a growth apparatus, and after cleaning of the surface,
A substrate temperature of 600 ° C. is grown on 1 to grow an i-Si layer 312 to a thickness of 50 nm.

Next, a Ge vapor deposition source using heater heating and Si
Simultaneously with the evaporation source, further undoped impurity-doped i-Si _0.7 Ge _0.3 buffer layer 313 exceeds the critical film thickness of 2000 nm, no stress from the substrate
An i-Si _0.7 Ge _0.3 buffer layer 313 is formed. 20nm on this
Was grown so that the i-Si _0.7 Ge _0.3 buffer layer 313 Si layer was subjected to biaxial tensile stress. On top of this, no further impurity doping
An i-Si _0.7 Ge _0.3 spacer layer 315 nm is grown in lattice matching with the i-Si channel layer 314.

Next, Si and Sb are simultaneously evaporated to grow a Si layer 316 of about 2 nm doped with Sb. Then i-Si _0.7
The Ge _0.3 cap layer 317 is grown to 10 nm, and the i-Si layer 318 is grown to 5 nm.

Next, as shown in FIG.
The Si layer 318 is oxidized in the same manner as in the above case, and then is subjected to photolithography or ion implantation in a conventional process.
An impurity implantation region 319 (source / drain region) is formed by As implantation, and then a source electrode 321,
A drain electrode 322 and a gate electrode 323 are formed, and a high-speed mobility transistor including an n-channel field effect transistor is formed.

In the case of the element structure of the semiconductor device 300 of the second embodiment, the band structure is as shown in FIG.
The Si layer 316 forms a quantum well, but since the well width is as small as 2 nm, the energy level inside the well is high and Si _0.7 Ge _0.3
Electrons emitted from the donor Sb due to being close to the energy at the bottom of the conduction band of the layer (i-Si _0.7 Ge _0.3 spacer layer 315) are not bound by the energy level inside the well and the electron channel i-Si The two-dimensional electron gas is accumulated in the channel layer 314 and is formed.

As in the semiconductor device 300 of the second embodiment,
Even when the delta-doped layer is a Si layer doped with a group V element such as Sb, the activation rate of impurities can be made almost 100% as in the case of the first embodiment, and a field-effect transistor having good characteristics is manufactured. It became possible. As a result, it has become possible to realize a field effect transistor having a mobility that is at least twice as high as that of the conventional device.

(Embodiment 3) FIG. 9 is a schematic cross-sectional view showing a semiconductor device according to another embodiment (Embodiment 3) of the present invention, and FIG. FIG. 4 is a schematic sectional view in which a layer is formed. Also,
FIG. 11 is a schematic diagram showing a band structure of a junction portion of the semiconductor device.

In the semiconductor device 400 of the third embodiment, in the configuration of the first embodiment, the channel layer is formed of a Ge channel layer instead of the Si channel layer, and the delta-doped layer is formed of Ge doped with a group V element such as Sb. Instead of the layer, it is constituted by a Si layer doped with a group 3 element such as B. In addition, Si _1-X Ge _X mixed crystal layer (0
The mixed crystal ratio X of <x <1) is 0.7. Note that an n-type Si substrate is used as the substrate.

In the semiconductor device 400, the Si _1-X Ge _X buffer layer is formed, the i-Ge channel layer is formed, and the Si _1-X Ge _X spacer layer is formed. Is formed by forming a delta-doped layer with a Si layer doped with a Group 3 element such as B on the Si _1-X Ge _X spacer layer.

Next, the semiconductor device will be described while explaining the manufacturing method.
The configuration of 400 will be described. As shown in FIG. 10, an n-type Si substrate 4 having a resistivity of 5 Ωcm where the main crystal plane is (100).
After chemically cleaning 11, the substrate is put into a growth apparatus, and after surface cleaning, i-Si is grown on the substrate 411 at a substrate temperature of 600 ° C. using a Si evaporation source by electron beam heating, and an i-Si layer 412 is grown to a thickness of 50 nm. I do.

Next, a Ge vapor deposition source using heater heating and Si
Simultaneously with the evaporation source, further undoped impurity-doped i-Si _0.3 Ge _0.7 buffer layer 413 over the critical thickness of 2000 nm, no stress from the substrate
An i-Si _0.3 Ge _0.7 buffer layer 413 is formed. 20nm on this
Is grown so that the i-Ge channel layer 414 receives biaxial compressive stress from the i-Si _0.3 Ge _0.7 buffer layer 413. On this, a 10 nm i-Si _0.3 Ge _0.7 spacer layer 415 not further doped with impurities is grown in lattice matching with the i-Ge channel layer 414.

Next, Si and B are simultaneously vapor-deposited, and a B-doped Si layer 416 of about 2 nm is grown. Then, an i-Si _0.3 Ge _0.7 cap layer 417 is formed thereon with a thickness of 10 nm, and an i-Si layer 418 is formed thereon with a thickness of 5 nm.
Let it grow.

Next, as shown in FIG.
The i-Si layer 418 is oxidized in the same manner as in the above case, and thereafter, an impurity implantation region 419 (source / drain region) is formed by group III element implantation by photolithography or ion implantation in a conventional process, and then the source is formed by electrode formation. Forming an electrode 421, a drain electrode 422, and a gate electrode 423;
A high-speed mobility transistor including a p-channel field-effect transistor using the e-channel layer 414 as a hole channel is formed.

In the case of the element structure of the semiconductor device 400 according to the third embodiment, the band structure is as shown in FIG. 11, and the B-doped Si layer 416 forms a barrier layer, and holes emitted from the acceptor B are used. Immediately move and accumulate in the hole i-Ge channel layer 414 to form a two-dimensional hole gas.

As in the semiconductor device 400 of the third embodiment,
Even when the delta-doped layer is a Si layer doped with a group 3 element such as B, the activation rate of the impurities can be made almost 100% as in the case of the first embodiment, and a field-effect transistor having good characteristics is manufactured. It became possible. As a result, it has become possible to realize a field effect transistor having a mobility that is at least twice as high as that of the conventional device.

(Embodiment 4) FIG. 12 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 4) of the present invention. FIG. FIG. 4 is a schematic sectional view in which a layer is formed. Also,
FIG. 14 is a schematic diagram showing a band structure of a junction portion of the semiconductor device.

In the semiconductor device 500 of the fourth embodiment, in the structure of the first embodiment, the channel layer is formed of a Ge channel layer instead of the Si channel layer, and the delta-doped layer is formed of Ge doped with a group V element such as Sb. Instead of a layer, it is constituted by a Ge layer doped with a group 3 element such as B. In addition, Si _1-X Ge _X mixed crystal layer (0
The mixed crystal ratio X of <x <1) is 0.7. Note that an n-type Si substrate is used as the substrate.

The semiconductor device 500 according to the first embodiment has the same structure as that of the first embodiment except that the i 1 -Ge channel layer is formed after the formation of the Si _{1 -X} Ge _X buffer layer, and the Si _{1 -X} Ge _X spacer layer is formed. Is formed by forming a delta-doped layer with a Ge layer doped with a group 3 element such as B on the Si _1-x Ge _x spacer layer.

Next, the semiconductor device will be described while explaining the manufacturing method.
The configuration of 500 will be described. As shown in FIG. 13, an n-type Si substrate 5 having a resistivity of 5 Ωcm and a crystal plane of the main surface being (100) is provided.
After chemical cleaning of 11, put it in the growth equipment, and after cleaning the surface, remove Si
A Si layer 512 is grown on the substrate 511 at a substrate temperature of 600 ° C. to a thickness of 50 nm.

Next, a Ge evaporation source using heater heating and Si
Simultaneously with the evaporation source, further undoped impurity-doped i-Si _0.3 Ge _0.7 buffer layer 513 over the critical film thickness of 2000 nm, no stress from the substrate
An i-Si _0.3 Ge _0.7 buffer layer 513 is formed. 20nm on this
Was grown so that the i-Ge channel layer 514 was subjected to biaxial compressive stress from the i-Si _0.3 Ge _0.7 buffer layer 513. On this, a 10 nm i-Si _0.3 Ge _0.7 spacer layer 515 which is not further doped with impurities is grown in lattice matching with the i-Ge channel layer 514.

Next, Ge and B are simultaneously deposited, and a Ge layer 516 of about 2 nm doped with B is grown. Next, an i-Si _0.3 Ge _0.7 cap layer 517 is grown thereon to a thickness of 10 nm and a Si layer 518 is grown to a thickness of 5 nm.

Next, as shown in FIG. 12, the Si layer 518 is oxidized in the same manner as in the first embodiment, and thereafter, the impurity implantation region 519 is implanted by Group 3 element implantation by conventional photolithography or ion implantation. (Source / drain region), and then a source electrode 521, a drain electrode 522, and a gate electrode 523 are formed by electrode formation.
A high-speed mobility transistor including a p-channel field-effect transistor using the e-channel layer 514 as a hole channel is formed.

In the case of the element structure of the semiconductor device 500 of the fourth embodiment, the band structure is as shown in FIG. 14, and the B-doped Ge layer 516 forms a quantum well, but the well width is as small as 2 nm. The energy level inside the well is high and i-Si
_The holes emitted from the acceptor B because they are close to the energy at the bottom of the valence band of the _0.3 Ge _0.7 spacer layer 515 are not bound by the energy levels inside the wells, and the hole channel i-Ge channel layer 514 is not bound. And a two-dimensional hole gas is formed.

As in the semiconductor device 500 of the fourth embodiment,
Also in the case where the delta-doped layer is a Ge layer doped with a group 3 element such as B, the activation rate of impurities can be made almost 100% as in the case of the first embodiment, and a field effect transistor with good characteristics is manufactured. It became possible. As a result, it has become possible to realize a field effect transistor having a mobility that is at least twice as high as that of the conventional device.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

[0069]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) In the present invention, a carrier supply layer having a high activation rate is formed by using a single semiconductor such as Si or Ge as a region for supplying carriers in a barrier layer adjacent to a channel layer. It has become possible to realize a field effect transistor having a mobility that is twice or more higher.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the principle of the present invention.

FIG. 2 is a schematic cross-sectional view showing a semiconductor device according to one embodiment (Embodiment 1) of the present invention.

FIG. 3 is a schematic cross-sectional view in which a semiconductor growth layer is formed in multiple layers on a Si substrate in manufacturing the semiconductor device of the first embodiment.

FIG. 4 is a schematic cross-sectional view of a Si substrate or the like showing a state in which a source region and a drain region are formed in manufacturing the semiconductor device of the first embodiment.

FIG. 5 is a schematic view showing a band structure of a joint portion of the semiconductor device according to the first embodiment.

FIG. 6 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 2) of the present invention.

FIG. 7 is a schematic sectional view in which a semiconductor growth layer is formed in multiple layers on a Si substrate in the manufacture of the semiconductor device of the second embodiment.

FIG. 8 is a schematic diagram showing a band structure of a joint portion of the semiconductor device according to the second embodiment.

FIG. 9 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 3) of the present invention.

FIG. 10 is a diagram illustrating a method of manufacturing a semiconductor device according to the third embodiment;
FIG. 3 is a schematic cross-sectional view in which a semiconductor growth layer is formed in multiple layers on a substrate.

FIG. 11 is a schematic diagram illustrating a band structure of a junction portion of the semiconductor device according to the third embodiment.

FIG. 12 is a schematic sectional view showing a semiconductor device according to another embodiment (Embodiment 4) of the present invention.

FIG. 13 illustrates a method for manufacturing a semiconductor device according to the fourth embodiment.
FIG. 3 is a schematic cross-sectional view in which a semiconductor growth layer is formed in multiple layers on a substrate.

FIG. 14 is a schematic diagram showing a band structure of a joint portion of the semiconductor device according to the fourth embodiment.

[Explanation of symbols]

200,300,400,500… semiconductor device, 211,311… p-type Si substrate,
212,512… Si layer, 213,313… Si _1-X Ge _X buffer layer (i-Si _0.7
Ge _0.3 buffer layer), 214,314 ... i-Si layer, 215,315 ... Si _1-X G
e _X spacer layer (i-Si _0.7 Ge _0.3 spacer layer), 216 ... Sb-doped Ge layer, 217,317 ... Si _1-X Ge _X cap layer (i-Si _0.7 Ge _0.3
Cap layer), 218,518: Si layer, 219,319,419,519: impurity implantation region, 220,320,420,520 ... SiO ₂ film, 221,321,421,5
21 ... source electrode, 222,322,422,522 ... drain electrode, 22
3,323,423,523… Gate electrode, 312,412… i-Si layer, 316… S
b-doped Si layer, 318,418 ... i-Si layer, 411,511 ... n-type Si substrate, 413,513 ... Si _1-X Ge _X buffer layer (i-Si _0.3 Ge _0.7 buffer layer), 414,514 ... i-Ge channel layer, 415,515 … Si _1-X Ge _X
Spacer layer (i-Si _0.3 Ge _0.7 layer spacer layer), 416 ... B-doped Si layer, 417,517 ... Si _1-X Ge _X cap layer (i-Si _0.3 Ge _0.7
Layer cap layer), 516... B-doped Ge layer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shinya Yamaguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Central Research Laboratory F-term (reference) 5F040 DA01 DC01 EB11 EC04 ED03 EE04 EE06 EF11 EH02 FB10 FC11 5F102 GB01 GC01 GD10 GJ03 GK02 GL03 GM02 GQ04 GR01 GR07 GR09 GT02 HC04 HC07 HC10 HC11 HC15 HC21

Claims (12)

[Claims] An Si substrate, a Si _{1- x} Ge _x buffer layer (0 <x <1) formed on the Si substrate without lattice matching, and a Si channel layer formed on the buffer layer And a Si _1-X Ge _X spacer layer (0 <x <1) formed on the Si channel layer, and a group V element such as Sb formed on the Si _1-X Ge _X spacer layer. Delta-doped layer composed of a Ge layer, and a Si _1-X Ge _X cap layer formed on the delta-doped layer (0 <x <1)
A source region provided at one end of the Si channel layer and a drain region provided at the other end, and a gate electrode provided on the Si _1-X Ge _X cap layer via an insulating film, wherein the Si A semiconductor device comprising an n-type field effect transistor configured to generate a two-dimensional electron gas at an interface between a channel layer and the Si _1-x Ge _x spacer layer. 2. A Si substrate, a Si _{1- x} Ge _X buffer layer (0 <x <1) formed on the Si substrate without lattice matching, and a Si channel layer formed on the buffer layer And a Si _1-X Ge _X spacer layer (0 <x <1) formed on the Si channel layer, and a group V element such as Sb formed on the Si _1-X Ge _X spacer layer. Delta-doped layer made of a Si layer, and a Si _1-X Ge _X cap layer formed on the delta-doped layer (0 <x <1)
A source region provided at one end of the Si channel layer and a drain region provided at the other end, and a gate electrode provided on the Si _1-X Ge _X cap layer via an insulating film, wherein the Si A semiconductor device comprising an n-type field effect transistor configured to generate a two-dimensional electron gas at an interface between a channel layer and the Si _1-x Ge _x spacer layer. 3. The semiconductor device according to claim 1, wherein the mixed crystal ratio X is about 0.3. 4. A Si substrate, a Si _{1 -X} Ge _X buffer layer (0 <x <1) formed on the Si substrate without lattice matching, and a Ge channel layer formed on the buffer layer And a Si _1-X Ge _X spacer layer (0 <x <1) formed on the Ge channel layer, and a Group 3 element such as B formed on the Si _1-X Ge _X spacer layer. Delta-doped layer made of a Si layer, and a Si _1-X Ge _X cap layer formed on the delta-doped layer (0 <x <1)
A source region provided at one end of the Ge channel layer and a drain region provided at the other end, and a gate electrode provided on the Si _1-X Ge _X cap layer via an insulating film, A semiconductor device comprising a p-type field effect transistor configured to generate a two-dimensional hole gas at an interface between a channel layer and the Si _1-x Ge _x spacer layer. 5. A Si substrate, a Si _{1- x} Ge _X buffer layer (0 <x <1) formed on the Si substrate without lattice matching, and a Ge channel layer formed on the buffer layer And a Si _1-X Ge _X spacer layer (0 <x <1) formed on the Ge channel layer, and a Group 3 element such as B formed on the Si _1-X Ge _X spacer layer. Delta-doped layer composed of a Ge layer, and a Si _1-X Ge _X cap layer formed on the delta-doped layer (0 <x <1)
A source region provided at one end of the Ge channel layer and a drain region provided at the other end, and a gate electrode provided on the Si _1-X Ge _X cap layer via an insulating film, A semiconductor device comprising a p-type field effect transistor configured to generate a two-dimensional hole gas at an interface between a channel layer and the Si _1-x Ge _x spacer layer. 6. The semiconductor device according to claim 4, wherein said mixed crystal ratio X is about 0.7. 7. A Si _1-X Ge _X mixed crystal layer (0 <x <1) on a Si substrate
Forming a Si _1-X Ge _X buffer layer by growing without lattice matching, and growing an i-Si layer on the Si _1-X Ge _X buffer layer to form a Si channel layer, A Si _1-X Ge _X mixed crystal layer (0 <x <1) is grown on the Si channel layer to form a Si _1-X Ge
Forming a _X spacer layer, the Si _1-X Ge _X a step of the spacer layer on the grown Ge layer doped with Group 5 element such as Sb to form a delta doped layer, Si ₁ on the delta doped layer Forming a Si _1-X Ge _X cap layer by growing a _-X Ge _X mixed crystal layer (0 <x <1); and forming Si on the Si _1-X Ge _X cap layer.
Forming a silicon layer by growing a layer or i-Si layer; forming the silicon layer by thermal oxidation to form a SiO ₂ film; and selectively removing the SiO ₂ film to form an n-type impurity. Forming a source region and a drain region by forming a gate electrode, a source electrode, and a drain electrode on the SiO ₂ film and between the source region and the drain region and on the source region and the drain region. Forming a two-dimensional electron gas at the interface between the Si channel layer and the Si _1-x Ge _x spacer layer. 8. A Si _1-X Ge _X mixed crystal layer (0 <x <1) on a Si substrate
Forming a Si _1-X Ge _X buffer layer by growing without lattice matching, and growing an i-Si layer on the Si _1-X Ge _X buffer layer to form a Si channel layer, A Si _1-X Ge _X mixed crystal layer (0 <x <1) is grown on the Si channel layer to form a Si _1-X Ge
Forming a _X spacer layer, the Si _1-X Ge _X a step of the spacer layer on the grown Si layer doped with Group 5 element such as Sb to form a delta doped layer, Si ₁ on the delta doped layer Forming a Si _1-X Ge _X cap layer by growing a _-X Ge _X mixed crystal layer (0 <x <1); and forming Si on the Si _1-X Ge _X cap layer.
Forming a silicon layer by growing a layer or i-Si layer; forming the silicon layer by thermal oxidation to form a SiO ₂ film; and selectively removing the SiO ₂ film to form an n-type impurity. Forming a source region and a drain region by implanting, a gate electrode and a source by forming electrodes on the SiO ₂ film between the source region and the drain region and on the source region and the drain region, respectively. Forming an electrode and a drain electrode to produce an n-type field effect transistor configured to generate a two-dimensional electron gas at the interface between the Si channel layer and the Si _1-x Ge _x spacer layer. A method for manufacturing a semiconductor device. 9. The mixed crystal ratio X of the Si _1-X Ge _X mixed crystal layer (0 <x <1)
9. The method of manufacturing a semiconductor device according to claim 7, wherein the value is about 0.3. 10. A Si _1-X Ge _X mixed crystal layer (0 <x <1) on a Si substrate
forming a Si _1-X Ge _X buffer layer by growing without lattice matching to i; and forming a Ge channel layer by growing an i-Ge layer on the Si _1-X Ge _X buffer layer. Growing a Si _1-X Ge _X mixed crystal layer (0 <x <1) on the Ge channel layer to form a Si _1-X
Ge _X forming a spacer layer, the Si _1-X Ge _X a step of the spacer layer on the grown Si layer doped with Group 3 element such as B to form the delta doped layer, Si on the delta doped layer _1-X Ge _X mixed crystal layer and the step of (0 <x <1) the grown to form a Si _1-X Ge _X cap layer, on the Si _1-X Ge _X cap layer
Growing a Si layer or an i-Si layer to form a silicon layer, thermally oxidizing the silicon layer to form a SiO ₂ film, and selectively removing the SiO ₂ film to form a p-type film. Implanting impurities to form a source region and a drain region, and forming an electrode on the SiO ₂ film and between the source region and the drain region between the source region and the drain region, and on the drain region, respectively. Forming a source electrode and a drain electrode by producing a p-type field effect transistor having a configuration in which a two-dimensional hole gas is generated at an interface between the Ge channel layer and the Si _1-x Ge _x spacer layer. Manufacturing method of a semiconductor device. 11. A Si _1-X Ge _X mixed crystal layer (0 <x <1) on a Si substrate
forming a Si _1-X Ge _X buffer layer by growing without lattice matching to i; and forming a Ge channel layer by growing an i-Ge layer on the Si _1-X Ge _X buffer layer. Growing a Si _1-X Ge _X mixed crystal layer (0 <x <1) on the Ge channel layer to form a Si _1-X
Ge _X forming a spacer layer, the Si _1-X Ge _X and step on the spacer layer is grown Ge layer doped with Group 3 element such as B to form the delta doped layer, Si on the delta doped layer _1-X Ge _X mixed crystal layer and the step of (0 <x <1) the grown to form a Si _1-X Ge _X cap layer, on the Si _1-X Ge _X cap layer
Growing a Si layer or an i-Si layer to form a silicon layer, thermally oxidizing the silicon layer to form a SiO ₂ film, and selectively removing the SiO ₂ film to form a p-type film. Implanting impurities to form a source region and a drain region, and forming an electrode on the SiO ₂ film and between the source region and the drain region between the source region and the drain region, and on the drain region, respectively. Forming a source electrode and a drain electrode by producing a p-type field effect transistor having a configuration in which a two-dimensional hole gas is generated at an interface between the Ge channel layer and the Si _1-x Ge _x spacer layer. Manufacturing method of a semiconductor device. 12. The semiconductor according to claim 10, wherein a mixed crystal ratio X of the Si _1-X Ge _X mixed crystal layer (0 <x <1) is about 0.7. Device manufacturing method.