CN103811352A - MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) provided with GeSn source and drain and forming method thereof - Google Patents

MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) provided with GeSn source and drain and forming method thereof Download PDF

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CN103811352A
CN103811352A CN201410063619.7A CN201410063619A CN103811352A CN 103811352 A CN103811352 A CN 103811352A CN 201410063619 A CN201410063619 A CN 201410063619A CN 103811352 A CN103811352 A CN 103811352A
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gesn
layer
source
mosfet
substrate
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王敬
肖磊
赵梅
梁仁荣
许军
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Tsinghua University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) provided with a GeSn source and drain and a forming method thereof. The forming method comprises the following steps: providing a substrate of which the top is provided with a Ge layer; forming a gate stack or a fake gate on the substrate; forming openings of a source area and a drain area in both sides of the gate stack or the fake gate, and exposing the Ge layer out of the openings; injecting atoms, molecules, ions or plasmas containing Sn elements into the surface layer of the Ge layer, and forming a GeSn layer in the openings. By adopting the forming method of the MOSFET, a field effect transistor provided with the GeSn source and drain can be formed. Since the thicknesses of the GeSn source and drain are small, and the crystal quality is good, the transistor has high electric performance. Moreover, the method has the advantages of easiness, practicability and low cost.

Description

There is MOSFET leaking in GeSn source and forming method thereof
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to MOSFET leaking in a kind of GeSn of having source and forming method thereof.
Background technology
Along with the development of microelectric technique, constantly the dwindling of device size, the mobility that Si material is lower has become the principal element of restriction device performance.For the performance of continuous boost device, must adopt the more channel material of high mobility.The main technical schemes of research is at present: adopt Ge or SiGe material to do the channel material of PMOSFET device, III-V compound semiconductor materials is the channel material of NMOSFET device.Ge has the hole mobility that is four times in Si, and along with deepening continuously of research, the technological difficulties in Ge and SiGe channel mosfet are captured one by one.In the MOSFET of Ge or SiGe device, in order to introduce single shaft compressive strain in Ge or SiGe raceway groove, can fill strain Ge at source and drain areas 1-xsn x(GeSn) alloy, the strain GeSn leaking by source like this can introduce single shaft compressive strain in raceway groove, significantly promotes the performance of Ge or SiGe raceway groove, and when channel length is during at nanoscale, its performance boost is particularly evident.With Ge mutually compatible GeSn alloy be a kind of IV family semi-conducting material, and there is good compatibility with complementary metal oxide semiconductors (CMOS) (CMOS) technique of silicon.
But the GeSn alloy of the high Sn content of direct growth high-quality is very difficult.First, the equilirbium solid solubility of Sn in Ge is less than 1%(and is about 0.3%); Secondly, the surface of Sn can be less than Ge, is very easy to occur fractional condensation on surface; Again, Ge and α-Sn have very large lattice mismatch (14.7%).
In the time of growth GeSn material, the method conventionally adopting is molecular beam epitaxy (MBE).Wherein, the process of existing MBE technique growth GeSn material is: insert Sn solid metal as Sn source material in the Sn solid source stove of vacuum chamber; Substrate is inserted on the heater of vacuum chamber of molecular beam epitaxy source stove, vacuum chamber is vacuumized, substrate is heated; To the heating of Sn solid metal, make the fusing of Sn solid metal, evaporation produces the atom of Sn, opens baffle plate, makes Sn atom arrive substrate surface; In the vacuum chamber of molecular beam epitaxy source stove, pass into the chemical compound gas that contains Ge, make Ge atomic deposition to substrate surface, complete the epitaxial growth of GeSn alloy.The method can obtain the good GeSn film of crystal mass, but apparatus expensive, growth course is comparatively time-consuming, and cost is higher, in large-scale production, will be subject to certain limitation.Also someone adopts chemical vapor deposition (CVD) technique growth GeSn film, but the GeSn film quality making is poor, and thermal stability is not good, and the easy fractional condensation of Sn, is not suitable for semiconductor device yet.And, in MOSFET structure, the method that generally need to adopt constituency to form forms GeSn at source-drain area, can adopt in theory chemical vapor deposition to carry out selective growth GeSn film, and the thermal stability of the method in the time of non-selective growth GeSn alloy is not good at present, the easy fractional condensation of Sn, its selective growth technique is still immature, and cost is also higher.
Summary of the invention
The present invention is intended to solve at least to a certain extent above-mentioned MOSFET source and is difficult to form the measured GeSn film of matter, problem that production cost is high in leaking.For this reason, the object of the invention is to propose a kind of simple and cost is low has field-effect transistor leaking in GeSn source and forming method thereof.
For achieving the above object, can comprise the following steps according to the formation method with the MOSFET leaking in GeSn source of the embodiment of the present invention: provide top to there is the substrate of Ge layer; On described substrate, form the stacking or false grid of grid; At the opening in formation source region, the stacking or false grid of described grid both sides and drain region, expose described Ge layer at described aperture position; Inject the atom, molecule, ion or the plasma that contain Sn element to described Ge layer top layer, form GeSn layer at described aperture position.
Can form and there is the field-effect transistor that leak in GeSn source according to the formation method of the embodiment of the present invention, thinner thickness, the crystal mass that wherein leak in GeSn source are better, therefore transistor has good electric property, and this method have advantages of simple, cost is low.
Alternatively, also there is following technical characterictic according to the formation method with the MOSFET leaking in GeSn source of the embodiment of the present invention:
In an example of the present invention, also comprise: before forming the opening in described source region and drain region, form grid side wall in the stacking or false grid of described grid both sides.
In an example of the present invention, also comprise: after forming described GeSn layer, remove described false grid, form grid in described false gate region stacking.
In an example of the present invention, the method for described injection comprises Implantation.
In an example of the present invention, described Implantation comprises that plasma source Implantation and plasma immersion ion inject.
In an example of the present invention, the method for described injection comprises magnetron sputtering.
In an example of the present invention, in the process of utilizing described magnetron sputtering to inject, on described substrate, load back bias voltage.
In an example of the present invention, also comprise: remove the Sn film that described magnetron sputtering forms on described GeSn layer.
In an example of the present invention, utilize GeSn and Sn are had to high corrosion to select the solution of ratio to clean to remove described Sn film.
In an example of the present invention, the process of described injection heats described substrate, and heating-up temperature is 100-600 ℃.
In an example of the present invention, also comprise: after described injection, to the annealing of GeSn layer, annealing temperature is 100-600 ℃.
In an example of the present invention, described GeSn layer is strain GeSn layer.
In an example of the present invention, the thickness of described strain GeSn layer is 0.5-100nm.
In an example of the present invention, in described strain GeSn layer, the atomic percentage conc of Sn is less than 20%.
In an example of the present invention, the substrate that described top has Ge layer comprises: pure Ge substrate, ge-on-insulator substrate, have the Si substrate on Ge surface.
For achieving the above object, according to the MOSFET that leak in GeSn source that has of the embodiment of the present invention, comprising: substrate; Be formed on the Ge raceway groove at the top of substrate; Leak in the GeSn source that is formed on described Ge raceway groove both sides; And be formed on the grid stacked structure on described Ge raceway groove.
According to the MOSFET that leak in GeSn source that has of the embodiment of the present invention, have advantages of that electric property is good.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is the flow chart of the formation method with the MOSFET leaking in GeSn source of first embodiment of the invention;
Fig. 2 (a) is the detailed process schematic diagram of the formation method shown in Fig. 1 to Fig. 2 (d);
Fig. 3 is the flow chart of the formation method with the MOSFET leaking in GeSn source of second embodiment of the invention;
Fig. 4 (a) is the detailed process schematic diagram of the formation method shown in Fig. 3 to Fig. 4 (e).
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic it " on " or D score can comprise that the first and second features directly contact, also can comprise that the first and second features are not directly contacts but by the other feature contact between them.And, First Characteristic Second Characteristic " on ", " top " and " above " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " comprise First Characteristic under Second Characteristic and tiltedly, or only represent that First Characteristic level height is less than Second Characteristic.
Adopt first grid technique according to the formation method with the MOSFET leaking in GeSn source of first embodiment of the invention, as shown in Figure 1, can comprise the steps:
S11. provide top to there is the substrate of Ge layer.
Particularly, provide substrate 10, this substrate 10 can be pure Ge substrate, ge-on-insulator sheet (Ge-On-Insulator, GeOI), have Si substrate on Ge surface (comprising that surface local region is the Si substrate of Ge) etc., with reference to figure 2(a).The Si substrate that is Ge for surface local region, in one embodiment of the invention, can form Ge layer by selective epitaxial process regional area extension on Si substrate; In another embodiment of the present invention, can on the Si substrate with Ge surface, form by photoetching and etching technics the Si substrate that surface local region is Ge.
S12. on substrate, form grid stacking.
Particularly, on substrate 10, deposit successively gate dielectric material and grid material, form patterned, to comprise gate dielectric layer 20a and grid layer 20b grid stacking 20 by photoetching and etching technics.With reference to figure 2(b).
S13. at the opening in grid formation source region, stacking both sides and drain region, expose Ge layer at aperture position.
Particularly, can further form grid side wall 30 in stacking 20 both sides of grid, to limit opening 40.This grid side wall 30 can play the effect that reduces element leakage.Detailed process is: after above-mentioned steps, first deposit the required dielectric material of grid side wall, then by suitable dry etch process, form grid side wall 30 in the stacking both sides of patterned grid, above source region and drain region, form opening 40, expose Ge layer at aperture position simultaneously.With reference to figure 2(c).
S14. inject the atom, molecule, ion or the plasma that contain Sn element to Ge layer top layer, to form GeSn layer at aperture position.
Particularly, inject the atom, molecule, ion or the plasma that contain Sn element to Ge layer top layer, the top layer of the Ge layer that opening 40 places are exposed or all Ge layer change target GeSn layer 50 into.This GeSn layer 50 can be as the source-drain area of MOSFET.So far, formed the MOSFET with GeSn source-drain area.With reference to figure 2(d).
According to the formation method of the MOSFET of first embodiment of the invention, can form and there is the field-effect transistor that leak in GeSn source, wherein GeSn source leak thinner thickness, crystal mass better, therefore transistor has good electric property, and this method have advantages of simple, cost is low.
Grid technique after adopting according to the formation method with the MOSFET leaking in GeSn source of second embodiment of the invention, as shown in Figure 3, can comprise the steps:
S21. provide top to there is the substrate of Ge layer.
Particularly, provide substrate 10, this substrate 10 can be pure Ge substrate, ge-on-insulator sheet (Ge-On-Insulator, GeOI), have Si substrate on Ge surface (comprising that surface local region is the Si substrate of Ge) etc., with reference to figure 4(a).The Si substrate that is Ge for surface local region, in one embodiment of the invention, can form Ge layer by selective epitaxial process regional area extension on Si substrate; In another embodiment of the present invention, can on the Si substrate with Ge surface, form by photoetching and etching technics the Si substrate that surface local region is Ge.
S22. on substrate, form false grid.
Particularly, on the region of the default raceway groove of substrate 10, form false grid 60.With reference to figure 4(b).
S23. at the opening in formation source region, false grid both sides and drain region, expose Ge layer at aperture position.
Particularly, can further form grid side wall 30 in false grid 60 both sides, to limit the opening 40 in source region and drain region.This grid side wall 30 can play the effect that reduces element leakage.Detailed process is: after above-mentioned steps, first deposit the required dielectric material of grid side wall, then by suitable dry etch process, form grid side wall 30 in patterned false grid 60 both sides, above source region and drain region, form opening 40, and expose Ge layer at aperture position simultaneously.With reference to figure 4(c).
S24. inject the atom, molecule, ion or the plasma that contain Sn element to Ge layer top layer, to form GeSn layer at aperture position.
Particularly, inject the atom, molecule, ion or the plasma that contain Sn element to Ge layer top layer, the top layer of the Ge layer that opening 40 places are exposed or all Ge layer change target GeSn layer 50 into.This GeSn layer 50 can be as the source-drain area of MOSFET.With reference to figure 4(d).
S25. remove false grid, form grid in false gate region stacking.
Particularly, can combine and remove false grid 60 by wet-chemical etching or dry etching and wet-chemical etching, and deposit successively gate dielectric material and grid material, and then by photoetching and etching technics, patterned to form, to comprise gate dielectric layer 20a and grid layer 20b grid stacking 20.So far, formed the MOSFET with GeSn source-drain area.With reference to figure 4(e).
According to the formation method of the MOSFET of second embodiment of the invention, can form equally and there is the field-effect transistor that leak in GeSn source, thinner thickness, the crystal mass that wherein leak in GeSn source are better, and therefore transistor has good electric property, and that this method has advantages of is simple, cost is low.
According to the present invention in the formation method of the MOSFET of above-mentioned two embodiment, by utilizing injection technology to carry out surface modification to original Ge layer.The atom, molecule, ion or the plasma that are about to contain Sn element are injected in original Ge layer, by controlling suitable temperature and implantation dosage, make the not obvious diffusion of Sn element of injecting, just can make the Sn atom in lattice can not assemble the sediment that forms Sn, keep the metastable state of GeSn alloy and fractional condensation does not occur, can obtain like this thinner thickness, the good GeSn layer of quality, have advantages of simple, cost is low.And in existing GeSn formation method, MBE method needs expensive equipment and needs ultra high vacuum, complex process and cost are high; CVD method is also not exclusively ripe, because growth temperature is high, thus often there is the fractional condensation of Sn element in metastable GeSn, thus the crystal mass of GeSn layer affected, and its equipment and comparatively costliness of source of the gas, thereby cost is also higher.
It should be noted that, in injection technology process, original Ge layer can only have surface part to be changed to GeSn layer, also can all be changed to GeSn layer.Particularly, in the time that the leakage of the source of MOSFET needs to form thicker GeSn layer, can inject the ion or the plasma that contain Sn element.Ion and energy of plasma are high, can inject and reach certain depth.In the time that the leakage of the source of MOSFET needs to form thinner GeSn layer, not only inject ion or plasma and can form GeSn layer, the molecule that injects Sn atom or contain Sn element also can form GeSn layer.
In an example of the present invention, the method of injecting can adopt Implantation, (comprising Sn ion or the plasma containing Sn element) incided in Ge layer and goes to be about to have ion beam certain energy, that contain Sn element, and rest in Ge layer, make Ge layer segment or be all converted to GeSn alloy.The degree of depth that changes injection by changing the energy of ion beam, ion beam energy is higher, injects darker.In injection process, can adopt the voltage of variation to obtain the ion beam energy of variation, thereby Sn element is distributed within the specific limits comparatively equably.Particularly, except conventional Implantation, Implantation also comprises that plasma source Implantation and plasma immersion ion inject, and plasma based ion is injected.In the time that plasma based ion is injected, Ge layer is buried in the plasma that contains Sn element, accelerated under electric field action containing the cation of Sn element, and directive Ge layer surface is also injected in Ge layer.Inject by plasma based ion, can be easy to the implantation dosage that reaches very high, be easy to the GeSn layer of the Sn content that obtains 1%～20%, highly efficient in productivity, cost is also very low, and is subject to the impact of surface configuration little, and nonplanar Ge surface also can be realized equably and being injected.Implantation can form thicker GeSn layer, and Implantation Energy is higher, and GeSn layer is thicker.Preferably, the thickness of GeSn layer is 0.5-100nm.
In an example of the present invention, the method for injection can adopt magnetron sputtering.When magnetron sputtering, Ar ion accelerates to fly to negative electrode Sn target or the target containing Sn under electric field action, and with high-energy bombardment target surface, makes target generation sputter.Sputtering particle is mainly atom, also has a small amount of ion.By adjusting voltage of electric field, the technological parameters such as vacuum degree, make sputtering particle have higher energy, and with higher speed directive Ge layer, part particle can be injected in Ge layer and form metastable GeSn alloy.Alternatively, in the process of utilizing magnetron sputtering to inject to Ge layer, on substrate, load back bias voltage, such as-40～-120V, can make like this part particle sputtering there is more high-energy, be conducive to particle and be injected into the more depths on Ge top layer, for example, can be deep to some nanometers.It should be noted that, the material sputtering during due to magnetron sputtering is more, conventionally can after forming GeSn layer, further form Sn film.Therefore after magnetron sputtering, also need to remove the Sn film that magnetron sputtering forms on GeSn layer.For example, can utilize and GeSn and Sn are had to high corrosion select the solution of ratio to clean to remove Sn film and expose GeSn layer.Common cleaning solution comprises watery hydrochloric acid, dilute sulfuric acid, rare nitric acid.The thickness of the GeSn layer remaining after cleaning is 0.5-20nm, and preferably, this GeSn layer thickness is 0.5-10nm.
In an example of the present invention, in injection technology, heating-up temperature can be controlled between 100-600 ℃, preferably 150-450 ℃.The film quality obtaining under this temperature range is better.Temperature is too low, injects the damage that brings and can not repair, GeSn layer second-rate; Excess Temperature, will spread seriously the Sn in GeSn layer, and the solid solubility of Sn in Ge very low (being atomic percent 0.3% under equilibrium state), the Sn in GeSn layer easily separates out and forms Sn sediment.
In an example of the present invention, after forming GeSn layer, can also strengthen this GeSn layer by annealing in process.The temperature range of annealing is 100-600 ℃, preferably 150-450 ℃.Temperature is too low, injects the damage that brings and can not repair, GeSn layer second-rate; Excess Temperature, will the Sn in GeSn layer be spread seriously, and the solid solubility of Sn in Ge be very low, and the Sn in GeSn easily separates out and forms Sn sediment.It is pointed out that if adopt first grid technique, gate medium wherein may not bear 450 ℃ of above high temperature, and now, the heating-up temperature in injection technology and annealing in process temperature can be controlled at below 400 ℃.
In an example of the present invention, GeSn layer is strain GeSn layer.The thickness of strain GeSn layer is 0.5-100nm.Be preferably 10-40nm.In strain GeSn layer, the atomic percentage conc of Sn is less than 20%.It should be noted that, in the GeSn layer of strain, Sn content is higher completely, and it answers variation larger, and correspondingly its thickness should be reduced to below the critical thickness of relaxation, could keep complete strain.In strain GeSn layer, Sn content is higher, and its critical thickness is thinner.In the time that Sn content is 10%, the variation of answering of the GeSn film of the upper complete strain of Ge is about 1.5%, the now about 30nm of the critical thickness of strain GeSn layer, that is now the GeSn thickness of MOSFET source-drain area should not exceed 30nm; And in the time that Sn content is 5%, it answers variation approximately 0.8%, more than its critical thickness can reach 100nm, illustrate that now the GeSn thickness of MOSFET source-drain area can reach 100nm and GeSn layer still keeps complete strain.
Need to further illustrate, in the time that GeSn layer is strain GeSn layer, in injection technology, in heating-up temperature and annealing process, the height of annealing temperature need to mate with the material character of strain GeSn layer.The strain GeSn layer that the atomic percentage conc that for example needs Sn in common MOSFET device is 3-8%, and the GeSn layer that Sn atomic percentage conc is 8% is stable substantially at 450 ℃, thus now in injection technology in heating-up temperature and annealing process annealing temperature need to be no more than 450 ℃.
The invention allows for the MOSFET that leak in a kind of GeSn of having source, formed by above-mentioned disclosed any method, comprising: substrate; Be formed on the Ge raceway groove at the top of substrate; Leak in the GeSn source that is formed on Ge raceway groove both sides; And be formed on the grid stacked structure on Ge raceway groove.This has the MOSFET that leak in GeSn source, has advantages of that electric property is good.
For making those skilled in the art understand better the present invention, elaboration specific embodiment is as follows:
First, prepare ge-on-insulator substrate, and adopt successively acetone, absolute ethyl alcohol, deionized water and hydrofluoric acid clean for subsequent use.
Secondly, deposit according to this gate dielectric material HfO2 and grid material TaN/TiAl/TiN at substrate, then by photoetching and etching technics, obtained patterned HfO2/TaN/TiAl/TiN grid stacking, and form opening above source region and drain region.
Then, deposition grid spacer material, can, with silicon nitride as grid spacer material, by dry etch process, form grid side wall in the stacking both sides of grid, and form opening above source region and drain region, exposes Ge layer at aperture position.The opening size of opening size now when thering is no grid side wall is little.
Then, using plasma immersion ion injection technology is injected the plasma that contains Sn element in substrate, and now substrate heating temperature is 100-200 ℃, and injecting voltage is 10-25KeV, and implantation dosage is about 5 × 10 16/ cm 2.After injection completes, formed the thick strain GeSn layer of 15-30nm on Ge layer top layer, Sn content is about 8%.The substrate that Implantation is completed carries out annealing in process, and annealing temperature is 200-300 ℃, further to strengthen GeSn layer.
Now, obtained the MOSFET device that source region and drain region are GeSn material.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, modification, replacement and modification.

Claims (16)

1. a formation method with the MOSFET leaking in GeSn source, is characterized in that, comprises the following steps:
Provide top to there is the substrate of Ge layer;
On described substrate, form the stacking or false grid of grid;
At the opening in formation source region, the stacking or false grid of described grid both sides and drain region, expose described Ge layer at described aperture position;
Inject the atom, molecule, ion or the plasma that contain Sn element to described Ge layer top layer, form GeSn layer at described aperture position.
2. the formation method with the MOSFET leaking in GeSn source as claimed in claim 1, is characterized in that, also comprises:
Before forming the opening in described source region and drain region, form grid side wall in the stacking or false grid of described grid both sides.
3. the formation method with the MOSFET leaking in GeSn source as claimed in claim 1 or 2, is characterized in that, also comprises:
After forming described GeSn layer, remove described false grid, form grid in described false gate region stacking.
4. the formation method with the MOSFET leaking in GeSn source as described in claim 1-3 any one, is characterized in that, the method for described injection comprises Implantation.
5. the formation method with the MOSFET leaking in GeSn source as claimed in claim 4, is characterized in that, described Implantation comprises that plasma source Implantation and plasma immersion ion inject.
6. the formation method with the MOSFET leaking in GeSn source as described in claim 1-3 any one, is characterized in that, the method for described injection comprises magnetron sputtering.
7. the formation method with the MOSFET leaking in GeSn source as claimed in claim 6, is characterized in that, in the process of utilizing described magnetron sputtering to inject, on described substrate, loads back bias voltage.
8. the formation method with the MOSFET leaking in GeSn source as described in claim 6 or 7, is characterized in that, also comprises: remove the Sn film that described magnetron sputtering forms on described GeSn layer.
9. as claimed in claim 8 have a formation method of MOSFET that leak in GeSn source, it is characterized in that, utilizes GeSn and Sn are had to high corrosion to select the solution of ratio to clean to remove described Sn film.
10. the formation method with the MOSFET leaking in GeSn source as claimed in claim 1, is characterized in that, the process of described injection heats described substrate, and heating-up temperature is 100-600 ℃.
The 11. formation methods with the MOSFET leaking in GeSn source as claimed in claim 1, is characterized in that, also comprise: after described injection, to the annealing of GeSn layer, annealing temperature is 100-600 ℃.
The 12. formation methods with the MOSFET leaking in GeSn source as claimed in claim 1, is characterized in that, described GeSn layer is strain GeSn layer.
The 13. formation methods with the MOSFET leaking in GeSn source as claimed in claim 12, is characterized in that, the thickness of described strain GeSn layer is 0.5-100nm.
The 14. formation methods with the MOSFET leaking in GeSn source as claimed in claim 12, is characterized in that, in described strain GeSn layer, the atomic percentage conc of Sn is less than 20%.
15. have a formation method of MOSFET that leak in GeSn source as described in claim 1-14 any one, it is characterized in that, the substrate that described top has Ge layer comprises: pure Ge substrate, ge-on-insulator substrate, have the Si substrate on Ge surface.
16. 1 kinds have the MOSFET that leak in GeSn source, it is characterized in that, comprising:
Substrate;
Be formed on the Ge raceway groove at the top of substrate;
Leak in the GeSn source that is formed on described Ge raceway groove both sides; And
Be formed on the grid stacked structure on described Ge raceway groove.
CN201410063619.7A 2014-02-25 2014-02-25 MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) provided with GeSn source and drain and forming method thereof Pending CN103811352A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285153A1 (en) * 2012-04-25 2013-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Strained structure of semiconductor device and method of making the strained structure
CN103594495A (en) * 2012-08-16 2014-02-19 中国科学院微电子研究所 semiconductor device and making method thereof
WO2014026308A1 (en) * 2012-08-16 2014-02-20 中国科学院微电子研究所 Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285153A1 (en) * 2012-04-25 2013-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Strained structure of semiconductor device and method of making the strained structure
CN103594495A (en) * 2012-08-16 2014-02-19 中国科学院微电子研究所 semiconductor device and making method thereof
WO2014026308A1 (en) * 2012-08-16 2014-02-20 中国科学院微电子研究所 Semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
徐滨士等: "《表面工程新技术》", 31 January 2002 *
戴达煌等: "《薄膜与涂层现代表面技术》", 31 July 2008 *

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Application publication date: 20140521