CN103972105A - MOSFET with SiGe channel and forming method of MOSFET - Google Patents

MOSFET with SiGe channel and forming method of MOSFET Download PDF

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CN103972105A
CN103972105A CN201410186686.8A CN201410186686A CN103972105A CN 103972105 A CN103972105 A CN 103972105A CN 201410186686 A CN201410186686 A CN 201410186686A CN 103972105 A CN103972105 A CN 103972105A
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sige
mosfet
layer
raceway groove
formation method
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王敬
肖磊
梁仁荣
许军
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Tsinghua University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention provides an MOSFET with a SiGe channel and a forming method of the MOSFET. The forming method includes the following steps of providing a substrate with a Si layer at the top, injecting atoms, molecules, ions or plasmas containing Ge elements into the surface layer of the Si layer so that the SiGe layer can be formed, forming a gate stacking structure on the upper portion of the SiGe layer, and forming a source and a drain on the two sides of the gate stacking structure. According to the forming method of the MOSFET, the MOSFET with the SiGe channel can be formed, the SiGe channel is thin, crystalline quality is good, and accordingly the MOSFET has good electrical property and the method has the advantages of being simple, easy to carry out and low in cost.

Description

There is MOSFET of SiGe raceway groove and forming method thereof
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to MOSFET of a kind of SiGe of having raceway groove and forming method thereof.
Background technology
Along with the development of microelectric technique, constantly the dwindling of MOSFET device size, the mobility that Si material is lower has become the principal element of restriction device performance.For the continuous performance of boost device, must take measures to improve carrier mobility in raceway groove, industry-wide adoption at present be strained silicon technology.Because strain SiGe has the mobility higher than Si, for MOSFET, can adopt strain SiGe channel technology, adopt strain SiGe material at channel region, to promote the electric property of MOSFET device.
When growth SiGe material, conventionally the method adopting is chemical vapor deposition (CVD) technique, complex process, quality is wayward, especially the selective epitaxial process of the strain SiGe film of high Ge content (Ge content is greater than 30%), to substrate surface preliminary treatment with epitaxial temperature has and strict requirement, process window is narrow, and epitaxial device is comparatively expensive, and cost is also higher.
Summary of the invention
The present invention is intended to solve at least to a certain extent and in above-mentioned MOSFET raceway groove, is difficult to form the measured SiGe film of matter, complex process and the high problem of production cost.For this reason, the object of the invention is to propose a kind of simple and field-effect transistor with SiGe raceway groove that cost is low and forming method thereof.
For achieving the above object, can comprise the following steps according to the formation method of the MOSFET with SiGe raceway groove of first aspect present invention embodiment: provide top to there is the substrate of Si layer; Inject the atom, molecule, ion or the plasma that contain Ge element to described Si layer top layer, to form SiGe layer; On described SiGe layer, form grid stacked structure, and in formation source, described grid stacked structure both sides and leakage.
Can form the field-effect transistor with SiGe raceway groove according to the formation method of the embodiment of the present invention, wherein the thinner thickness of SiGe raceway groove, crystal mass are better, therefore transistor has good electric property, and that this method has advantages of is simple, cost is low.
Alternatively, also there is following technical characterictic according to the formation method of the MOSFET with SiGe raceway groove of the embodiment of the present invention:
In one embodiment of the invention, also comprise: when the atom, molecule, ion that contains Ge element described in injecting to described Si layer top layer or plasma, inject atom, molecule, ion or plasma containing B or P or As element, so that described SiGe layer is adulterated.
In one embodiment of the invention, also comprise: before described injection, on described substrate, form mask, in mask, form the opening of device region, expose described Si layer at described aperture position.
In one embodiment of the invention, also comprise: form grid side wall in the stacking both sides of described grid.
In one embodiment of the invention, the method for described injection comprises Implantation.
In one embodiment of the invention, described Implantation comprises that plasma source Implantation and plasma immersion ion inject.
In one embodiment of the invention, the method for described injection comprises magnetron sputtering.
In one embodiment of the invention, in the process of utilizing described magnetron sputtering to inject, on described substrate, load back bias voltage.
In one embodiment of the invention, also comprise: remove the Ge film that described magnetron sputtering forms on described SiGe layer.
In one embodiment of the invention, utilize and Ge and SiGe are had to high corrosion select the solution of ratio to clean to remove described Ge film.
In one embodiment of the invention, the process of described injection heats described substrate, and heating-up temperature is 100-900 DEG C.
In one embodiment of the invention, also comprise: after described injection, to the annealing of SiGe layer, annealing temperature is 100-900 DEG C.
In one embodiment of the invention, described SiGe layer is strain SiGe layer.
In one embodiment of the invention, the thickness of described strain SiGe layer is 0.5-100nm.
In one embodiment of the invention, in described strain SiGe layer, the atomic percentage conc of Ge is less than 50%.
In one embodiment of the invention, to have the substrate of Ge layer be Si substrate on pure Si substrate or insulator at described top.
For achieving the above object, according to the MOSFET with SiGe raceway groove of second aspect present invention embodiment, comprising: substrate; Be formed on the SiGe raceway groove at the top of substrate; Be formed on the grid stacked structure on described SiGe raceway groove; And be formed on source and the leakage of described grid stacked structure both sides.
According to the MOSFET with SiGe raceway groove of the embodiment of the present invention, in raceway groove, carrier mobility is high, for strain SiGe material, there is on the one hand the hole mobility higher than Si, on the other hand in the time that its Ge content exceedes 20%, its electron mobility is also high than Si, and therefore the MOSFET of SiGe raceway groove has advantages of that electric property is good.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Brief description of the drawings
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is the flow chart of the formation method of the MOSFET with SiGe raceway groove of first embodiment of the invention.
Fig. 2 (a) is the detailed process schematic diagram of the formation method shown in Fig. 1 to Fig. 2 (c).
Fig. 3 is the flow chart of the formation method of the MOSFET with SiGe raceway groove of second embodiment of the invention.
Fig. 4 (a) is the detailed process schematic diagram of the formation method shown in Fig. 3 to Fig. 4 (d).
Fig. 5 is SiGe/Si structure (004) the face XRD scanning curve of the embodiment of the present invention.
Fig. 6 is SiGe/Si structure (224) the face XRD scanning curve of the embodiment of the present invention.
Fig. 7 is the XRD reciprocal space figure test result schematic diagram of the SiGe/Si structure of the embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In the present invention, unless otherwise clearly defined and limited, First Characteristic Second Characteristic it " on " or D score can comprise that the first and second features directly contact, also can comprise that the first and second features are not directly contacts but by the other feature contact between them.And, First Characteristic Second Characteristic " on ", " top " and " above " comprise First Characteristic directly over Second Characteristic and oblique upper, or only represent that First Characteristic level height is higher than Second Characteristic.First Characteristic Second Characteristic " under ", " below " and " below " comprise First Characteristic under Second Characteristic and tiltedly, or only represent that First Characteristic level height is less than Second Characteristic.
According to the formation method of the MOSFET with SiGe raceway groove of first embodiment of the invention, as shown in Figure 1, can comprise the steps:
S11. provide top to there is the substrate of Si layer.
Particularly, this substrate 10 can be Si substrate (Si-On-Insulator, SOI) etc. on pure Si substrate, insulator, with reference to figure 2 (a).
S12. inject the atom, molecule, ion or the plasma that contain Ge element to Si layer top layer, to form SiGe layer.
Particularly, inject the atom, molecule, ion or the plasma that contain Ge element to Si layer top layer, by the top layer of Si layer or all change target SiGe layer 20 into.For example, for pure Si substrate, its surface part is converted into SiGe layer after injecting; For SOI substrate, its top layer Si layer can all be converted into SiGe layer after injecting, and can Partial Conversion be also SiGe layer.This SiGe layer 20 can be as channel region, source region and the drain region of MOSFET.With reference to figure 2 (b).Certainly, this SiGe layer 20 also can only be used as the channel region of MOSFET.Alternatively, inject the atom that contains Ge element, molecule, ion or plasma to Si layer top layer time, inject atom, molecule, ion or plasma containing B or P or As element, so that SiGe layer 20 is adulterated.The B being injected into or P or As element can be activated in annealing process or the subsequent anneal technique of injecting the while, realize the doping to SiGe layer, wherein, while injecting B element, can carry out p-type doping, while injecting P or As element, can carry out N-shaped doping.
S13. on SiGe layer, form grid stacked structure, and in formation source, grid stacked structure both sides and leakage.
Particularly, on SiGe layer 20, form the grid stacked structure 30 that comprises gate dielectric layer 30a and grid layer 30b.And, can be by technique formation source and leakages in the SiGe layer 20 of grid stacked structure 30 both sides such as doping.So far, formed the MOSFET with SiGe channel region.Alternatively, can also form grid side wall 40 in stacking 30 both sides of grid.With reference to figure 2 (c).It should be noted that, in step S13, can adopt first grid technique (first form grid stacked structure after formation source and leakage), also can adopt rear grid technique (first to form false grid, form again source and leakage, then remove false grid, finally form grid stacked structure in false gate region).
According to the formation method of the MOSFET of the embodiment of the present invention, can form the field-effect transistor that there is raceway groove, source and leakage and be SiGe material, wherein the thinner thickness of SiGe raceway groove, crystal mass are better, therefore transistor has good electric property, and that this method has advantages of is simple, cost is low.
According to the formation method of the MOSFET with SiGe raceway groove of second embodiment of the invention, as shown in Figure 3, can comprise the steps:
S21. provide top to there is the substrate of Si layer.
Particularly, provide substrate 10, this substrate 10 can be Si substrate (Si-On-Insulator, SOI) etc. on pure Si substrate, insulator, with reference to figure 4 (a).
S22. on substrate, form mask, in mask, form the opening of device region, expose Ge layer at aperture position.
Particularly, on substrate 10, form mask 10a by deposition or coating processes, then on mask 10a, form the opening of patterned device region by photoetching and etching technics, expose Si layer at aperture position.With reference to figure 4 (b).
S23. inject the atom, molecule, ion or the plasma that contain Ge element to Si layer top layer, to form SiGe layer at aperture position.
Particularly, inject the atom, molecule, ion or the plasma that contain Ge element to Si layer top layer, the top layer of the Si layer that opening part is exposed or all change target SiGe layer 20 into.With reference to figure 4 (c).For example, for pure Si substrate, its surface part of exposing in open area is converted into SiGe layer after injecting; For SOI substrate, the top layer Si layer that it exposes in open area can all be converted into SiGe layer after injecting, and can Partial Conversion be also SiGe layer.After injection, mask 10a can remove also and can retain.Alternatively, inject the atom that contains Ge element, molecule, ion or plasma to Si layer top layer time, inject atom, molecule, ion or plasma containing B or P or As element, so that SiGe layer 20 is adulterated.The B being injected into or P or As element can be activated in annealing process or the subsequent anneal technique of injecting the while, realize the doping to SiGe layer, wherein, while injecting B element, can carry out p-type doping, while injecting P or As element, can carry out N-shaped doping.
S24. on SiGe layer, form grid stacked structure, and in formation source, grid stacked structure both sides and leakage.
Particularly, on SiGe layer 20, form the grid stacked structure 30 that comprises gate dielectric layer 30a and grid layer 30b.And, can be by technique formation source and leakages in the SiGe layer 20 of grid stacked structure 30 both sides such as doping.So far, formed the MOSFET with SiGe channel region.Alternatively, can also form grid side wall 40 in stacking 30 both sides of grid.With reference to figure 4 (d).
It should be noted that, in embodiments of the present invention, by controlling position and the size of opening, both can form the MOSFET device that raceway groove, source and drain region are SiGe, can form again only channel region is that SiGe material, source and drain region are the MOSFET device of Si, now, the size of the size of opening and position and default channel region and position consistency.
According to the formation method of the MOSFET of the embodiment of the present invention, can form and there is the field-effect transistor that raceway groove is SiGe material, wherein the thinner thickness of SiGe raceway groove, crystal mass are better, and therefore transistor has good electric property, and that this method has advantages of is simple, cost is low.
In the formation method of MOSFET according to the above embodiment of the present invention, by utilizing injection technology to carry out surface modification to original Si layer.The atom, molecule, ion or the plasma that are about to contain Ge element are injected in original Si layer, by controlling suitable temperature and implantation dosage, can obtain thinner thickness, the good SiGe layer of quality, have advantages of simple, cost is low.And in the existing method of utilizing CVD selective epitaxial SiGe raceway groove, complex process and cost are higher.
It should be noted that, in injection technology process, original Si layer can only have surface part to be changed to SiGe layer, also can all be changed to SiGe layer.Particularly, in the time that device need to form thicker SiGe layer, can inject the ion or the plasma that contain Ge element.Ion and energy of plasma are high, can inject and reach certain depth.In the time that device need to form thinner SiGe layer, not only inject ion or plasma and can form SiGe layer, the molecule that injects Ge atom or contain Ge element also can form thinner SiGe layer.
In one embodiment of the invention, the method of injecting can adopt Implantation, that is: incide in Si layer and go thering is ion beam certain energy, that contain Ge element (comprising Ge ion or the plasma containing Ge element), and rest in Si layer, make Si layer segment or be all converted to SiGe alloy.The degree of depth that changes injection by changing the energy of ion beam, ion beam energy is higher, injects darker.In injection process, can adopt the voltage of variation to obtain the ion beam energy of variation, thereby Ge element is distributed within the specific limits comparatively equably.Particularly, except conventional Implantation, Implantation also comprises that plasma source Implantation and plasma immersion ion inject, and plasma based ion is injected.In the time that plasma based ion is injected, Si layer is buried in the plasma that contains Ge element, accelerated under electric field action containing the cation of Ge element, and directive Si layer surface is also injected in Si layer.Inject by plasma based ion, can be easy to the implantation dosage that reaches very high, be easy to the SiGe layer of the Ge content that obtains 1%～50%, highly efficient in productivity, cost is also very low, and is subject to the impact of surface configuration little, and nonplanar Si surface also can be realized equably and being injected.Implantation can form thicker SiGe layer, and Implantation Energy is higher, and SiGe layer is thicker.Preferably, the thickness of SiGe layer is 0.5-100nm.
In one embodiment of the invention, the method for injection can adopt magnetron sputtering.When magnetron sputtering, Ar ion accelerates to fly to negative electrode Ge target or the target containing Ge under electric field action, and with high-energy bombardment target surface, makes target generation sputter.Sputtering particle is mainly atom, also has part ion.By adjusting voltage of electric field, the technological parameters such as vacuum degree, make sputtering particle have higher energy, and with higher speed directive Si layer, part particle can be injected in Si layer and form SiGe alloy.Alternatively, in the process of utilizing magnetron sputtering to inject to Si layer, on substrate, load back bias voltage, such as-40～-120V, can make like this part particle sputtering there is more high-energy, be conducive to particle and be injected into the more depths on Si top layer, for example, can be deep to some nanometers.It should be noted that, the material sputtering during due to magnetron sputtering is more, conventionally can after forming SiGe layer, further form Ge film.Therefore after magnetron sputtering, also need to remove the Ge film that magnetron sputtering forms on SiGe layer.For example, can utilize and Ge and SiGe are had to high corrosion select the solution of ratio to clean to remove Ge film and expose SiGe layer.Common cleaning solution comprises hydrofluoric acid and the hydrogen peroxide mixed aqueous solution of the sulfuric acid of the hydrochloric acid of dilution and the mixed aqueous solution of hydrogen peroxide, dilution and hydrogen peroxide mixed aqueous solution, dilution, and rare nitric acid.The thickness of the SiGe layer remaining after cleaning is 0.5-20nm, and preferably, this SiGe layer thickness is 0.5-10nm.
In one embodiment of the invention, in injection technology, heating-up temperature can be controlled between 100-900 DEG C, preferably 400-800 DEG C.The film quality obtaining under this temperature range is better.Temperature is too low, injects the damage that brings and can not repair, SiGe layer second-rate; Excess Temperature, the easy relaxation of SiGe layer, can not get the SiGe layer of complete strain, affects device performance.
In one embodiment of the invention, after forming SiGe layer, can also strengthen this SiGe layer by annealing in process.The temperature range of annealing is 100-900 DEG C, preferably 400-800 DEG C.Temperature is too low, injects the damage that brings and can not repair, SiGe layer second-rate; Excess Temperature, the easy relaxation of SiGe layer, can not get the SiGe layer of complete strain, affects device performance.
In one embodiment of the invention, SiGe layer is strain SiGe layer.The thickness of strain SiGe layer is 0.5-100nm.Be preferably 5-20nm.In strain SiGe layer, the atomic percentage conc of Ge is less than 50%.It should be noted that, in the SiGe layer of strain, Ge content is higher completely, and it answers variation larger, and correspondingly its thickness should be reduced to below the critical thickness of relaxation, could keep complete strain.In strain SiGe layer, Ge content is higher, and its critical thickness is thinner.In the time that Ge content is 50%, the variation of answering of the SiGe film of the upper complete strain of Si is about 2.1%, the now about 10nm of the critical thickness of strain SiGe layer, that is now the SiGe thickness of MOSFET channel region should not exceed 10nm; And in the time that Ge content is 20%, it answers variation approximately 0.8%, more than its critical thickness can reach 100nm, illustrate that now the SiGe thickness of MOSFET channel region can reach 100nm and SiGe layer still keeps complete strain.Need to further illustrate, in the time that SiGe layer is strain SiGe layer, in injection technology, in heating-up temperature and annealing process, the height of annealing temperature need to mate with the material character of strain SiGe layer.The strain SiGe layer that the atomic percentage conc that for example needs Ge in common MOSFET device is 20-40%, and the SiGe layer that Ge atomic percentage conc is 40% is stable substantially at 800 DEG C, thus now in injection technology in heating-up temperature and annealing process annealing temperature need to be no more than 800 DEG C.
The invention allows for a kind of MOSFET of the SiGe of having raceway groove, formed by above-mentioned disclosed any method, comprising: substrate; Be formed on the SiGe raceway groove at the top of substrate; Be formed on the grid stacked structure on SiGe raceway groove; And be formed on source and the leakage of grid stacked structure both sides.This has the MOSFET of SiGe raceway groove, and in raceway groove, carrier mobility is high, has advantages of that electric property is good.
For making those skilled in the art understand better the present invention, elaboration specific embodiment is as follows:
First, prepare N-shaped Si substrate, and adopt successively acetone, absolute ethyl alcohol, deionized water and hydrofluoric acid clean for subsequent use.
Secondly, at Si substrate surface deposit silicon nitride or SiO2, as mask, photoetching also etches the opening of device region, exposes local Si top surface.
Then, using plasma immersion ion injection technology is injected the plasma that contains Ge element in substrate, and injecting voltage is 5-25KeV, and implantation dosage is about 5 × 10 16/ cm 2.After injection completes, substrate is cleaned and annealed, annealing temperature is 800 DEG C, has formed the strain SiGe layer that about 30nm is thick in channel region, and wherein Ge content is the highest is about 35%.
Structure, crystalline state, Ge content and the strain regime of the SiGe material obtaining have been characterized with high resolution X-ray diffractometry (HRXRD).(004) face to SiGe material has carried out Omega-2Theta scanning, result as shown in Figure 5, wherein abscissa is (004) face diffraction maximum that 0 o'clock corresponding peak is Si substrate, appear at-3140arcsec of the diffraction peak left and right of SiGe (004).SiGe (224) face has been carried out to Omega-2Theta scanning, result as shown in Figure 6, wherein abscissa is that 0 o'clock corresponding peak is Si substrate (224) face diffraction maximum, appear at-733arcsec of the diffraction peak left and right of SiGe (224).By can be calculated, in SiGe material, Ge content is 34%, and relaxivity is 0.24%, and relaxivity is negligible, illustrates that SiGe is complete strain.Further SiGe material has been carried out reciprocal space figure (RSM) sweep test of (224) faces, result as shown in Figure 7.As shown in Figure 7, Si substrate and SiGe material are positioned on same vertical line and along pseudo-crystal line and distribute, and SiGe layer prepared by illustrative experiment is complete strain, and this conclusion is consistent with above-mentioned relaxivity result of calculation.
Then, on substrate, deposit according to this gate dielectric material and grid material, then by photoetching and etching technics, obtained patterned grid stacking.Deposition grid spacer material is also passed through dry etch process, forms grid side wall in the stacking both sides of grid.
Finally, the SiGe layer top surface of the stacking both sides of grid carried out to heavy doping technique with formation source and leakage.
Now, channel region, source-drain area have been obtained and have been the MOSFET device of SiGe material.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, amendment, replacement and modification.

Claims (17)

1. a formation method with the MOSFET of SiGe raceway groove, is characterized in that, comprises the following steps:
Provide top to there is the substrate of Si layer;
Inject the atom, molecule, ion or the plasma that contain Ge element to described Si layer top layer, to form SiGe layer;
On described SiGe layer, form grid stacked structure, and in formation source, described grid stacked structure both sides and leakage.
2. the formation method of the MOSFET with SiGe raceway groove as claimed in claim 1, is characterized in that, also comprises:
When the atom, molecule, ion that contains Ge element described in injecting to described Si layer top layer or plasma, inject atom, molecule, ion or plasma containing B or P or As element, so that described SiGe layer is adulterated.
3. the formation method of the MOSFET with SiGe raceway groove as claimed in claim 1 or 2, it is characterized in that, also comprise: before described injection, on described substrate, form mask, in mask, form the opening of device region, expose described Si layer at described aperture position.
4. the formation method of the MOSFET with SiGe raceway groove as described in claim 1-3 any one, is characterized in that, also comprises: form grid side wall in the stacking both sides of described grid.
5. the formation method of the MOSFET with SiGe raceway groove as described in claim 1-4 any one, is characterized in that, the method for described injection comprises Implantation.
6. the formation method of the MOSFET with SiGe raceway groove as claimed in claim 5, is characterized in that, described Implantation comprises that plasma source Implantation and plasma immersion ion inject.
7. the formation method of the MOSFET with SiGe raceway groove as described in claim 1-4 any one, is characterized in that, the method for described injection comprises magnetron sputtering.
8. the formation method of the MOSFET with SiGe raceway groove as claimed in claim 7, is characterized in that, in the process of utilizing described magnetron sputtering to inject, on described substrate, loads back bias voltage.
9. the formation method of the MOSFET with SiGe raceway groove as claimed in claim 7, is characterized in that, also comprises: remove the Ge film that described magnetron sputtering forms on described SiGe layer.
10. the formation method of the MOSFET with SiGe raceway groove as claimed in claim 9, is characterized in that, utilizes Ge and SiGe are had to high corrosion to select the solution of ratio to clean to remove described Ge film.
The formation method of 11. MOSFET with SiGe raceway groove as described in claim 1-4 any one, is characterized in that, the process of described injection heats described substrate, and heating-up temperature is 100-900 DEG C.
The formation method of 12. MOSFET with SiGe raceway groove as described in claim 1-4 any one, is characterized in that, also comprises: after described injection, to the annealing of SiGe layer, annealing temperature is 100-900 DEG C.
The formation method of 13. MOSFET with SiGe raceway groove as described in claim 1-4 any one, is characterized in that, described SiGe layer is strain SiGe layer.
The formation method of 14. MOSFET with SiGe raceway groove as claimed in claim 13, is characterized in that, the thickness of described strain SiGe layer is 0.5-100nm.
The formation method of 15. MOSFET with SiGe raceway groove as claimed in claim 13, is characterized in that, in described strain SiGe layer, the atomic percentage conc of Ge is less than 50%.
The formation method of 16. MOSFET with SiGe raceway groove as described in claim 1-4 any one, is characterized in that, the substrate that described top has Ge layer is Si substrate on pure Si substrate or insulator.
17. 1 kinds have the MOSFET of SiGe raceway groove, it is characterized in that, comprising:
Substrate;
Be formed on the SiGe raceway groove at the top of substrate;
Be formed on the grid stacked structure on described SiGe raceway groove; And
Be formed on source and the leakage of described grid stacked structure both sides.
CN201410186686.8A 2014-05-05 2014-05-05 MOSFET with SiGe channel and forming method of MOSFET Pending CN103972105A (en)

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