CN108565285B - GaAs-based high-electron-mobility transistor material and preparation method thereof - Google Patents
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- CN108565285B CN108565285B CN201810660416.4A CN201810660416A CN108565285B CN 108565285 B CN108565285 B CN 108565285B CN 201810660416 A CN201810660416 A CN 201810660416A CN 108565285 B CN108565285 B CN 108565285B
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 76
- 239000000463 material Substances 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 22
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000001179 sorption measurement Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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Abstract
The invention discloses a GaAs-based high electron mobility transistor material and a preparation method thereof, wherein the device comprises a GaAs substrate, a GaAs buffer layer, an InGaAs channel layer, an N-AlGaAs etching stop layer and an N + GaAs cap layer, and is characterized in that the growth temperature adopted by the GaAs buffer layer is low temperature. The preparation method comprises the steps of growing a GaAs buffer layer on a GaAs substrate at a low temperature; then continuing to sequentially grow the active region structure of the high electron mobility transistor on the GaAs buffer layer: InGaAs channel layer, N-AlGaAs etching stop layer, N + GaAs cap layer. The invention replaces the original buffer layer by growing the low-temperature GaAs buffer layer, and aims to avoid the formation of parallel conductance at the buffer layer of the high electron mobility transistor structure, so that the buffer layer generates the electric leakage phenomenon when the device works, thereby improving the maximum working frequency of the device and simultaneously effectively reducing the threshold voltage of the device.
Description
Technical Field
The invention relates to the technical field of epitaxial growth of III-V group compound semiconductor thin film materials, in particular to an improved GaAs-based high electron mobility transistor material and a preparation method thereof.
Background
The basic principle of molecular beam epitaxial growth (MBE) technology is that a substrate slice and a plurality of molecular beam source furnaces (jet furnaces) are oppositely arranged in an ultrahigh vacuum system, various elements (As, Ga and the like) and dopant elements (Si, Be and the like) which are to form a compound are respectively placed in different jet furnaces for heating, molecules or atoms of the elements are jetted to the surface of the heated substrate slice at a certain thermal motion speed and a certain proportion of beam intensity, and interact with the surface (including the actions of surface migration, decomposition, adsorption, desorption and the like) is generated, and the epitaxial production of a single crystal film is carried out. According to the set program, the shutter is opened and closed, the furnace temperature is changed, the growth time is controlled, and compounds with different thicknesses or ternary and quaternary solid solutions and heterojunctions with different component proportions can be grown to prepare various ultrathin layer structure materials.
The development of high-quality ultra-thin layer growth technology such as Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD) and the like and submicron fine processing technology enables a High Electron Mobility Transistor (HEMT) which is published in 1980 to obtain continuous innovation on the structure, and the frequency, the power and the low-noise performance of the HEMT are greatly improved, so that the HEMT becomes one of important members of microwave and millimeter wave devices.
Although HEMTs of the conventional structure have excellent high-frequency and high-speed characteristics, there is a great problem in that the HEMTs have poor temperature stability of characteristics. A Pseudomorphic High Electron Mobility Transistor (PHEMT) is an improvement over a High Electron Mobility Transistor (HEMT), the basic structure of which is shown in fig. 1. The temperature stability of the threshold voltage of the device is improved, the output voltage-current characteristic of the device is also improved, and the device has larger output resistance, higher transconductance, larger current processing capacity, higher working frequency, lower noise and the like. The PHEMT is mainly used for high-speed and high-frequency devices and is a core material for manufacturing microwave devices such as GaAs power tubes, low-noise monolithic circuits, T/R components, power monolithic circuits and the like.
In the current PHEMT structure, the GaAs buffer layer has low resistivity, leakage current is easy to generate, the working frequency of a device is reduced, and the power consumption of the device is increased.
Disclosure of Invention
In order to solve the above problems in the prior art, an object of the present invention is to provide an improved GaAs-based high electron mobility transistor material, which reduces leakage current caused by parallel conductance of a buffer layer and can improve the operating frequency of a device.
The invention also aims to provide a preparation method of the GaAs-based high electron mobility transistor material.
The GaAs-based high electron mobility transistor material comprises a GaAs substrate, a GaAs buffer layer, an InGaAs channel layer, an N-AlGaAs etching stop layer and an N + GaAs cap layer, wherein the GaAs buffer layer is a low-temperature buffer layer, Schottky barrier layers can be arranged between the GaAs buffer layer and the InGaAs channel layer or between the InGaAs channel layer and the N-AlGaAs etching stop layer, one mode is that the Schottky barrier layers can be respectively added between the GaAs buffer layer and the InGaAs channel layer and between the InGaAs channel layer and the N-AlGaAs etching stop layer, namely the number of the Schottky barrier layers is two; another way is to add one schottky barrier layer only between the GaAs buffer layer and the InGaAs channel layer or between the InGaAs channel layer and the n-AlGaAs etch stop layer, i.e., the number of schottky barrier layers is one.
It was found that the main reason for the lower resistivity of the GaAs buffer layer is due to the use of a growth temperature of 580 c, which approximates the resistivity of the intrinsic GaAs crystal, which is approximately 7 x 105And omega cm, when the high-electron-mobility transistor device is manufactured at the later stage, a part of current passes through the buffer layer, and the GaAs buffer layer becomes a parallel electric conduction layer with low mobility, so that the working frequency of the device is reduced, and the power consumption of the device is increased. The invention adopts the GaAs buffer layer growth temperature of 200-400 ℃, so that the grown GaAs buffer layer has higher resistivity, and the problem is effectively solved; and simultaneously, donor or acceptor impurities on the surface of the substrate can be pinned on the low-temperature buffer layer, so that the electric leakage of the buffer layer is greatly reduced.
Preferably, in the GaAs-based high electron mobility transistor material, the GaAs buffer layer has a resistivity of 1 to 7 × 107Omega cm. The GaAs buffer layer has an optimum resistivity of 5 × 107Ω.cm。
Preferably, in the GaAs-based high electron mobility transistor material, the GaAs buffer layer has a thickness of 50 to 5000 nm.
The invention provides a preparation method of any one of the GaAs-based high electron mobility transistor materials, which comprises the following steps:
growing a GaAs buffer layer on a GaAs substrate at the growth temperature of 200-400 ℃; then continuing to grow on the GaAs buffer layer in sequence: InGaAs channel layer, N-AlGaAs etching stop layer, N + GaAs cap layer. The InGaAs channel layer, the N-AlGaAs etching stop layer and the N + GaAs cap layer form an active region structure of the high electron mobility transistor.
The GaAs-based high-electron-mobility transistor material and the preparation method thereof provided by the invention have the following beneficial effects:
the low-temperature GaAs buffer layer is grown to replace the original buffer layer, so that the parallel conductance is prevented from being formed at the buffer layer of the high-electron-mobility transistor structure, the buffer layer is prevented from leaking electricity when the device works, the maximum working frequency of the device can be improved, and the threshold voltage of the device is effectively reduced.
Drawings
Fig. 1 shows the basic structure of a material for a high electron mobility transistor.
FIG. 2 shows a GaAs-based high electron mobility transistor material according to example 1.
Detailed Description
The technical solutions of the present invention are specifically and clearly explained below with reference to the drawings and examples, so that those skilled in the art can better understand the present invention.
Fig. 2 shows the basic structure of the high electron mobility transistor of the present application, specifically a pseudomorphic high electron mobility transistor, and referring to fig. 1-2, the material comprises a plurality of layers vertically grown from bottom to top, in order, a GaAs substrate, a GaAs buffer layer, an InGaAs channel layer, an N-AlGaAs etch stop layer, and an N + GaAs cap layer, wherein the GaAs buffer layer employs a growth temperature of 200 ℃ to 400 ℃, particularly 250 ℃ to 300 ℃, such as 280 ℃, 300 ℃, and so on. The basic structure of the PHEMT material is not limited to the above embodiments, and those skilled In the art may add other layer structures As required, for example, a schottky barrier layer may be added between the GaAs buffer layer and the InGaAs channel layer or between the InGaAs channel layer and the n-AlGaAs etch stop layer, the schottky barrier layer may be formed by using Al (ga) As, In (Al) As, InP or other iii-v semiconductor material, the thickness is 1-50nm, such As 15nm, 18nm, 20nm or 35nm, etc., the growth temperature is 450-600 ℃, and the optimal temperature is 600 ℃. One way is that Schottky barrier layers can be respectively added between the GaAs buffer layer and the InGaAs channel layer and between the InGaAs channel layer and the n-AlGaAs etching stop layer, namely the number of the Schottky barrier layers is two; another way is to add one schottky barrier layer only between the GaAs buffer layer and the InGaAs channel layer or between the InGaAs channel layer and the n-AlGaAs etch stop layer, i.e., the number of schottky barrier layers is one. The schottky barrier layer is used to form a region having a rectifying action on a boundary, and to reduce the flow of electrons in the vertical direction by allowing electrons to travel inside the channel.
Further referring to fig. 2, when growing a GaAs-based pseudomorphic hemt material structure, a low-temperature GaAs buffer layer is grown on a semi-insulating GaAs substrate at a growth temperature of 200 ℃ to 400 ℃, instead of the GaAs buffer layer grown at a high temperature of 580 ℃, and a PHEMT active region structure is continuously grown on the buffer layer, thereby reducing buffer layer leakage current of the PHEMT device. The schottky barrier layer may be grown according to a growth method commonly used in the art.
In order to verify whether the low-temperature GaAs buffer layer achieves the effects of high resistance and buffer layer leakage current reduction, the low-temperature GaAs buffer layer is required to be grown on the semi-insulating GaAs substrate, the growth temperature is 200-400 ℃, particularly the range of 250-300 ℃, such as 280 ℃, 300 ℃ and the like, the growth thickness is 50-5000nm, preferably the thickness is 200-500 nm, such as 200nm, 500nm, 1500nm or 2000 nm. Then, Hall measurement is carried out to judge whether the resistivity of the GaAs buffer layer reaches 107In the order of Ω.
Hall measurement shows that the resistivity of the GaAs buffer layer is 5 multiplied by 107Ω · cm, indicating that the resistivity of the GaAs buffer layer increases significantly after lowering the growth temperature.
The semiconductor material structure related to the present application can be grown by using a commonly used growth apparatus, for example, an MBE apparatus.
The inventive concept is explained in detail herein using specific examples, which are given only to aid in understanding the core concepts of the invention. It should be understood that any obvious modifications, equivalents and other improvements made by those skilled in the art without departing from the spirit of the present invention are included in the scope of the present invention.
Claims (3)
1. A GaAs-based high electron mobility transistor material comprises a GaAs substrate, a GaAs buffer layer, an InGaAs channel layer, an N-AlGaAs etching stop layer and an N + GaAs cap layer, and is characterized in that the GaAs buffer layer is a low-temperature buffer layer and is provided with two Schottky barrier layers, the Schottky barrier layers are arranged between the GaAs buffer layer and the InGaAs channel layer, and the InGaAs channel layer and the N-AlGaAs channel layerA Schottky barrier layer is arranged between the As etching stop layers, and the resistivity of the GaAs buffer layer is 1-7 multiplied by 107Omega.cm; the growth temperature of the GaAs buffer layer is 250-300 ℃;
the thickness of the GaAs buffer layer is 200 nm;
the thickness of the Schottky barrier layer is 15nm, 18nm, 20nm or 35nm, and the growth temperature is 450-600 ℃.
2. The GaAs-based high electron mobility transistor material of claim 1, wherein the growth temperature of the schottky barrier layer is 600 ℃.
3. The method for producing a GaAs-based high electron mobility transistor material according to claim 1 or 2, comprising the steps of:
growing a GaAs buffer layer on a GaAs substrate at a low growth temperature; then, the InGaAs channel layer, the N-AlGaAs etching stop layer and the N + GaAs cap layer are continuously and sequentially grown on the GaAs buffer layer.
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