CN111009468A - Preparation method and application of semiconductor heterostructure - Google Patents
Preparation method and application of semiconductor heterostructure Download PDFInfo
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- CN111009468A CN111009468A CN201811166674.3A CN201811166674A CN111009468A CN 111009468 A CN111009468 A CN 111009468A CN 201811166674 A CN201811166674 A CN 201811166674A CN 111009468 A CN111009468 A CN 111009468A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention provides a preparation method of a semiconductor heterostructure and application thereof, wherein the preparation method comprises the steps of providing a substrate; forming a nucleation layer on a substrate; forming a first buffer layer on the nucleation layer; forming a second buffer layer on the first buffer layer; forming a channel layer on the first buffer layer; forming a barrier layer on the channel layer, wherein the barrier layer and the channel layer form a heterostructure; the first buffer layer has a first doping concentration, the second buffer layer has a second doping concentration, and the first doping concentration is greater than the second doping concentration. The invention introduces at least two doping concentration buffer layers in the semiconductor heterostructure, can simultaneously consider the requirements of the resistivity of the high-resistance buffer layer and the crystal quality of the channel layer, has simple preparation, can greatly reduce the defect density of the channel layer, improves the crystal quality of the semiconductor heterostructure, improves the breakdown voltage and the current collapse effect of a device, and can be applied to the development of high-frequency and high-power devices with low cost.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method and application of a semiconductor heterostructure.
Background
Third-generation semiconductors represented by group III nitrides have excellent properties such as high forbidden bandwidth, high breakdown electric field, high saturated electron drift velocity, strong polarization, and the like, and particularly, high mobility transistors (HEMTs) based on AlGaN/GaN heterostructures have excellent characteristics such as high switching speed, low on-resistance, small device volume, high temperature resistance, energy saving, and the like, and are expected to be widely used in the field of next-generation high-efficiency power electronic devices. Among GaN-based heterostructure materials using sapphire, silicon carbide and silicon as substrate materials, GaN-based heterostructure materials on Si and devices have obvious advantages in the aspects of large size, low cost, compatibility with the existing Si process and the like, and have wide application prospects in the fields of solar inverters, hybrid electric vehicle inverters, power supplies, power converters of household appliances and industrial equipment and the like, so that the GaN-based heterostructure materials on Si and the devices become one of the hot spots of international nitride field research.
The epitaxial material of the active region of the AlGaN/GaN HEMT device mainly comprises a high-resistance buffer layer formed by GaN (AlGaN) material, a GaN high-mobility channel layer and an AlGaN barrier layer, and also comprises functional material layers added for solving the growth problem of certain materials or improving certain properties of the device. The high-resistance GaN (AlGaN) buffer layer has two functions: firstly, it will becomeDislocation and defects in the nuclear layer are isolated, so that the GaN channel layer can grow on a good initial interface, the quality and the flatness of an AlGaN/GaN heterojunction interface can be remarkably improved, and the transport performance of two-dimensional electron gas is improved; secondly, the leakage of electrons in the channel layer to the lower layer material is prevented, and the leakage problem of the device is solved, so that the GaN buffer layer is required to have higher resistivity, and the room temperature resistivity of the GaN buffer layer is required to be 106Omega cm or more. In order to improve the breakdown voltage of a GaN-based material on a Si substrate, carbon (C) doping with high background concentration is required to be introduced, the carbon doping technology is to obtain a high-resistance GaN (AlGaN) buffer layer by utilizing the self-compensation effect of carbon impurities, which is a key basis for obtaining high-voltage-resistant GaN-based HEMT materials and devices, the high-resistance GaN buffer layer can be obtained by the self-compensation effect of the carbon doping, and the doping concentration of carbon can reach atom 1x1020Atom/cm3The resistivity is more than 5000 omega/□. However, under the condition of such high doping of compensation impurities, the quality of the GaN-based material is seriously cracked, which is not beneficial to improving the voltage withstanding property of the device, and a large number of defects are introduced, the surface quality and the crystal quality of the GaN-based heterojunction are greatly influenced, the growth parameters of the GaN channel layer need to be optimized again on the C-doped GaN-based buffer layer, the surface quality is improved by adjusting the growth conditions, and the electron concentration and the mobility of the two-dimensional electron gas are improved.
The high-mobility GaN channel layer is a core component of the AlGaN/GaNHEMT structure, and the quality of the crystal lattice of the channel layer material directly influences the transport performance of two-dimensional electron gas. On one hand, the crystal lattice quality of the channel layer material is required to be improved and the background electron concentration of the channel layer is reduced in the growth process, so that the scattering is reduced and the mobility of two-dimensional electron gas is improved; on the other hand, lattice mismatch and thermal mismatch stress between the substrate and the GaN channel layer are effectively released, the interface characteristic of the heterojunction is improved, and then the high-quality AlGaN barrier layer is extended.
The Current collapse (Current collepse) phenomenon is a phenomenon that the output Current and the output power of an AlGaN/GaN HEMT device are reduced, the gain is reduced, the performance is deteriorated, and the reliability of the device is damaged under a certain condition, and is one of the major obstacles for the mature application of the AlGaN/GaN HEMT device. On one hand, the GaN-based buffer layer doped with high carbon concentration can affect the crystal quality of the channel layer and the mobility and carrier concentration of two-dimensional electron gas; on the other hand, the current collapse effect of the AlGaN/GaN HEMT device can be caused under high voltage (or high field). At present, in the application of a microwave amplifier, the working voltage of a device is lower, and the current collapse effect is better solved. However, the current collapse effect caused by high voltage (or high field) is still not completely solved, and whether the current collapse problem is solved or not is an important factor for practical application of GaN power electronic devices, and is also a great technical difficulty.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor heterostructure and a use thereof, which are used to solve the technical problems that the semiconductor heterostructure cannot simultaneously satisfy the requirements of a high-resistance buffer layer and a high-quality channel layer, and thus has poor breakdown resistance and is prone to current collapse.
To achieve the above and other related objects, the present invention provides a semiconductor heterostructure manufacturing method, which includes the steps of:
providing a substrate;
forming a nucleation layer on the substrate;
forming a first buffer layer on the nucleation layer;
forming a second buffer layer on the first buffer layer;
forming a channel layer on the first buffer layer; and the number of the first and second groups,
forming a barrier layer on the channel layer, wherein the barrier layer and the channel layer form a heterostructure;
wherein the first buffer layer has a first doping concentration and the second buffer layer has a second doping concentration, the first doping concentration being greater than the second doping concentration.
As an improvement of the above semiconductor heterostructure manufacturing method of the present invention, the manufacturing method further includes a step of forming an insertion layer between the channel layer and the barrier layer, the insertion layer, and the channel layer together constituting a heterostructure; the material of the insertion layer comprises aluminum nitride.
As an improvement to the above semiconductor heterostructure manufacturing method of the present invention, the manufacturing method further includes a step of forming a control layer between the nucleation layer and the first buffer layer; the control layer comprises aluminum gallium nitrogen, the chemical general formula of the control layer is AlxGa1-xN, and x is more than or equal to 0.1 and less than or equal to 1.
As an improvement to the above semiconductor heterostructure manufacturing method of the present invention, the substrate includes a silicon substrate or a silicon carbide substrate; the material of the nucleation layer comprises aluminum gallium nitride or aluminum nitride; the material of the first buffer layer comprises gallium nitride or aluminum gallium nitrogen; the material of the second buffer layer comprises gallium nitride or aluminum gallium nitrogen; the material of the channel layer comprises gallium nitride or indium gallium nitride; the barrier layer comprises aluminum gallium nitride or indium aluminum nitride.
As an improvement to the above semiconductor heterostructure manufacturing method of the present invention, the manufacturing method further includes:
forming the first buffer layer on the nucleation layer by in-situ epitaxial doping;
and forming the second buffer layer on the first buffer layer in an in-situ epitaxial doping mode.
As an improvement to the above semiconductor heterostructure manufacturing method of the present invention, the manufacturing method further includes:
forming a first buffer material layer on the nucleation layer, and implanting doping elements into the first buffer material layer through an ion implantation process to form the first buffer layer;
and forming a second buffer material layer on the first buffer layer, and implanting doping elements into the second buffer material layer through an ion implantation process to form the second buffer layer.
As an improvement to the above semiconductor heterostructure manufacturing method of the present invention, the manufacturing method further includes:
forming a first buffer material layer on the nucleation layer, and injecting doping elements into the first buffer material layer through a thermal diffusion process to form the first buffer layer;
and forming a second buffer material layer on the first buffer layer, and injecting doping elements into the second buffer material layer through a thermal diffusion process to form the second buffer layer.
As an improvement of the above semiconductor heterostructure manufacturing method of the present invention, the manufacturing method further includes forming at least a third buffer layer between the first buffer layer and the second buffer layer; the third buffer layer has a third doping concentration between the first doping concentration and the second doping concentration.
As an improvement to the above semiconductor heterostructure manufacturing method of the present invention, the doping element in the first buffer layer and the second buffer layer includes a carbon element or an iron element.
As an improvement to the above semiconductor heterostructure fabrication method of the present invention, the first doping concentration is greater than 1x1019Atom/cm3The second doping concentration is 1x1018Atom/cm3～1x1019Atom/cm3。
To achieve the above and other related objects, the present invention also provides a use of the above semiconductor heterostructure manufacturing method applied to the manufacture of a heterostructure high mobility transistor.
As described above, the semiconductor heterostructure manufacturing method and the use thereof of the present invention have the following advantageous effects:
the invention introduces at least two buffer layers with different doping concentrations into the semiconductor heterostructure, can simultaneously consider the requirements of the resistivity of the high-resistance buffer layer and the crystal quality of the channel layer, has simple preparation process, can greatly reduce the defect density of the channel layer, improves the crystal quality of the semiconductor heterostructure, improves the breakdown voltage and the current collapse effect of a device, and can be applied to the development of low-cost high-frequency and high-power semiconductor devices such as high-mobility transistors of AlGaN/GaN heterostructure.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure according to the present invention.
FIG. 2 is a flow chart of a method for fabricating a semiconductor structure according to the present invention.
Description of the element reference numerals
1 substrate
2 nucleation layer
3 control layer
41 first buffer layer
42 second buffer layer
5 channel layer
6 insert layer
7 barrier layer
S10-S80
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 2, in order to solve the technical problems of the prior art that the semiconductor heterostructure cannot simultaneously satisfy the requirements of a high-resistance buffer layer and a high-quality channel layer 5, and has poor breakdown resistance and easy occurrence of current collapse, the invention provides a preparation method of the semiconductor heterostructure, which comprises the following steps:
step S10 is performed to provide a substrate 1, where the substrate 1 includes a silicon substrate or a silicon carbide substrate, for example, a single crystal silicon substrate may be used.
Step S20 is executed to form a nucleation layer 2 on the substrate 1, wherein the material of the nucleation layer 2 includes aluminum gallium nitride or aluminum nitride; the thickness of the nucleation layer 2 is 10 nm-2 μm.
Step S30 is performed to form a first buffer layer 41 on the nucleation layer 2; forming a second buffer layer 42 on the first buffer layer 41; the material of the first buffer layer 41 includes gallium nitride or aluminum gallium nitride; the material of the second buffer layer 42 includes gallium nitride or aluminum gallium nitride; the total thickness of the first buffer layer 41 and the second buffer layer 42 is not less than 3 μm, wherein the thickness of the second buffer layer 42 is not less than 1 μm.
In order to achieve a high resistance buffer layer resistivity and channel layer 5 crystal quality, the first buffer layer 41 has a first doping concentration, and the second buffer layer 42 has a second doping concentration, wherein the first doping concentration is greater than the second doping concentration. As an example, the first doping concentration is greater than 1x1019Atom/cm3The second doping concentration is 1x1018Atom/cm3～1x1019Atom/cm3。
It should be noted that the doping element in the first buffer layer 41 and the second buffer layer 42 includes a carbon element or an iron element, and as an example, the doping element may be a carbon element.
In one embodiment, the step of forming the first buffer layer 41 and the second buffer layer 42 includes forming the first buffer layer 41 on the nucleation layer 2 by in-situ epitaxial doping; the second buffer layer 42 is formed on the first buffer layer 41 by in-situ epitaxial doping.
In another embodiment, the step of forming the first buffer layer 41 and the second buffer layer 42 includes forming a first buffer layer on the nucleation layer 2, and implanting a doping element into the first buffer layer through a thermal diffusion process to form the first buffer layer 41; forming a second buffer material layer on the first buffer layer 41, and implanting doping elements into the second buffer material layer through a thermal diffusion process to form the second buffer layer 42.
In yet another embodiment, the step of forming the first buffer layer 41 and the second buffer layer 42 includes forming a first buffer layer on the nucleation layer 2, and implanting a doping element into the first buffer layer through a thermal diffusion process to form the first buffer layer 41; forming a second buffer material layer on the first buffer layer 41, and implanting doping elements into the second buffer material layer through a thermal diffusion process to form the second buffer layer 42.
It is noted that, in some embodiments, at least one third buffer layer is formed between the first buffer layer 41 and the second buffer layer 42; the third buffer layer has a third doping concentration between the first doping concentration and the second doping concentration. In other embodiments, a fourth buffer layer, a fifth buffer layer, and more buffer layers may be further included between the first buffer layer 41 and the second buffer layer 42, where the buffer layers are disposed between the first buffer layer 41 and the second buffer layer 42, and doping concentrations of the buffer layers between the first buffer layer 41 and the second buffer layer 42 are sequentially reduced according to a concentration step distribution.
In an embodiment, a step of forming a control layer 3 between the nucleation layer 2 and the first buffer layer 41, where the control layer 3 is used for controlling stress in the gallium nitride-based epitaxial layer and suppressing defects in the gallium nitride-based epitaxial layer; the material of the control layer 3 comprises AlGaN, and the chemical general formula of the material of the control layer 3 is AlxGa1-xN, wherein x is more than or equal to 0.1 and less than or equal to 1; the thickness of the control layer 3 is 5nm to 20 μm.
Step S40 is executed to form a channel layer 5 on the first buffer layer 41, for providing a good transport channel for the two-dimensional electron gas, wherein the material of the channel layer 5 includes gan or ingan; the thickness of the channel layer 5 is 2nm to 1 μm.
Step S50 is performed to form a barrier layer 7 on the channel layer 5, forming the semiconductor heterostructure as shown in fig. 1. The material of the barrier layer 7 comprises aluminum gallium nitride or indium aluminum nitride; the thickness of the barrier layer 7 is 3nm to 50 nm; the barrier layer 7 and the channel layer 5 constitute a heterostructure for forming a high concentration of two-dimensional electron gas having high mobility characteristics at the interface of the barrier layer 7 and the channel layer 5.
In one embodiment, a step of forming an insertion layer 6 between the channel layer 5 and the barrier layer 7, the insertion layer 6 being used to reduce disorder scattering of the alloy; the barrier layer 7, the insertion layer 6 and the channel layer 5 together constitute a heterostructure for forming a high concentration of a two-dimensional electron gas having high migration characteristics at the interface of the barrier layer 7 and the channel layer 5; the material of the insertion layer 6 comprises aluminum nitride; the thickness of the insertion layer 6 is 0.5nm to 3 nm.
It should be noted that the growth method of the nucleation layer 2, the control layer, the epitaxial layer, the channel layer 5, the insertion layer 6 and the barrier layer 7 may use one of Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE) and vapor phase epitaxy (CVD), and may also use other methods such as Atomic Layer Deposition (ALD), without being limited thereto.
By the preparation method of the semiconductor heterostructure, a high-breakdown semiconductor heterostructure with the longitudinal breakdown voltage of 1000V and the transverse breakdown voltage of 670V can be obtained.
The preparation method of the semiconductor heterostructure can be applied to the manufacture of a heterostructure high-mobility transistor; the heterostructure high mobility transistor includes an AlGaN/GaN heterostructure high mobility transistor.
As shown in fig. 1, the present invention also provides a semiconductor heterostructure prepared by the above semiconductor heterostructure preparation method, which comprises a substrate 1, a nucleation layer 2, a buffer layer, a channel layer 5 and a barrier layer 7 sequentially disposed on the substrate 1.
In particular, the nucleation layer 2 is disposed on the substrate 1; the buffer layer is arranged on the nucleation layer 2 and has two main functions, namely dislocation and defect in the nucleation layer 2 are isolated, so that the channel layer 5 can grow on a good initial interface, the quality and the flatness of the heterojunction interface of the barrier layer 7/the channel layer 5 can be obviously improved, and the transport performance of two-dimensional electron gas is improved; secondly, preventing electrons in the channel layer 5 from leaking to a lower layer material (the substrate 1); the channel layer 5 is disposed on the first buffer layer 41 and is used for providing a good transport channel for the two-dimensional electron gas; and a barrier layer 7 disposed on the channel layer 5, the barrier layer 7 and the channel layer 5 constituting a heterostructure for forming a high concentration of a two-dimensional electron gas having a high mobility characteristic at an interface of the barrier layer 7 and the channel layer 5.
As shown in fig. 1, the buffer layer includes at least a first buffer layer 41 and a second buffer layer 42, the first buffer layer 41 is disposed on the nucleation layer 2, and the second buffer layer 42 is disposed on the first buffer layer 41; wherein the first buffer layer 41 has a first doping concentration, the second buffer layer 42 has a second doping concentration, the first doping concentration is greater than the second doping concentration, so that the first buffer layer 41 has a high resistivity, electrons in the channel layer 5 can be effectively prevented from being injected down into the substrate 1, the second buffer layer 42, due to its lower doping concentration, can grow a channel layer 5 with high lattice quality thereon, not only reducing the background electron concentration in the channel layer 5, reducing scattering and increasing the mobility of the electron gas, and moreover, lattice adaptation and thermal mismatch stress between the substrate 1 and the channel layer 5 can be effectively released, the cross-sectional characteristics of the heterojunction are improved, a high-quality barrier layer is extended, and the requirements of the semiconductor heterostructure on the resistivity of the high-resistance buffer layer and the crystal quality of the channel layer 5 are also met.
As an example, the substrate 1 includes a silicon substrate or a silicon carbide substrate, but may also include an implanted sapphire substrate or a gallium arsenide substrate; the material of the nucleation layer 2 comprises aluminum gallium nitride or aluminum nitride; the material of the first buffer layer 41 includes gallium nitride or aluminum gallium nitride; the material of the second buffer layer comprises gallium nitride or aluminum gallium nitrogen; the material of the channel layer 5 comprises gallium nitride or indium gallium nitride; the material of the barrier layer 7 comprises aluminum gallium nitride or indium aluminum nitride.
As an example, the total thickness of the first buffer layer 41 and the second buffer layer 42 is not less than 3 μm, wherein the thickness of the second buffer layer 42 is not less than 1 μm.
As an example, the thickness of the nucleation layer 2 is 10nm to 2 μm; the thickness of the channel layer 5 is 2 nm-1 μm; the thickness of the barrier layer 7 is 3nm to 50 nm.
In one embodiment, as shown in fig. 1, an insertion layer 6 is further disposed between the channel layer 5 and the barrier layer 7, and the insertion layer 6 is used for reducing disorder scattering of the alloy; the barrier layer 7, the insertion layer 6 and the channel layer 5 together constitute a heterostructure for forming a high concentration of a two-dimensional electron gas having high migration characteristics at the interface of the barrier layer 7 and the channel layer 5. As an example, the material of the insertion layer 6 includes aluminum nitride; the thickness of the insertion layer 6 is 0.5nm to 3 nm.
In one embodiment, as shown in fig. 1, a control layer 3 is further disposed between the nucleation layer 2 and the first buffer layer 41. As an example, the material of the control layer 3 includes aluminum gallium nitride, and the chemical formula of the material of the control layer 3 is AlxGa1-xN, wherein x is more than or equal to 0.1 and less than or equal to 1; the thickness of the control layer 3 is 5nm to 20 μm.
In one embodiment, the buffer layer further includes a third buffer layer (not shown) located between the first buffer layer 41 and the second buffer layer 42; the third buffer layer has a third doping concentration between the first doping concentration and the second doping concentration. In other embodiments, the buffer layers may further include a fourth buffer layer, a fifth buffer layer, and more buffer layers, where the buffer layers are disposed between the first buffer layer 41 and the second buffer layer 42, and the doping concentrations of the buffer layers between the first buffer layer 41 and the second buffer layer 42 are sequentially reduced according to a concentration step distribution.
The doping elements in the first buffer layer 41 and the second buffer layer 42 include carbon or iron, and as an example, the doping manner may be in-situ epitaxial doping, where in-situ epitaxial doping refers to changing the concentration of unintentional doping by controlling experimental conditions during the process of forming the first buffer layer 41 and the second buffer layer 42; of course, an ion implantation doping process or a thermal diffusion doping process may also be used, but not limited thereto.
As an example, the first doping concentration is greater than 1x1019Atom/cm3The second doping concentration is 1x1018Atom/cm3～1x1019Atom/cm3。
The longitudinal breakdown voltage of the semiconductor heterostructure can reach 1000V, and the transverse breakdown voltage can reach 670V.
It should be noted that the semiconductor heterostructure can be applied to specific semiconductor devices (such as high-frequency and high-power devices) to improve the breakdown voltage and current collapse effect of the devices and improve the performance of the devices. Such as AlGaN/GaN heterostructure high mobility transistors including the semiconductor conformal structures described above.
The preparation of the semiconductor heterostructure according to the invention will now be described with reference to specific examples.
Example 1
(1) A single crystal silicon substrate 1 is selected, and the crystal orientation of silicon includes silicon (111), silicon (100), silicon (110), and the like, but other substrates 1 such as silicon carbide may be used without limitation.
(2) Growing AlGaN or aluminum nitride on a monocrystalline silicon substrate 1 as a nucleating layer 2 at the growth temperature of 900-1200 ℃, the growth pressure of 10-200mbar and the growth thickness of 10 nm-2 mu m.
(3) And epitaxially growing AlGaN on the nucleation layer 2 to serve as a control layer, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, the growth thickness is 10 nm-10 mu m, the molar component of aluminum is 100-10%, and the layer plays a role in regulating and controlling stress and inhibiting defects.
(4) Growing an epitaxial layer of gallium nitride on the control layer 3, the usual methods for growing epitaxial layers of gallium nitride such as TMGa/TEGa and nitrogen as Ga and N sources, respectively, with ultrapure hydrogen as carrier gas, and the growth of GaN material being carried out at high temperature by decomposing Ga and NH from TMGa or TEGa3The reversible reaction equation is as follows: ga + NH3＝GaN+3/2H2In this embodiment, the unintentional doping concentration of carbon is changed by changing the growth temperature, the five-to-three ratio, the ammonia gas flow rate, the pressure, and other conditions, wherein the high resistance gallium nitride buffer layer includes a first buffer layer 41 with a high carbon doping concentration and a second buffer layer 42 with a relatively low carbon doping concentration, the carbon doping concentration of the first buffer layer 41 is greater than 1 × 1019Atom/cm3The second buffer layer 42 has a carbon doping concentration of less than 1 × 1019Atom/cm3But greater than 1X1018Atom/cm3(ii) a The thickness of the first buffer layer 41 and the second buffer layer 42 is more than 3 μm in total, and the thickness of the second buffer layer 42 is more than 1 μm; as an example, the growth temperature of the gallium nitride epitaxial layer is 900-1100 ℃, and the growth pressure is 10-200 mbar.
(5) Growing a gallium nitride channel layer 5 on the gallium nitride epitaxial layer, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, the thickness is 2 nm-1.0 mu m, and a good conveying channel is provided for two-dimensional electron gas.
(6) And growing an aluminum nitride insertion layer 6 on the gallium nitride channel layer 5 to reduce alloy disordered scattering, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, and the thickness is 0.5-3.0 nm.
(7) An aluminum gallium nitrogen barrier layer 7 grows on the aluminum nitride insertion layer 6, the growth temperature is 750-1200 ℃, the growth pressure is 10-200mbar, the thickness is 3 nm-50 nm, the aluminum gallium nitrogen barrier layer and the gallium nitride channel layer 5 and the aluminum nitride insertion layer 6 below the aluminum gallium nitride barrier layer form a heterostructure together, and high-concentration two-dimensional electron gas with high migration characteristics is formed at the interface of the heterostructure.
Example 2
(1) A single crystal silicon substrate 1 is selected, and the crystal orientation of silicon includes silicon (111), silicon (100), silicon (110), and the like, but other substrates 1 such as silicon carbide may be used without limitation.
(2) Growing AlGaN or aluminum nitride on a monocrystalline silicon substrate 1 as a nucleating layer 2 at the growth temperature of 900-1200 ℃, the growth pressure of 10-200mbar and the growth thickness of 10 nm-2 mu m.
(3) And epitaxially growing AlGaN on the nucleation layer 2 to serve as a control layer 3, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, the growth thickness is 10 nm-10 mu m, the molar component of aluminum is 100-10%, and the layer plays a role in regulating and controlling stress and inhibiting defects.
(4) Growing a gallium nitride epitaxial layer on the control layer 3, wherein the growth temperature is 900-1100 ℃, the growth pressure is 10-200mbar, and the concentration of the unintentional doped carbon is changed by changing the conditions of the growth temperature, the five-to-three ratio, the ammonia gas flow, the pressure and the like, wherein the high-resistance gallium nitride buffer layer comprises a first buffer layer 41 with high carbon doping concentration and a second buffer layer 42 with relatively low carbon doping concentration, and the carbon doping concentration of the first buffer layer 41 is more than 1x1019Atom/cm3The second buffer layer 42 has a carbon doping concentration of less than 1 × 1019Atom/cm3But greater than 1X1018Atom/cm3(ii) a The thicknesses of the first and second buffer layers 41 and 42 are greater than 3 μm in total, and the thickness of the second buffer layer 42 is greater than 1 μm.
(5) Growing a gallium nitride channel layer 5 on the aluminum gallium nitrogen epitaxial layer, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, the thickness is 2 nm-1.0 mu m, and a good conveying and transporting channel is provided for two-dimensional electron gas.
(6) And growing an aluminum nitride insertion layer 6 on the gallium nitride channel layer 5 to reduce alloy disordered scattering, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, and the thickness is 0.5-3.0 nm.
(7) An indium aluminum nitrogen barrier layer 7 grows on the aluminum nitride insertion layer 6, the growth temperature is 750-1200 ℃, the growth pressure is 10-200mbar, the thickness is 3-50 nm, the indium aluminum nitrogen barrier layer and the gallium nitride channel layer 5 and the aluminum nitride insertion layer 6 below the indium aluminum nitrogen barrier layer form a heterostructure together, and high-concentration two-dimensional electron gas with high migration characteristics is formed at the interface of the heterostructure.
Example 3
(1) A single crystal silicon substrate 1 is selected, and the crystal orientation of silicon includes silicon (111), silicon (100), silicon (110), and the like, but other substrates 1 such as silicon carbide may be used without limitation.
(2) Growing AlGaN or aluminum nitride on a monocrystalline silicon substrate 1 as a nucleating layer 2 at the growth temperature of 900-1200 ℃, the growth pressure of 10-200mbar and the growth thickness of 10 nm-2 mu m.
(3) And epitaxially growing AlGaN on the nucleation layer 2 to serve as a control layer 3, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, the growth thickness is 10 nm-10 mu m, the molar component of aluminum is 23.4%, and the layer plays a role in regulating and controlling stress and inhibiting defects.
(4) Growing a gallium nitride epitaxial layer on the control layer 3, wherein the growth temperature is 900-1100 ℃, the growth pressure is 10-200mbar, and the concentration of the unintentional doped carbon is changed by changing the conditions of the growth temperature, the five-to-three ratio, the ammonia gas flow, the pressure and the like, wherein the high-resistance gallium nitride buffer layer comprises a first buffer layer 41 with high carbon doping concentration and a second buffer layer 42 with relatively low carbon doping concentration, and the carbon doping concentration of the first buffer layer 41 is more than 1x1019Atom/cm3The second buffer layer 42 has a carbon doping concentration of less than 1 × 1019Atom/cm3But greater than 1X1018Atom/cm3(ii) a The thicknesses of the first and second buffer layers 41 and 42 are greater than 3 μm in total, and the thickness of the second buffer layer 42 is greater than 1 μm.
(5) An indium gallium nitride channel layer 5 grows on a gallium nitride epitaxial layer, the molar composition of indium in the indium gallium nitride channel layer 5 is 0.01-100%, the growth temperature is 600-1200 ℃, the growth pressure is 10-1000 mbar, the thickness is 2 nm-1.0 mu m, and a good conveying and transporting channel is provided for two-dimensional electron gas.
(6) And growing an aluminum nitride insertion layer 6 on the indium gallium nitride channel layer 5 to reduce alloy disordered scattering, wherein the growth temperature is 900-1200 ℃, the growth pressure is 10-200mbar, and the thickness is 0.5-3.0 nm.
(7) Growing an aluminum gallium nitrogen barrier layer 7 or an indium aluminum nitrogen barrier layer 7 on the aluminum nitride insertion layer 6, wherein the growth temperature is 750-1200 ℃, the growth pressure is 10-200mbar, the thickness is 3 nm-50 nm, the aluminum gallium nitride channel layer 5 and the aluminum nitride insertion layer 6 below the aluminum gallium nitride barrier layer form a heterostructure together, and high-concentration two-dimensional electron gas with high migration characteristic is formed at the interface of the heterostructure.
In summary, the present invention provides a semiconductor heterostructure manufacturing method and a use thereof, the semiconductor heterostructure manufacturing method includes the steps of providing a substrate; forming a nucleation layer on the substrate; forming a first buffer layer on the nucleation layer; forming a second buffer layer on the first buffer layer; forming a channel layer on the first buffer layer; forming a barrier layer on the channel layer, wherein the barrier layer and the channel layer form a heterostructure; wherein the first buffer layer has a first doping concentration and the second buffer layer has a second doping concentration, the first doping concentration being greater than the second doping concentration. The invention introduces at least two doping concentration buffer layers in the semiconductor heterostructure, can simultaneously consider the requirements of the resistivity of the high-resistance buffer layer and the crystal quality of the channel layer, has simple preparation process, can greatly reduce the defect density of the channel layer, improves the crystal quality of the semiconductor heterostructure, improves the breakdown voltage and the current collapse effect of a device, and can be applied to the development of low-cost high-frequency and high-power semiconductor devices such as high-mobility transistors of AlGaN/GaN heterostructure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method of fabricating a semiconductor heterostructure, the method comprising the steps of:
providing a substrate;
forming a nucleation layer on the substrate;
forming a first buffer layer on the nucleation layer;
forming a second buffer layer on the first buffer layer;
forming a channel layer on the first buffer layer; and the number of the first and second groups,
forming a barrier layer on the channel layer, wherein the barrier layer and the channel layer form a heterostructure;
wherein the first buffer layer has a first doping concentration and the second buffer layer has a second doping concentration, the first doping concentration being greater than the second doping concentration.
2. A semiconductor heterostructure manufacturing method according to claim 1, further comprising a step of forming an insertion layer between the channel layer and the barrier layer, the insertion layer and the channel layer together constituting a heterostructure; the material of the insertion layer comprises aluminum nitride.
3. The method of claim 1, further comprising forming a control layer between the nucleation layer and the first buffer layer; the material of the control layer comprises aluminum gallium nitrogen, and the chemical general formula of the material of the control layer is AlxGa1-xN, wherein x is more than or equal to 0.1 and less than or equal to 1.
4. The method of claim 1, wherein the substrate comprises a silicon substrate or a silicon carbide substrate; the material of the nucleation layer comprises aluminum gallium nitride or aluminum nitride; the material of the first buffer layer comprises gallium nitride or aluminum gallium nitrogen; the material of the second buffer layer comprises gallium nitride or aluminum gallium nitrogen; the material of the channel layer comprises gallium nitride or indium gallium nitride; the barrier layer comprises aluminum gallium nitride or indium aluminum nitride.
5. The method of fabricating a semiconductor heterostructure according to claim 1, further comprising:
forming the first buffer layer on the nucleation layer by in-situ epitaxial doping;
and forming the second buffer layer on the first buffer layer in an in-situ epitaxial doping mode.
6. The method of fabricating a semiconductor heterostructure according to claim 1, further comprising:
forming a first buffer material layer on the nucleation layer, and implanting doping elements into the first buffer material layer through an ion implantation process or a thermal diffusion process to form the first buffer layer;
and forming a second buffer material layer on the first buffer layer, and injecting doping elements into the second buffer material layer through an ion injection process thermal diffusion process to form the second buffer layer.
7. The method of claim 1, further comprising forming at least a third buffer layer between the first buffer layer and the second buffer layer; the third buffer layer has a third doping concentration between the first doping concentration and the second doping concentration.
8. The method for preparing the semiconductor heterostructure according to any one of claims 1 to 7, wherein the doping element in the first buffer layer and the second buffer layer comprises a carbon element or an iron element.
9. The method of claim 8, wherein the first doping concentration is greater than 1x1019Atom/cm3Said second dopingConcentration of 1x1018Atom/cm3～1x1019Atom/cm3。
10. Use of a semiconductor heterostructure manufacturing method according to any of claims 1 to 9, for the manufacture of heterostructure high mobility transistors.
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