CN117613071A - Enhancement mode gallium nitride high electron mobility transistor device - Google Patents
Enhancement mode gallium nitride high electron mobility transistor device Download PDFInfo
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- CN117613071A CN117613071A CN202410096071.XA CN202410096071A CN117613071A CN 117613071 A CN117613071 A CN 117613071A CN 202410096071 A CN202410096071 A CN 202410096071A CN 117613071 A CN117613071 A CN 117613071A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 44
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 30
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 11
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 description 16
- 230000005533 two-dimensional electron gas Effects 0.000 description 14
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 11
- 229910052799 carbon Inorganic materials 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 229910052742 iron Inorganic materials 0.000 description 6
- 150000001721 carbon Chemical group 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 125000004432 carbon atom Chemical group C* 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021386 carbon form Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
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Abstract
The invention discloses an enhanced gallium nitride high electron mobility transistor device. The device includes: a substrate; the first buffer layer is positioned on the substrate and is an acceptor level doped III-V semiconductor layer; the second buffer layer is positioned on the surface, far away from the substrate, of the first buffer layer, and is an acceptor level doped III-V semiconductor layer, wherein the acceptor level doping concentration of the second buffer layer is larger than that of the first buffer layer, and the thickness of the second buffer layer is smaller than that of the first buffer layer; the gallium aluminum nitride back barrier layer is positioned on the surface of the second buffer layer far away from the first buffer layer, and the proportion of aluminum atoms to gallium atoms in the gallium aluminum nitride back barrier layer is 1:9, a step of performing the process; and the epitaxial layer is positioned on the surface of the gallium aluminum nitride back barrier layer. The technical scheme provided by the embodiment of the invention reduces the leakage current of the device and improves the reliability of the electrical parameters of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an enhanced gallium nitride transistor device with high electron mobility.
Background
Existing enhancement mode gallium nitride High Electron Mobility Transistor (HEMT) devices have a carbon doped high resistance layer to reduce leakage and increase vertical withstand voltage. However, the doped carbon forms a deep acceptor level, and electrons in the two-dimensional electron gas from the channel layer are captured during the switching process of the device, so that the two-dimensional electron gas is reduced when the device is operated again, and the resistance is increased, which is the so-called dynamic resistance peak value is increased, and the conduction loss is increased.
As shown in fig. 1, fig. 1 is a schematic structural diagram of an enhanced gan hemt device provided in the prior art, and in order to effectively reduce a dynamic resistance peak value and achieve the purpose of reducing on-loss, a gan-al back barrier layer is disposed between a channel layer and a carbon-doped high-resistance layer in the prior art. Wherein reference numerals in fig. 1 are as follows: 1-substrate, 2-high-resistance layer doped with carbon, 3-gallium nitride aluminum back barrier layer, 4-channel layer, 5-barrier layer, 6-P type nitride layer, 7-grid electrode, 8-source electrode and 9-drain electrode.
However, due to the difference of aluminum components at the interface accessories of the gallium aluminum nitride back barrier layer and the carbon doped high-resistance layer, two-dimensional electron gas of a parasitic channel can be formed at the interface accessories, and the parasitic channel can not be closed when the device is in an off state, so that electric leakage of the device can be increased, and the reliability of the electrical parameters of the device is affected.
Disclosure of Invention
The invention provides an enhanced gallium nitride high electron mobility transistor device, which is used for reducing the leakage current of the device and improving the reliability of the electrical parameters of the device.
According to an aspect of the present invention, there is provided an enhanced gallium nitride high electron mobility transistor device comprising:
a substrate;
the first buffer layer is positioned on the substrate and is an acceptor level doped III-V semiconductor layer;
the second buffer layer is positioned on the surface, far away from the substrate, of the first buffer layer, and is an acceptor level doped III-V semiconductor layer, wherein the acceptor level doping concentration of the second buffer layer is larger than that of the first buffer layer, and the thickness of the second buffer layer is smaller than that of the first buffer layer;
the gallium aluminum nitride back barrier layer is positioned on the surface, far away from the first buffer layer, of the second buffer layer, and the proportion of aluminum atoms to gallium atoms in the gallium aluminum nitride back barrier layer is 1:9, a step of performing the process;
the epitaxial layer is positioned on the surface of the gallium aluminum nitride back barrier layer, which is far away from the second buffer layer;
the P-type nitride layer is positioned on the surface of the epitaxial layer, which is far away from the gallium nitride aluminum back barrier layer;
the grid electrode is positioned on the surface, away from the epitaxial layer, of the P-type nitride layer;
the source electrode is positioned on the surface of the epitaxial layer, which is far away from the gallium nitride aluminum back barrier layer;
and the drain electrode is positioned on the surface of the epitaxial layer, which is far away from the gallium nitride aluminum back barrier layer.
Optionally, the first buffer layer is a carbon-doped group iii-v semiconductor layer;
the second buffer layer is a carbon-doped III-V semiconductor layer.
Optionally, the first buffer layer is an iron-doped group iii-v semiconductor layer;
the second buffer layer is an iron-doped III-V semiconductor layer.
Optionally, the acceptor level doping concentration of the first buffer layer is greater than or equal to 8×10 18 /cm 3 And less than or equal to 2X 10 19 /cm 3 。
Optionally, the acceptor level doping concentration of the second buffer layer is greater than or equal to 5×10 19 /cm 3 And less than or equal to 1X 10 20 /cm 3 。
Optionally, the first buffer layer includes a gallium nitride layer or an aluminum gallium nitride layer doped with an acceptor level;
and/or the second buffer layer comprises a gallium nitride layer or an aluminum gallium nitride layer doped with an acceptor level.
Optionally, the thickness of the second buffer layer is greater than or equal to 50 nanometers and less than or equal to 100 nanometers.
Optionally, a third buffer layer is further included, the third buffer layer being located between the substrate and the first buffer layer;
the third buffer layer comprises a stack of gallium aluminum nitride buffer layers and superlattice buffer layers.
Optionally, the superlattice buffer layer is a superlattice buffer layer doped with an acceptor level.
Optionally, the superlattice buffer layer is a carbon doped superlattice buffer layer or an iron doped superlattice buffer layer.
According to the technical scheme provided by the embodiment of the invention, the first buffer layer is an III-V semiconductor layer doped with an acceptor level, and can be used for reducing electric leakage and increasing vertical withstand voltage.
The gallium aluminum nitride back barrier layer is positioned on the surface of the second buffer layer far away from the first buffer layer, and the proportion of aluminum atoms to gallium atoms in the gallium aluminum nitride back barrier layer is 1: and 9, the gallium aluminum nitride back barrier layer can effectively reduce the dynamic resistance peak value, thereby achieving the purpose of reducing the conduction loss. The arrangement of the gallium aluminum nitride back barrier layer can prevent the doped atoms in the first buffer layer from forming deep acceptor energy levels, and electrons in the two-dimensional electron gas from the channel layer in the epitaxial layer are prevented from being captured in the switching process of the device, so that the two-dimensional electron gas is prevented from being reduced when the device works again, and resistance is prevented from being increased.
The second buffer layer is an acceptor level doped III-V semiconductor layer, wherein the acceptor level doping concentration of the second buffer layer is larger than that of the first buffer layer, and the second buffer layer can enable a parasitic channel between the gallium aluminum nitride back barrier layer and the first buffer layer to be formed in the acceptor level deep doped second buffer layer. The arrangement of the second buffer layer can avoid the two-dimensional electron gas of a parasitic channel formed at the interface accessory of the gallium aluminum nitride back barrier layer and the first buffer layer due to the difference of aluminum components, and the parasitic channel cannot be closed when the device is in the off state, so that the electric leakage of the device is increased, and the reliability of the electrical parameters of the device is affected.
In addition, the acceptor level doping concentration of the second buffer layer is greater than that of the first buffer layer, and the thickness of the second buffer layer is smaller than that of the first buffer layer, and the acceptor level doping concentration of the most acceptor level doped group iii-v semiconductor layer is a normal concentration (the acceptor level doping concentration of the first buffer layer is a normal concentration), and the deep acceptor level trap is also a normal level, so that dynamic resistance is not deteriorated.
In summary, the technical scheme provided by the embodiment of the invention reduces the leakage current of the device and improves the reliability of the electrical parameters of the device.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an enhanced gan hemt device according to the prior art;
fig. 2 is a schematic structural diagram of an enhanced gan hemt device according to an embodiment of the invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or means is not necessarily limited to those steps or means that are expressly listed or inherent to such process, method, article, or apparatus.
In order to reduce leakage current of a device and improve reliability of electrical parameters of the device, the embodiment of the invention provides the following technical scheme:
as shown in fig. 2, fig. 2 is a schematic structural diagram of an enhanced gan hemt device according to an embodiment of the invention, the enhanced gan hemt device comprising: a substrate 100; a first buffer layer 400, the first buffer layer 400 being located above the substrate 100, the first buffer layer 400 being an acceptor level doped group iii-v semiconductor layer; the second buffer layer 500, the second buffer layer 500 is located on the surface of the first buffer layer 400 away from the substrate 100, the second buffer layer 500 is an acceptor level doped group iii-v semiconductor layer, wherein the acceptor level doping concentration of the second buffer layer 500 is greater than the acceptor level doping concentration of the first buffer layer 400; gallium aluminum nitride back barrier layer 600, gallium aluminum nitride back barrier layer 600 is located on the surface of second buffer layer 500 remote from first buffer layer 400, and the ratio of aluminum atoms to gallium atoms in gallium aluminum nitride back barrier layer 600 is 1:9, a step of performing the process; the epitaxial layer 700, the epitaxial layer 700 is located on the surface of the gallium nitride aluminum back barrier layer 600 away from the second buffer layer 500; a P-type nitride layer 800, the P-type nitride layer 800 being located on a surface of the epitaxial layer 700 remote from the aluminum gallium nitride back barrier layer 600; the gate 900, the gate 900 is located on the surface of the P-type nitride layer 800 away from the epitaxial layer 700; a source 901, the source 901 being located on a surface of the epitaxial layer 700 remote from the aluminum gallium nitride back barrier layer 600; a drain 902, the drain 902 being located on a surface of the epitaxial layer 700 remote from the aluminum gallium nitride back barrier layer 600.
Optionally, the epitaxial layer 700 includes a channel layer 701 and a barrier layer 702. A high concentration of two-dimensional electron gas is present near the interface between the channel layer 701 and the barrier layer 702. For example, the P-type nitride layer 800 may be P-type GaN, which is used to deplete the two-dimensional electron gas at the corresponding location of the underlying barrier layer 702, and may turn off the gallium nitride device at low voltage.
Due to the difference of aluminum components at the attachments of the gallium aluminum nitride back barrier layer 600 and the first buffer layer 400, two-dimensional electron gas of a parasitic channel can be formed at the attachment of the interface of the gallium aluminum back barrier layer and the first buffer layer, and the parasitic channel can not be closed when the device is in an off state, so that electric leakage of the device can be increased, and the reliability of the electrical parameters of the device is affected.
According to the technical scheme provided by the embodiment of the invention, the first buffer layer 400 is an acceptor level doped III-V semiconductor layer, and can be used for reducing electric leakage and increasing vertical withstand voltage.
The aluminum gallium nitride back barrier layer 600 is located on the surface of the second buffer layer 500 away from the first buffer layer 400, and the ratio of aluminum atoms to gallium atoms in the aluminum gallium nitride back barrier layer 600 is 1:9, the gallium aluminum nitride back barrier layer 600 can effectively reduce the dynamic resistance peak value, thereby achieving the purpose of reducing the conduction loss. The gallium aluminum nitride back barrier layer 600 can prevent the doped atoms in the first buffer layer 400 from forming deep acceptor energy levels, and avoid capturing electrons in the two-dimensional electron gas from the channel layer 701 in the epitaxial layer 700 during the switching process of the device, thereby avoiding reducing the two-dimensional electron gas when the device operates again and avoiding increasing the resistance.
The second buffer layer 500 is an acceptor level doped iii-v semiconductor layer, where the acceptor level doping concentration of the second buffer layer 500 is greater than the acceptor level doping concentration of the first buffer layer 400, and the second buffer layer 500 may allow a parasitic channel between the gallium aluminum nitride back barrier layer 600 and the first buffer layer 400 to appear in the acceptor level deep doped second buffer layer 500, because the acceptor level of the second buffer layer 500 is deeply doped, impurity scattering is increased, and electron mobility may be reduced. The second buffer layer 500 is disposed, so that it can avoid the parasitic channel formed by the two-dimensional electron gas at the interface of the gallium nitride aluminum back barrier layer 600 and the first buffer layer 400 due to the difference of aluminum components, and the parasitic channel can not be closed when the device is in the off state, thus increasing the leakage of the device and affecting the reliability of the electrical parameters of the device.
In addition, the acceptor level doping concentration of the second buffer layer 500 is greater than that of the first buffer layer 400, and the thickness of the second buffer layer 500 is smaller than that of the first buffer layer 400, and the acceptor level doping concentration of the most acceptor level doped group iii-v semiconductor layer is a normal concentration (the acceptor level doping concentration of the first buffer layer 400 is a normal concentration), and the deep acceptor level trap is also a normal level, so that dynamic resistance is not deteriorated.
In summary, the technical scheme provided by the embodiment of the invention reduces the leakage current of the device and improves the reliability of the electrical parameters of the device.
Optionally, based on the above technical solution, as shown in fig. 2, the first buffer layer 400 is a carbon-doped iii-v semiconductor layer; the second buffer layer 500 is a carbon-doped group iii-v semiconductor layer.
Specifically, in the first buffer layer 400, the group iii-v semiconductor layer is doped with carbon atoms to form an acceptor level doped group iii-v semiconductor layer, which can be used to reduce leakage and increase vertical withstand voltage.
In the second buffer layer 500, the group iii-v semiconductor layer is doped with carbon atoms to form an acceptor level doped group iii-v semiconductor layer, wherein the carbon atom doping concentration of the second buffer layer 500 is greater than that of the first buffer layer 400, and the second buffer layer 500 may allow a parasitic channel between the gallium aluminum nitride back barrier layer 600 and the first buffer layer 400 to appear in the acceptor level deep doped second buffer layer 500, because the second buffer layer is deeply doped with carbon atoms, impurity scattering is increased, and electron mobility may be reduced. The second buffer layer 500 is disposed, so that it can avoid the parasitic channel formed by the two-dimensional electron gas at the interface of the gallium nitride aluminum back barrier layer 600 and the first buffer layer 400 due to the difference of aluminum components, and the parasitic channel can not be closed when the device is in the off state, thus increasing the leakage of the device and affecting the reliability of the electrical parameters of the device.
In addition, the carbon atom doping concentration of the second buffer layer 500 is greater than that of the first buffer layer 400, and the thickness of the second buffer layer 500 is smaller than that of the first buffer layer 400, and the acceptor level doping concentration of the most carbon atom doped group iii-v semiconductor layer is a normal concentration (the carbon atom doping concentration of the first buffer layer 400 is a normal concentration), and the deep acceptor level trap is also a normal level, so that dynamic resistance is not deteriorated.
Optionally, based on the above technical solution, as shown in fig. 2, the first buffer layer 400 is an iron-doped iii-v semiconductor layer; the second buffer layer 500 is an iron-doped group iii-v semiconductor layer.
Specifically, in the first buffer layer 400, the iron atoms dope the iii-v semiconductor layer to form an acceptor level doped iii-v semiconductor layer, which can be used to reduce leakage and increase vertical withstand voltage.
In the second buffer layer 500, the iron atoms are doped with the iii-v semiconductor layer to form an acceptor level doped iii-v semiconductor layer, wherein the iron atom doping concentration of the second buffer layer 500 is greater than that of the first buffer layer 400, and the second buffer layer 500 can enable a parasitic channel between the gallium aluminum nitride back barrier layer 600 and the first buffer layer 400 to appear in the acceptor level deep doped second buffer layer 500, because the second buffer layer is deeply doped with iron atoms, impurity scattering is increased, and electron mobility can be reduced. The second buffer layer 500 is disposed, so that it can avoid the parasitic channel formed by the two-dimensional electron gas at the interface of the gallium nitride aluminum back barrier layer 600 and the first buffer layer 400 due to the difference of aluminum components, and the parasitic channel can not be closed when the device is in the off state, thus increasing the leakage of the device and affecting the reliability of the electrical parameters of the device.
In addition, the iron atom doping concentration of the second buffer layer 500 is greater than that of the first buffer layer 400, and the thickness of the second buffer layer 500 is smaller than that of the first buffer layer 400, and the acceptor level doping concentration of most of the iron atom doped iii-v semiconductor layers is a normal concentration (the iron atom doping concentration of the first buffer layer 400 is a normal concentration), and the deep acceptor level trap is also a normal level, so that dynamic resistance is not deteriorated.
Optionally, based on the above technical solution, as shown in fig. 2, the acceptor level doping concentration of the first buffer layer 400 is greater than or equal to 8×10 18 /cm 3 And less than or equal to 2X 10 19 /cm 3 The first buffer layer 400 is made to be in a high resistance state, and can be used to reduce leakage and increase vertical withstand voltage.
Optionally, based on the above technical solution, as shown in fig. 2, the acceptor level doping concentration of the second buffer layer 500 is greater than or equal to 5×10 19 /cm 3 And less than or equal to 1X 10 20 /cm 3 。
Specifically, the acceptor level doping concentration of the second buffer layer 500 is greater than or equal to 5×10 19 /cm 3 And less than or equal to 1X 10 20 /cm 3 Such that the acceptor level doping concentration of the second buffer layer 500 is greater than the acceptor level doping concentration of the first buffer layer 400.
Optionally, on the basis of the above technical solution, as shown in fig. 2, the first buffer layer 400 includes a gallium nitride layer or an aluminum gallium nitride layer doped with an acceptor level; and/or the second buffer layer 500 includes a gallium nitride layer or an aluminum gallium nitride layer doped with an acceptor level.
Alternatively, based on the above technical solution, as shown in fig. 2, the thickness of the second buffer layer 500 is greater than or equal to 50 nm and less than or equal to 100 nm.
Specifically, the acceptor level doping concentration of the second buffer layer 500 is greater than that of the first buffer layer 400, and the thickness of the second buffer layer 500 is less than that of the first buffer layer 400, wherein the thickness of the second buffer layer 500 is greater than or equal to 50 nm and less than or equal to 100 nm, and the acceptor level doping concentration of the most acceptor level doped group iii-v semiconductor layer is a normal concentration (the acceptor level doping concentration of the first buffer layer 400 is a normal concentration), and the deep acceptor level trap is also a normal level, so that dynamic resistance is not deteriorated.
Optionally, on the basis of the above technical solution, as shown in fig. 2, a third buffer layer is further included, where the third buffer layer is located between the substrate 100 and the first buffer layer 400; the third buffer layer comprises a stack of gallium aluminum nitride buffer layer 200 and superlattice buffer layer 300.
Specifically, the stack of the gan-al buffer layer 200 and the superlattice buffer layer 300 is used as a third buffer layer to match the lattices of the substrate 100 and the epitaxial layer 700, so as to improve the yield of the epitaxial layer 700.
Alternatively, as shown in fig. 2, the superlattice buffer layer 300 is an acceptor level doped superlattice buffer layer.
Specifically, the superlattice buffer layer 300 is an acceptor level doped superlattice buffer layer for matching crystal lattices of the substrate 100 and the first buffer layer 400, thereby improving yield of the first buffer layer 400.
Optionally, based on the above technical solution, as shown in fig. 2, the superlattice buffer layer 300 is a carbon doped superlattice buffer layer or an iron doped superlattice buffer layer, so that the doping atoms of the superlattice buffer layer 300 and the first buffer layer 400 are the same, and are used to match the lattices of the substrate 100 and the first buffer layer 400, thereby improving the yield of the first buffer layer 400.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. An enhanced gallium nitride high electron mobility transistor device, comprising:
a substrate;
the first buffer layer is positioned on the substrate and is an acceptor level doped III-V semiconductor layer;
the second buffer layer is positioned on the surface, far away from the substrate, of the first buffer layer, and is an acceptor level doped III-V semiconductor layer, wherein the acceptor level doping concentration of the second buffer layer is larger than that of the first buffer layer, and the thickness of the second buffer layer is smaller than that of the first buffer layer;
the gallium aluminum nitride back barrier layer is positioned on the surface, far away from the first buffer layer, of the second buffer layer, and the proportion of aluminum atoms to gallium atoms in the gallium aluminum nitride back barrier layer is 1:9, a step of performing the process;
the epitaxial layer is positioned on the surface of the gallium aluminum nitride back barrier layer, which is far away from the second buffer layer;
the P-type nitride layer is positioned on the surface of the epitaxial layer, which is far away from the gallium nitride aluminum back barrier layer;
the grid electrode is positioned on the surface, away from the epitaxial layer, of the P-type nitride layer;
the source electrode is positioned on the surface of the epitaxial layer, which is far away from the gallium nitride aluminum back barrier layer;
and the drain electrode is positioned on the surface of the epitaxial layer, which is far away from the gallium nitride aluminum back barrier layer.
2. The enhancement-mode gallium nitride high electron mobility transistor device of claim 1, wherein the first buffer layer is a carbon-doped group iii-v semiconductor layer;
the second buffer layer is a carbon-doped III-V semiconductor layer.
3. The enhancement-mode gallium nitride high electron mobility transistor device of claim 1, wherein the first buffer layer is an iron-doped group iii-v semiconductor layer;
the second buffer layer is an iron-doped III-V semiconductor layer.
4. The enhancement-mode gan hemt device of claim 1, wherein said first buffer layer has an acceptor level doping concentration of greater than or equal to 8 x 10 18 /cm 3 And less than or equal to 2X 10 19 /cm 3 。
5. The enhancement-mode gan hemt device of claim 4, wherein said second buffer layer has an acceptor level doping concentration of greater than or equal to 5 x 10 19 /cm 3 And less than or equal to 1X 10 20 /cm 3 。
6. The enhancement mode gallium nitride high electron mobility transistor device of claim 1, wherein the first buffer layer comprises an acceptor level doped gallium nitride layer or gallium aluminum nitride layer;
and/or the second buffer layer comprises a gallium nitride layer or an aluminum gallium nitride layer doped with an acceptor level.
7. The enhancement-mode gallium nitride high electron mobility transistor device of claim 1, wherein the second buffer layer has a thickness greater than or equal to 50 nanometers and less than or equal to 100 nanometers.
8. The enhancement-mode gallium nitride high electron mobility transistor device of claim 1, further comprising a third buffer layer, the third buffer layer being located between the substrate and the first buffer layer;
the third buffer layer comprises a stack of gallium aluminum nitride buffer layers and superlattice buffer layers.
9. The enhancement-gallium-nitride high-electron-mobility transistor device of claim 8, wherein the superlattice buffer layer is an acceptor level doped superlattice buffer layer.
10. The enhancement-mode gallium nitride high electron mobility transistor device of claim 8, wherein the superlattice buffer layer is a carbon-doped superlattice buffer layer or an iron-doped superlattice buffer layer.
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