JPH0346241A - Semiconductor heterostructure and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to form an active layer while the good crystal quality of the active layer is held by a method wherein the compositional ratio of InAs of a buffer layer is changed almost linearly to the thickness direction between the side of a GaAs substrate and the active layer and the rate of change of the compositional ratio is set as 1.5X10<-3>/nm or lower. CONSTITUTION:The composition (X) of InAs of a non-doped InxGa1-xAs buffer layer 12 is set as 0 on the side of a semi-insulative GaAs substrate 10, is increased linearly toward the side of the surface, is set as 0.53 in the interface between the layer 12 and a non-doped In0.52Al0.48As barrier layer 13, is set as a composition, which can make a lattice matching with each layer 13 to 16 located on the side of the surface from the layer 13, and the rate of change of the composition (x) is set as 1.5X10<-3>/nm or lower. Because of this, the crystallizability of an active layer formed on the buffer layer 12 is remarkedly improved and the crystal quality of the active layer can be favorably held. Thereby, while the InGaAs and InAlAs layers, whose grating constants are greatly different from one another, are grown, the active layer can be formed so as to have a superior crystal quality.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor heterostructure and a method for manufacturing the same.

(Prior art) N-type A Q Ga on a non-doped Ga As layer
A high electron mobility transistor (hereinafter referred to as HEMT) has been devised in which a gate electrode controls the concentration of a two-dimensional electron gas with high mobility generated at a heterojunction interface where an As layer is formed. Since this HEMT is promising as a high-speed switching element and a microwave element, research is being actively conducted on materials and structures to further improve its characteristics.

In terms of materials, an InP substrate is used instead of a GaAs substrate,
Ino, 53Ga, lattice matched to InP, 4.
As and n-type I no, sz AGo, 46 As
A heterostructure consisting of G a A s / A Q
Since it exhibits higher electron mobility, electron saturation velocity, and two-dimensional electron gas concentration than GaAs-based HEMTs, it has higher performance than Al)GaAs/GaAs-based HEMTs.
It is attracting attention as something that can achieve this.

However, InP substrates are currently not only more expensive than GaAs substrates, but also have poor quality.
It is inferior to the InP substrate, and there are problems such as unnecessary impurities being incorporated into the crystal layer formed on the InP substrate, and
There was a problem that it was more easily broken than an aAs substrate. As a countermeasure to this problem, GaAs substrates and Si substrates with excellent crystal quality are used.

A new technology that can grow InGaAs and InAQAs crystals is desired. Such technology is also important in producing integrated circuits for light-receiving and light-emitting devices and high-speed electronic devices.

InGaAs or InAQAs, for example, G
A problem when forming on an aAs substrate is the difference in lattice constant between InGaAs and InA (IAs and GaAs).

When forming an In, Gao, or 7As layer on GaAs, it is necessary to make the layer as thin as a few nm in order to suppress crystal defects caused by differences in lattice constants, making it impractical. . Therefore, since the occurrence of crystal defects is unavoidable, methods are being considered to reduce the defect density in the device active layer.

The conventional method based on this idea is to first layer InGaAs and InAlA as a buffer layer on a GaAs substrate.
The active layer of the device is formed on a superlattice made of a thin layer of s.

The conventional semiconductor heterostructure of this type will be explained with reference to FIG. The figure is an enlarged cross-sectional view of the main part, and the semiconductor heterostructure is on a GaAs substrate l.

3mm thick I n A Q A s film and lnm thick I
Thickness 1.NGaAs films are alternately stacked to form a superlattice.
A buffer layer 2 of 8 μm is formed, and HEM is further formed on it.
InGaAs with a thickness of 30n+m which becomes the channel layer of T
Layer 3 was formed. Furthermore, a non-doped InGaAs layer 4 with a thickness of 2.5 nm is formed by laminating thereon,
Planar-doped Si layer 5, 25 nm thick non-doped I n A Q A s layer 6, planar-doped S
The non-doped InGaAs layer 8 having a thickness of LL12 and the n-type InGaAs layer 9 having a thickness of 15 nm supply electrons to the InGaAs layer 3 and form an ohmic connection. (Y, K, Chen, G
,W.,Wang,W.,J.

5chaff, P.J., Ta5ker, K.Kav
anagh and L, F.

Eastn+an; I E D M Technic
al Didgest, p, 433° 1987).

(Problems to be Solved by the Invention) However, even though the superlattice buffer layer 2 is formed as described above, a few defects occur in the InGaAs layer 3 of the active layer. Further, as a result of experiments conducted by the present inventor, when such defects are observed, the electron mobility is 550 M/V, S, or 6000 M/V at room temperature.
There was a problem in that the value was approximately cd/V, S, which was significantly lower than the value of 104 d/V, S, or more when lattice matching was performed using an InP substrate.

The present invention solves the above problems and provides a semiconductor heterostructure having excellent crystal quality while growing InGaAs and InAQAs with significantly different lattice constants, and a method for manufacturing the same. .

(Means for Solving the Problems) In order to solve the above-mentioned all, the present invention provides
A method was used in which the s composition ratio X was set to O on the substrate side and gradually increased toward the active layer to obtain an InAs composition that lattice matched with the active layer on the active layer side, and the InAsnAs composition ratio was set to 1.5 10-”/na+ or less.

Further, when the buffer layer is grown by molecular beam epitaxy, the growth temperature is set to 450° C. or lower.

Furthermore, when an active layer is formed on a buffer layer formed at a temperature of 450°C or lower using molecular beam epitaxy, the growth temperature is raised from 450°C or higher to 530°C or lower.

In addition, InGa1-xAs buffer layer is
When forming the As active layer, an InA12As barrier layer having the same lattice constant as the InGaAs active layer is interposed between the InGaAs active layer and the InxGal-xAS buffer layer.

(Function) The In,Gal-xAs buffer layer in which the InAs composition is gradually increased from the substrate side to the active layer side significantly improves the crystallinity of the active layer formed on the buffer layer. This is considered to be because the generation of crystal defects is suppressed by this buffer layer, and almost no defects reach the active layer. However, In, 1 Gai-x
If the InAsnAs composition ratio of the As buffer layer is too large, the quality of the crystal deteriorates, and the buffer layer thickness is 1
Experiments have revealed that the rate of change should be 0.15 or less per 100n.

In other words, the rate of change in the composition of InAs is 1.5X10-3
/nm or less, it is possible to maintain good crystal quality.

In addition, the above I n z by molecular beam epitaxy method
The growth temperature of G ai-X As has a large effect on the crystallinity and surface texture of the active layer formed on the buffer layer. Growth temperature of buffer layer from 375℃ to 520℃
As a result of experiments conducted by varying the temperature up to 450° C., it was found that the temperature that provides good crystallinity and surface texture is approximately 450° C. or lower.

In addition, good results were obtained for the growth temperature of the active layer formed on the buffer layer even at the growth temperature of the buffer layer.
It has been found from experiments that the crystallinity of the active layer can be further improved when the temperature is raised to 530°C or higher.

Furthermore, InxGa1-xAs buffer layer and InxGa1-xAs buffer layer are
When forming an active layer of GaAs, InGaA of the active layer
By inserting a barrier layer of InAlAs that has a lattice match with s, propagation of crystal defects from the buffer layer to the active layer can be prevented, and the crystallinity of the active layer can be further improved. In addition, in the case of HEMT, the channel layer corresponds to the above-mentioned InGaAs active layer, but
Inserting a barrier layer of InAlAs is similar to that of InGaA
Since the two-dimensional electron gas accumulated in the s-channel layer is prevented from flowing through the In, 0at-xA1 layer, which contains many defects, the characteristics of the device are improved.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is an enlarged cross-sectional view of a main part of a semiconductor heterostructure according to the present invention, which is formed on a semi-insulating GaAs substrate IO with a thickness of 20 mm.
A non-doped GaAs buffer layer 11 with a thickness of 0 nm and a non-doped InxGal-x whose thickness will be described later.
As/(after forming buffer layer 12, thickness 20Q)
nm non-doped I no, st AOo, 41
As barrier layer 13, Inn, 5aGa with thickness loOnm
o, *tAs channel layer 14 43 nm thick non-doped Ino, 5zA (la, +sAs spacer layer 15 and 30 nm thick n-type Ino doped with Si at a high concentration,
, sz Al1°, and a HAs layer 16 were formed in this order. Note that n-type In6. The Si doping amount of the HAL, 4@As layer 16 was approximately 2×10”/aI.

InAsnAs of InxGaz-yAs buffer layer 12
Composition a A s O on the substrate 10 side, increasing linearly toward the surface side, Ino, 5zAllo, 4@A
s at the interface with the barrier layer 13, In+, 5z
AGo, 4@A8 Each layer 1 on the surface side from the barrier layer 13
The composition is such that lattice matching can be achieved with 3.14.15 and 16. This structure is.

This is the basic structure for fabricating an InGaAs/AnAs HEMT.
The As channel layer 14 is made of n-type In. ,,AQo,,y
Electrons are supplied from the As layer 16 and a two-dimensional electron gas is generated. What is important in device production is I no, , Ga
11. As for the crystallinity of the As channel layer 14, the mobility of the two-dimensional electron gas generated in the channel layer and the surface texture are cited as criteria for determining its quality.

The present inventor conducted experiments on crystal growth of the heterostructure shown in Figure 1 by molecular beam epitaxy using an ordinary solid source, and determined the optimal growth conditions and structure to obtain high electron mobility and good surface structure. The most important growth condition is the growth temperature, and the structural parameter is the thickness of the nxGa1-xAs buffer layer 12.

First, the thickness of the InxGa1-xAs buffer layer 12 is fixed at 90Or++++, which is considered to be a sufficiently thick film thickness, and f
i. The surface structure and electron mobility of the heterostructure were evaluated by repeating the growth experiment while changing the long temperature from 375°C to 520°C.

It was found that when the growth temperature was set to 450° C. or lower, the surface structure was a flat mirror surface with slight loss hatches, which caused no problem in device fabrication. However, when the growth temperature was increased to 480° C. or higher, surface irregularities became noticeable and the surface structure deteriorated.

FIG. 2 is a characteristic diagram showing the results of investigating the growth temperature dependence of electron mobility in a prototype heterostructure. As can be seen from the figure, when the growth temperature is 450°C or higher, the electron mobility decreases rapidly, but the samples grown at a growth temperature of around 400°C have a high electron mobility of 9500a#/V,S at room temperature. showed that. This value is comparable to the value in a HEMT structure fabricated on an InP substrate with lattice matching.

Such a good value is due to the adoption of the nxGa1-xAs buffer layer 12 and the optimization of its growth temperature.
It can be concluded that manufacturing can be performed at the following growth temperature.

Next, we considered optimizing the thickness of the InxGa y-zAs barrier layer 12.
The thickness of the +x As buffer layer 12 is an important parameter because it corresponds to the rate of change of InAsIIi in the buffer layer, that is, the rate of change of the lattice constant, and is closely related to the degree of occurrence of crystal defects.

A plurality of samples in which the thickness of the InxGa1-xAs buffer layer 12 was varied from Onm to 1237 nm were prepared at a growth temperature of 400 DEG C., and the electron mobility was evaluated. The results are shown in FIG. As is clear from the figure, I nxG
a1+x A sThe thickness wb of the ballast layer 12 is 530
Above nm, the electron mobility approaches saturation and wb is 35
Below 0 nm, there is a rapid decrease in electron mobility.

However, the electron mobility when the thickness wb is 350 nm is at room temperature (
300”K) and 7500cn?/V, S, 77”K
25000a#/V, S, which is a sufficiently high value, and it is considered that it is sufficient for wb to be 350 nm or more in practice. This corresponds to a rate of change of composition X of 0.15 per 1100n. Therefore, it can be concluded that the rate of change of X should be 1.5 x 10-''/nm or less.

As described above, the heterostructure shown in FIG.
The InAsnAs composition ratio in 2 was set to 1.5X10-'
It has been revealed that good crystal quality can be achieved by setting the thickness to less than /nm.

However, it is generally known that at temperatures below 450° C., the flatness of the heterojunction interface deteriorates, which adversely affects electron mobility. Furthermore, although a high growth temperature is desirable, when growing a layer containing a high concentration of In by molecular beam epitaxy, the In adhesion coefficient is 53.
It is also known that the growth temperature gradually decreases at a growth temperature of 0° C. or higher, causing deterioration of crystal quality and deviation of the composition from the designed value. Therefore, the upper limit of the growth temperature is 53
It is automatically determined as 0℃. As a result of considering how to incorporate the growth temperature, the present inventor found that the decrease in mobility and the deterioration of the surface structure that occur at high growth temperatures mainly occur when forming the InxGa1-xAs buffer layers and 2. A
It was assumed that the layer above the s-buffer 7512 would not deteriorate in mobility or surface morphology even if grown at a higher temperature.

In fact, in the heterostructure shown in Figure 1, non-doped Ga
After growing the As buff layer 11 and the InxGax, xAs buffer layer 12 at 400°C, the growth temperature was increased to 50°C.
The temperature rises to 0°C, I no, 52 A, Ql), 4
@ As barrier layer 13 to n-type In, , , AQ+, ,
When up to 16 1lAs layers were grown, no deterioration of the surface structure or decrease in mobility was observed, and the mobility was 1050 at room temperature.
0aJ /V,S,, 77@ni 49000cj/y,
The highest value of S was obtained. In addition, in this sample, the thickness of the InxGa kneexAs rose film layer 12 was set to 1
It was set as μm. Also, the concentration of two-dimensional electron gas is 1.8
It was 1012/cd.

To summarize the above results, In
In order to form a device active layer made of GaAs or InAlAs with good crystal quality, an InxGa1-xAs buffer is used in which the InAs composition ratio X is linearly increased from O to a value that lattice matches with the device active layer from the substrate side. layer and G
a As to be interposed between the As substrate and the element active layer, and the rate of change in the InAs composition in this InxGa□-2As barrier layer to be 1.5X10-3/n+a or less;
Furthermore, it is important to keep the growth temperature of the InxGaz-yAs buffer layer at 450° C. or lower, which is higher than the formation temperature of the buffer layer for forming the active layer.

A temperature of 450°C to 530°C is preferred. By such a manufacturing method, at least good quality I
It is possible to form an nGaAs/AQGaAs-based HEMT structure on a GaAs substrate.

Although the above-described embodiments of the present invention have been mainly explained with reference to the HEMT structure, it goes without saying that the nxGa1-xAs buffer layer of the present invention and its manufacturing method are also effective when manufacturing optical devices.

In addition, the Peter structure and its manufacturing method according to the present invention are
When the application is limited to EMT, the non-doped In5,5zAffal@As barrier layer 13 in the heterostructure shown in FIG. 1 plays an important role. First, the crystal defects contained in the InxGa1-xAs buffer layer and 2 are removed by In. , 5□GaI, , 7As
The purpose is to prevent it from reaching the inside of the channel layer 14.
This is an InxGa, -xAs buffer layer and 2 and In6
．． 5zAQ6. This is due to the function of the heterojunction interface of the @As barrier layer 13. As a second effect, In...
, Gaa4. Electrons flowing through the As channel layer 14 are
At the drain electrode side of the EMT, it is pushed toward the substrate side, but at this time, In, ..., Af20. □When there is no As barrier layer 13, electrons are
s flows into the buffer layer I2 and is captured by defects existing in this buffer layer, thus having an adverse effect on the characteristics of the HEMT.

I no, s2 AQ6. The @As barrier layer 13 prevents these electrons from flowing into the buffer layer.

In addition, in order to fabricate an actual HEMT, in addition to the Peter structure shown in FIG. 1, undoped In, 52AQ, .

It is sufficient to form an As layer, and then form a source electrode, a drain electrode, and a gate electrode thereon. This is a well-known technique that is often used in InGaAs/InA (IAs-based HEMTs) formed on InP substrates.

As described above, in this embodiment, InGaA of the channel layer
Although the explanation is limited to the case where the InAsff1 composition of s is 0.53, it is not necessarily limited to this composition value,
This can be applied to any InAs composition.

Also, in this example, the HEMT structure was described;
I n11. B AQa, 1m As barrier layer 13
In6.53G86.7AI on top! As channel layer, this I no, 5a Gaa, 4? A metal-insulating film-semiconductor structure (Metal
-Insulator-3amiconductor;
MIS field effect transistor (MISFE)
T) and JFET (J
unction Field-Effect Tra
Needless to say, the present invention can also be applied to manufacturing .

(Effects of the Invention) As explained above, according to the present invention, an active layer of an electric device or an optical device made of InGaAs or InAlAs can be formed on a GaAs substrate while maintaining good crystallinity.
It becomes possible to significantly reduce the manufacturing cost of the element. Furthermore, it is possible to realize a high-performance transistor on a GaAs substrate with characteristics that could not be achieved with conventional GaAs-based electrical elements, and it can be applied to the production of integrated circuits for optical devices and electrical devices.

[Brief explanation of drawings]

FIG. 1 is an enlarged sectional view of the main part of the Peter structure according to the present invention, FIG. 2 is a characteristic diagram showing the relationship between electron mobility and growth temperature in the heterostructure of the present invention, and FIG. FIG. 4, a characteristic diagram showing the relationship between electron mobility, InxGa1-xAs buffer layer, and layer thickness, is an enlarged sectional view of the main part of a conventional heterostructure. 1...GaAs substrate, 2...buffer layer,
3... InGaAs layer, 4... Non-doped InG
aAs layer, 5.7... planar doped Si layer,
6.8...Non-doped InA (iAs layer, 9-
n-type InGaAs layer, 10...semi-insulating GaAs
Substrate, 11...GaAs buffer layer, 12...
non-doped InxGa□-XAs buffer layer,
43... Non-doped In6.5zAQy, 4@AS barrier layer, 14...
In,,5. Gao, vAs channel layer, 15-.
・Non-doped I no, sz A Qa,, A s
Spacer layer, 16-n shape n0.52 Al2O, 46
As layer.

Claims (4)

[Claims] (1) In_xGa_1_-_xAs on a GaAs substrate
In a semiconductor heterostructure in which an active layer containing In_yGa_1_-_yAs is formed via a buffer layer,
The InAs composition ratio x of the In_xGa_1_-_xAs buffer layer ranges from 0 to y between the GaAs substrate side and the active layer.
1. A semiconductor heterostructure characterized in that x changes substantially linearly in the thickness direction, and the rate of change in x is 1.5×10^-^3/nm or less. (2) In_xGa_ on a GaAs substrate, the InAs composition ratio x is changed almost linearly with the thickness from 0 to y, and the rate of change of x is 1.5×10^-^3/nm or less
1_-_xAs buffer layer forming process, and In_xGa_1_-_xAs buffer layer formed on the In_xGa_1_-_xAs buffer layer.
including at least a step of forming an active layer containing Ga_1_-_yAs, and the above-mentioned In_xGa_1_-_x
A method for manufacturing a semiconductor heterostructure, characterized in that the As buffer layer and the active layer are formed by molecular beam epitaxy at a growth temperature of 450° C. or lower. (3) In_xGa where the InAs composition ratio x is changed almost linearly with the thickness from 0 to y on a GaAs substrate, and the rate of change of x is 1.5×10^-^3/nm or less
A step of forming an In_xGa_1_-_xAs buffer layer using a molecular beam epitaxy method at a growth temperature of 450°C or lower, and a step of forming an In_xGa_1_-_xAs buffer layer on the
The active layer containing Ga_1_-_yAs was heated to 53°C from 450°C.
A method for manufacturing a semiconductor heterostructure, comprising at least a step of forming the semiconductor heterostructure by molecular beam epitaxy at a growth temperature of 0°C. (4) Undoped GaAs on a semi-insulating GaAs substrate
A buffer layer, a non-doped In_xGa_1_-_xAs buffer layer in which the InAs composition ratio x is changed almost linearly with the thickness from 0 to y at a rate of change of 1.5 x 10^-^3/nm or less, and In_y.
The thickness that lattice matches with Ga_1_-_yAs is 200 nm.
a non-doped InAlAs barrier layer, a non-doped In_yGa_1_-_yAs channel layer, a non-doped InAlAs spacer layer, and an n-type InAlAs
A semiconductor heterostructure including at least a heterostructure in which S layers are sequentially formed.