JP2530496B2 - Semiconductor heterostructure and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor heterostructure and a method for manufacturing the same.

(Prior Art) A high electron mobility transistor (hereinafter referred to as HEMT) in which the concentration of a high mobility two-dimensional electron gas generated at a heterojunction interface in which an n-type AlGaAs layer is formed on a non-doped GaAs layer is controlled by a gate electrode. ) Has been devised. This HEMT is
Since it is promising as a high-speed switching element and a microwave element, researches on materials and structures for further improving the characteristics are actively conducted.

In terms of materials, a heterostructure composed of In _0.53 Ga _0.47 As lattice-matched to InP and n-type In _0.52 Al _0.48 As is used for the InP substrate instead of the GaAs substrate, and each has a higher electron structure than the GaAs / AlGaAs HEMT Since it exhibits mobility, electron saturation velocity, and two-dimensional electron gas concentration, it is attracting attention as a device that can realize HEMTs with higher performance than AlGaAs / GaAs systems.

However, the InP substrate is not only more expensive than the GaAs substrate at present, but its quality is inferior to that of the GaAs substrate, and unnecessary impurities are introduced into the crystal layer formed on the InP substrate. However, there is a problem that it is easier to crack than a GaAs substrate. As a countermeasure against this problem, use InGaAs or InAlAs with a GaAs substrate or Si substrate with excellent crystal quality.
There is a demand for a new technology that can grow the crystals. Such a technique is also important in manufacturing integrated circuits for light receiving / light emitting devices and high-speed electronic devices.

A problem in forming InGaAs or InAlAs on, for example, a GaAs substrate is a difference in lattice constant between InGaAs and InAlAs and GaAs. When forming an In _0.53 Ga _0.47 As layer on GaAs,
In order to suppress crystal defects caused by the difference in lattice constant, it is necessary to form a thin layer with a thickness of several nm, which is not practical. Therefore, a method of reducing the defect density of the device active layer is considered as an unavoidable occurrence of crystal defects.

According to the conventional method based on this idea, first, a superlattice made of a thin layer of InGaAs and InAlAs is grown as a buffer layer on a GaAs substrate, and then an active layer of the device is formed.

A conventional semiconductor heterostructure of this type will be described with reference to FIG. This figure is an enlarged cross-sectional view of the main part. The semiconductor heterostructure has a 1.8 μm thick superlattice structure in which a 3 nm thick InAlAs film and a 1 nm thick InGaAs film are alternately laminated on a GaAs substrate 1. Buffer layer 2 is formed, and HEM is further formed on it
The InGaAs layer 3 having a thickness of 30 nm to be a T channel layer is formed. Thickness formed by stacking on it 2.
The 5 nm non-doped InGaAs layer 4, the planar doped Si layer 5, the 25 nm thick non-doped InAlAs layer 6, the planar doped Si layer 7, the 1 nm thick non-doped InAlAs layer 8 and the 15 nm thick n-type InGaAs layer 9 are Electrons are supplied to the InGaAs layer 3 and ohmic contact is formed. (YK
Chen, GWWang, WJSchaff, PJTasker, K.Kavanagh and
LFEastman; IEDM Technical Didgest, p.433,1987).

(Problems to be Solved by the Invention) However, despite the formation of the buffer layer 2 of the superlattice as described above, defects are generated in the InGaAs layer 3 of the active layer although the defects are slight. Further, the present inventors have experimented, when such a defect is found, the electron mobility is 5500cm ² / VS to 6000 cm ² / VS approximately at room temperature, when subjected to lattice matching with the InP substrate Of 10 ⁴ cm ² / V.
There was a problem that it was significantly lower than the value above S.

The present invention solves the above problems and provides a semiconductor heterostructure having excellent crystal quality while growing InGaAs and InAlAs having greatly different lattice constants, and a method for manufacturing the same.

(Means for Solving the Problems) In order to solve the above problems, the present invention sets the InAs composition ratio x of the In _x Ga _1-x As layer used for the buffer layer to 0 on the substrate side,
A method is used in which the InAs composition is gradually increased toward the active layer and lattice-matched with the active layer on the active layer side, and the change rate of the InAs composition x is 1.5 × 10 ⁻³ / nm or less. .

Further, when the buffer layer is grown by the molecular beam epitaxy method, the growth temperature is set to 450 ° C. or lower.

Furthermore, when the active layer is formed on the buffer layer formed at a temperature of 450 ° C. or lower by the molecular beam epitaxy method, the growth temperature is raised from 450 ° C. or higher to 530 ° C. or lower.

In forming the active layer of InGaAs in In _x Ga _1-x As of the buffer layer, InGaAs active layer and the lattice constant between the InGaAs active layer and In _x Ga _1-x As buffer layer of the same InAlAs A barrier layer is interposed.

(Operation) In with the InAs composition gradually increased from the substrate side to the active layer side
_{The x} Ga _1-x As buffer layer significantly improves the crystallinity of the active layer formed on the buffer layer. It is considered that this is because the generation of crystal defects is suppressed by this buffer layer and almost no defects reach the active layer. However, if the rate of change of the InAs composition x of the In _x Ga _1-x As buffer layer is made too large, the quality of the crystal deteriorates, and the rate of change of 0.15 or less per 100 nm of the buffer layer should be realized. It became clear. That is, the crystal quality can be kept good by setting the change rate of the InAs composition to be 1.5 × 10 ⁻³ / nm or less.

In addition, the above In _x Ga _1-x As by the molecular beam epitaxy method is used.
Growth temperature has a great influence on the crystallinity and surface texture of the active layer formed on the buffer layer. As a result of experimenting by changing the growth temperature of the buffer layer from 375 ° C to 520 ° C,
It was revealed that the temperature at which good crystallinity and surface texture were obtained was approximately 450 ° C or lower.

In addition, the growth temperature of the active layer formed on the buffer layer was good even when the growth temperature of the buffer layer was 450.
It has been clarified from experiments that the crystallinity of the active layer can be further improved when the temperature is raised to 530 ° C. or higher above ℃.

Furthermore, when forming an active layer of InGaAs on the above In _x Ga _1-x As buffer layer, InAl that lattice-matches with InGaAs of the active layer.
By inserting the As barrier layer, crystal defects can be prevented from propagating from the buffer layer to the active layer, and the crystallinity of the active layer can be further improved. Further, in the case of HEMT, the channel layer corresponds to the InGaAs active layer, but the insertion of the InAlAs barrier layer causes many defects in the two-dimensional electron gas accumulated in the InGaAs channel layer.
Since it is prevented from flowing through the In _x Ga _1-x As layer, the device characteristics are improved.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an enlarged cross-sectional view of an essential part of a semiconductor heterostructure according to the present invention. A 200 nm-thick non-doped GaAs buffer layer 11 on a semi-insulating GaAs substrate 10 and a non-doped In _x Ga _{1- x} As buffer layer 12 is overlaid and then 200 nm thick undoped In _0.52 Al _0.48 As barrier layer 1
3, 100 nm thick In _0.53 Ga _0.47 As channel layer 14, thickness 3 n
A non-doped In _0.52 Al _0.48 As spacer layer 15 of m and an n-type In _0.52 Al _0.48 As layer 16 having a thickness of 30 nm and having Si added at a high concentration are sequentially formed. In addition, n-type In _0.52 Al _0.48 As layer
The Si doping amount of 16 was set to about 2 × 10 ¹⁸ / cm ³ . Also, In _x Ga
The InAs composition x of the _1-x As buffer layer 12 is 0 on the GaAs substrate 10 side.
And increase linearly toward the surface side, and In _0.52 Al
_0.48 As 0.53 at the interface with the barrier layer 13, In _0.52 Al _0.48 As
The composition is such that lattice matching can be achieved with each of the layers 13, 14, 15 and 16 on the surface side of the barrier layer 13. This structure is InGaAs / I
The basic structure for fabricating nAlAs HEMTs, In _0.53 G
The a _0.47 As channel layer 14 is supplied with electrons from the n-type In _0.52 Al _0.48 As layer 16 to generate a two-dimensional electron gas. What is important in device fabrication is the crystallinity of the In _0.53 Ga _0.47 As channel layer 14, and the mobility and surface texture of the two-dimensional electron gas generated in the channel layer are the criteria for judging the quality.

The present inventor has conducted an experiment on the crystal structure of the heterostructure shown in FIG. 1 by the molecular beam epitaxy method using an ordinary solid source, and has optimized the growth conditions and the structure for obtaining a high electron mobility and a good surface texture. The most important item of growth condition is the growth temperature, and the structural parameter is
It was considered to be the thickness of the In _x Ga _1-x As buffer layer 12.

First, the thickness of the In _x Ga _1-x As buffer layer 12 was fixed to 900 nm, which is considered to be a sufficiently large thickness, and the growth temperature was changed from 375 ° C to 520 ° C.
The growth experiment was repeated up to ℃ and the surface texture and electron mobility of the fabricated heterostructures were evaluated.

As for the surface texture, it was found that when the growth temperature was 450 ° C or less, a slight crosshatch was observed, but there was no problem in device fabrication with a flat mirror surface. However, when the growth temperature was 480 ° C or higher, surface irregularities were conspicuous and the surface texture deteriorated.

FIG. 2 is a characteristic diagram showing the results of investigating the growth temperature dependence of electron mobility in a prototype heterostructure. As can be seen from the figure, the electron mobility sharply decreases at the growth temperature of 450 ° C or higher, but the electron mobility of the sample at the growth temperature of about 400 ° C showed a high value of 9500 cm ² / VS at room temperature. This value is the value of HEMT fabricated by lattice matching on InP substrate.
It is comparable to the value in the structure.

Such a good value is a result of the adoption of the In _x Ga _1-x As buffer layer 12 and the optimization of its growth temperature, and the growth at a temperature of 450 ° C. or lower at which good surface texture and electron mobility can be obtained. It can be concluded that it is good to manufacture at temperature.

Next, it was considered to optimize the thickness of the In _x Ga _1-x As buffer layer 12. The thickness of the In _x Ga _1-x As buffer layer 12 is
This is an important parameter because it corresponds to the rate of change of the InAs composition in the buffer layer, that is, the rate of change of the lattice constant, and is closely related to the degree of occurrence of crystal defects.

A plurality of samples in which the thickness of the In _x Ga _1-x As buffer layer 12 was changed from 0 nm to 1237 nm was prepared at a growth temperature of 400 ° C,
The results of evaluation of electron mobility are shown in FIG. As is clear from the figure, the thickness Wb of the In _x Ga _1-x As buffer layer 12
Above 530 nm, the electron mobility approaches saturation and Wb is 350.
A sharp decrease in electron mobility occurs below nm. However, the electron mobility with a thickness Wb of 350 nm is at room temperature (300 ° K).
It is a sufficiently high value of 7500 cm ² / VS and 25000 cm ² / VS at 77 ° K, and it is considered that Wb should be 350 nm or more for practical use. The thickness Wb of 350 nm corresponds to the change rate of the InAs composition x in the In _x Ga _1-x As buffer layer 12 being 0.15 per 100 nm. Therefore, it can be concluded that the rate of change of x should be 1.5 × 10 ⁻³ / nm or less.

As described above, if the heterostructure shown in FIG. 1 is formed at a growth temperature of 450 ° C. or less and the rate of change of InAs composition x in the In _x Ga _1-x As buffer layer 12 is 1.5 × 10 ^-3 / nm or less. It was clarified that good crystal quality can be realized.

However, it is generally known that at a temperature of 450 ° C. or lower, the flatness of the heterojunction interface deteriorates and the electron mobility is adversely affected. A high growth temperature is desirable, but when performing crystal growth of a layer containing high concentration of In by the molecular beam epitaxy method, the sticking coefficient of In gradually decreases at the growth temperature of 530 ° C or higher, and the quality of the crystal grows. It is also known to cause deterioration and deviation of the composition from the designed value. Therefore, the upper limit of the growth temperature is automatically set to approximately 530 ° C. The present inventors have results of examining the intake how the growth temperature, the mobility of the drop and the surface tissues caused by high growth temperatures degradation occurs when mainly forming the In _x Ga _1-x As buffer layer 12, an In _x It was considered that the layers above the Ga _1-x As buffer layer 12 did not deteriorate in mobility or surface morphology even when grown at a higher temperature.

In fact, in the heterostructure of FIG.
After the buffer layer 11 and the In _x Ga _1-x As buffer layer 12 were grown at 400 ° C, the growth temperature was raised to 500 ° C and In _0.52 Al
_{When the 0.48} As barrier layer 13 to the n-type In _0.52 Al _0.48 As layer 16 were grown, no deterioration of the surface texture or decrease in mobility was observed, and the mobility was 10500 cm ² / VS at 77 ° K at room temperature. In 49000
The highest value of cm ² / VS was obtained. In the sample at this time, the thickness of the In _x Ga _1-x As buffer layer 12 was 1 μm.
The concentration of the two-dimensional electron gas was 1.8 × 10 ¹² / cm ² .

Summarizing the above results, InGaAs and InAl on a GaAs substrate
To form the device active layer having a good crystal quality of As it was linearly increased from the substrate side InAs composition ratio x from 0 to a value that is lattice-matched device active layer an In _x Ga _1-x As
By interposing a buffer layer between the GaAs substrate and the device active layer, the rate of change of InAs composition in this In _x Ga _1-x As buffer layer can be measured.
It is important that the growth temperature of the In _x Ga _1-x As buffer layer is 450 ° C or less, and that the formation temperature of the buffer layer is 1.5 x 10 ^-3 / nm or less. A higher temperature, 450 ° C to 530 ° C, is desirable. With such a manufacturing method, at least good quality InGa
It is possible to form an As / AlGaAs HEMT structure on a GaAs substrate.

In the embodiments of the present invention described above, the HEMT structure was mainly described, but the present invention can be applied to the case of manufacturing an optical element.
It goes without saying that the In _x Ga _1-x As buffer layer and its manufacturing method are effective.

The heterostructure according to the present invention and the manufacturing method thereof are
When the application is limited to HEMT, the undoped In _0.52 Al _0.48 As barrier layer 13 in the heterostructure of FIG. 1 plays an important role. The first is to prevent crystal defects contained in the In _x Ga _1-x As buffer layer 12 from reaching the In _0.53 Ga _0.47 As channel layer 14, which is the In _x Ga _1-x As buffer layer. Layer 12
And In _0.52 Al _0.48 As barrier layer 13 at the heterojunction interface. As a second effect, the electrons flowing in the In _0.53 Ga _0.47 As channel layer 14 are pushed to the substrate side by the HEMT drain electrode side. At this time, if the In _0.52 Al _0.48 As barrier layer 13 is not present, the electrons are In _x Ga _1-x As buffer layer 12
It flows into the buffer layer and is trapped by defects existing in this buffer layer, which adversely affects the HEMT characteristics. In
_{The 0.52} Al _0.48 As barrier layer 13 prevents this electron from flowing into the buffer layer.

In the actual fabrication of HEMT, an undoped In _0.52 Al _0.48 As layer was further formed on the heterostructure shown in FIG.
A source electrode, a drain electrode, and a gate electrode may be formed on this, which is the InGaAs / In formed on the InP substrate.
This is a well-known technique often used in AlAs HEMTs.

As described above, in the present embodiment, the case where the InAs composition of InGaAs of the channel layer is 0.53 has been described, but the present invention is not limited to this composition value, and it can be applied to any InAs composition.

Although the HEMT structure has been described in the present embodiment, In
_0.52 Al _0.48 As barrier layer 13 to form the In _0.53 Ga _0.47 As channel layer on the metal by using the In _0.53 Ga _0.47 As channel layer - insulating film - semiconductor structure (Metal-Insulator-Semico
n field effect transistor (MISFET) or p
-JFET (Junction Field-Effe) using -n junction gate
It goes without saying that it is also applicable to manufacture a ct Transistor).

(Effect of the Invention) As described above, according to the present invention,
Since the active layers of electric elements and optical elements made of InGaAs and InAlAs can be formed while maintaining good crystallinity, the manufacturing cost of the elements can be significantly reduced. Further, it is possible to realize a high-performance transistor having characteristics that cannot be achieved by a conventional GaAs-based electric element on a GaAs substrate, and it can be applied to manufacture an integrated circuit of an optical element and an electric element.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of an essential part of a heterostructure according to the present invention, FIG. 2 is a characteristic diagram showing the relationship between electron mobility and growth temperature in the heterostructure of the present invention, and FIG. 3 is a heterostructure of the present invention. FIG. 4 is a characteristic diagram showing the relationship between the electron mobility and the layer thickness of the In _x Ga _1-x As buffer layer, and FIG. 4 is an enlarged cross-sectional view of a main part of a conventional hetero structure. 1 ... GaAs substrate, 2 ... buffer layer, 3 ... InGaAs layer,
4 ... Non-doped InGaAs layer, 5,7 ... Planar-doped Si
Layers, 6,8 ... Non-doped InAlAs layers, 9 ... n-type InGaAs
Layer, 10 ... Semi-insulating GaAs substrate, 11 ... GaAs buffer layer,
12 …… Non-doped In _x Ga _1-x As buffer layer, 13 …… Non-doped In _0.52 Al _0.48 As barrier layer, 14 …… In _0.53 Ga _0.47 As channel layer, 15 …… Non-doped In _0.52 Al _0.48 As spacer layer, 16 ... n-type In _0.52 Al _0.48 As layer.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/808 29/812 (56) Reference JP-A-1-158719 (JP, A) JP-A 61- 268069 (JP, A) JP-A-2-271638 (JP, A)

Claims (2)

(57) [Claims] 1. A buffer of In _x Ga _1-x As crystals on a GaAs substrate in which the InAs composition ratio x is changed substantially linearly from 0 to y with the thickness at a rate of change of 1.5 × 10 ^-3 / nm or less. layer and, in _y Ga _1-y as and the InAlAs barrier layer substantially lattice-matched, in _y Ga _1-y as channel layer and the n-type InAlAs layer and the semiconductor heterostructure comprising at least a heterostructure formed by sequentially formed. 2. An InAs composition ratio x on a GaAs substrate is changed substantially linearly with thickness from 0 to y, and a rate of change of x is 1.
A step of forming an In _x Ga _1-x As buffer layer at 5 × 10 ^-3 / nm or less, and forming an active layer containing In _y Ga _1-y As on this In _x Ga _1-x As buffer layer And an In _x Ga _1-x As buffer layer and the active layer are formed at a growth temperature of 450 ° C or lower by a molecular beam epitaxy method. Manufacturing method.