JPH02271638A - Semiconductor element - Google Patents

Abstract

PURPOSE:To increase carrier concentration of a two-dimensional electron gas and improve mobility and saturation rate of the carrier by providing a layer where a mixed crystal ratio y of In changes continuously from 0 to y between a GaAs layer and an InyGa1-yAs layer. CONSTITUTION:A layer 4 called a graded layer where the mixed crystal ratio of In changes from 0 to y continuously from a GaAs layer 3 toward the InyGa1-yAs layer 5 is provided between the undoped GaAs layer 3 and the undoped InyGa1-yAs layer 5 to relax distortion due to difference in lattice constant between GaAs and InGaAs. As a result, since the undoped InyGa1-yAs layer 5 is relaxed due to presence of the graded layer 4, the thickness may be increased by that amount and the mixed crystal ratio y can be increased. Thus, the carrier concentration becomes larger and the mobility and saturation rate of carrier can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to InGaAs/GaAs
The present invention relates to a technique that is effective when applied to semiconductor devices having a heterojunction, particularly high electron mobility transistors having a two-dimensional electron gas.

[Conventional technology]

One of the semiconductor devices that utilizes heterojunctions is the two-dimensional electron field effect transistor (Two-dimensional field effect transistor).
nal Electron Gas FET: 2
High electron mobility transistor (DEG-FET)
(transistor) is known. In addition, compared to GaAs, the electron mobility (mobility)
High electron mobility transistors made of InGaAs have also been developed because of their high saturation speed. For example, the Japanese Journal of Applied Physics discusses lnGaAs/GaAs heterostructures.
pplied Physics) Volume 26, No. 4, April, 1987, P539-P542.

This document discusses the critical thickness at which crystal distortion occurs due to lattice mismatch between InGaAsJli and GaAs1l. This document describes an InGaAs layer and a GaAs layer.
It is stated that distortion due to mismatching of the lattice constants of the As layer can be avoided by making the InGaAs layer thinner.

[Problem to be solved by the invention]

As stated in the above literature, the lattice constant is 5.6.
GaAs with 5 people and A with a lattice constant of 5° and 66 people.
When flGaAs is in a junction state, InGaAs
When the film thickness of 1ii exceeds a specific thickness, lattice distortion occurs due to lattice constant mismatch. This strain deteriorates crystallinity and reduces carrier mobility and saturation speed. Also,
From the relationship of the band gap in two-dimensional electron gas, I
The mixed crystal ratio (molar ratio) y of In in nGaAsJil is 0.15 to 0.2. Therefore, in the past, I
For 2DEG-FET using nGaAs layer, 2
The thickness of InGaAsJi, where the dimensional electron gas is formed, is about 200 degrees thick and discolored.

In verification by the present inventor, when the thickness of the InGaAs layer in which two-dimensional electron gas is formed is about 200 mm thick, no dependence is observed when the film thickness is 500 mm thick. It has been found that the sheet concentration (carrier concentration) n of the dimensional electron gas decreases rapidly.

Drain current 1. is expressed by the following formula.

Is = q n, W, V, ... (1) Here,
q is the electric charge, W is the gate width, and ■ is the saturation speed determined by the material.

Therefore, in order to suppress the decrease in n,
It is necessary to increase the thickness of the aAs layer by about 500 layers. However, if the InGaAs layer is simply made thicker by about 500 layers, lattice distortion will occur as described above, and the carrier mobility and saturation speed will be slowed down, resulting in a high-speed Gender is no longer embodied.

In view of the above, the present inventor attempted to make the InGaAs layer in which the two-dimensional electron gas is formed into a thick layer with no lattice distortion and a large mixed crystal ratio y, and accomplished the present invention.

The purpose of the present invention is to form a thick InGaAs layer with no lattice strain by using GaAs.
The purpose is to form it on As1i.

Another object of the present invention is to provide a two-dimensional electronic field effect transistor that operates at high speed.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the two-dimensional electron field effect transistor of the present invention includes an undoped GaAs layer and an undoped I n O-1, Ga 141-rAs layer on the main surface of a semi-insulating GaAs substrate.
layer, undoped InyGa+-y As layer, n-type GaA
sJII has a structure in which a pair of selectively provided n-type GaAs layers are sequentially stacked, and a two-dimensional electron gas is formed in the surface layer of the undoped InyGa+-y AsN. There is. Further, the thickness of the and-11nGaAs layer is discolored by about 500 mm. Further, a gate electrode is provided on the n-type GaAs layer, and a source electrode is provided on one side of the n-type GaAs layer, and a drain electrode is provided on the other side.

[Operation] According to the above means, the two-dimensional electron field effect transistor of the present invention has an undoped GaAs layer and an undoped I
In order to alleviate the strain caused by the difference in lattice constant between GaAs and InGaAs, the In mixed crystal ratio is changed from the GaAs layer to the InyGa+− layer.
y Ino-my C, also called a graded layer that changes continuously from zero to y as it moves toward AsJI;
A +41-F A s layer is provided. As a result, due to the presence of the grepunt layer, the undoped I
Since the lattice strain of the nyGa+-As layer is relaxed, its thickness can be increased by 500 nm. Also, the mixed crystal ratio y is 0
．． It can be made larger than 3.

Therefore, a two-dimensional electron gas is formed in the undoped I
Since the thickness of the n, Gap-yAs layer can be increased and the mixed crystal ratio can be increased, the carrier concentration can be increased, thereby improving carrier mobility and saturation speed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing a semiconductor element in which a 2DEG-FET according to an embodiment of the present invention is formed, FIG. 2 is a schematic plan view similarly showing an electrode pattern, and FIGS. 2DEC; - Cross-sectional views of each manufacturing process of FET, FIG. 3 is a cross-sectional view of a wafer with a multilayer growth layer formed on the main surface, and FIG. 4 is a cross-sectional view of a wafer with a source electrode and a drain electrode formed. FIG. 5 is a cross-sectional view of a wafer on which a gate electrode is formed, FIG. 6 is a schematic cross-sectional view of a semiconductor device incorporating a semiconductor element according to the present invention, and FIG. 7 is a partially cutaway view. FIG.

The 2DEC-FET of this embodiment has a structure as shown in FIG. That is, this 2DEG-FE
T is a semi-insulating GaAs substrate layer with a thickness of 160//m;
It is composed of multilayer growth yM2 etc. formed on this main surface by the MBE (molecular beam epitaxy) method.

The multilayer growth layer 2 is made of undoped Ga with a thickness of 5000 nm.
As layer 3. Undoped I n(+-ey
G a 141-IT A 3 layers (graded layer)
4. 5. Undoped InGaAs layer (undoped In, Gap-y As layer) with a thickness of 500 nm. n-type AIC with a thickness of 400, a pair of n-type aAsAs layers with a thickness of 1600
It consists of a 10-shaped GaAs layer 7. As a result, the n
A two-dimensional electron gas (two-dimensional electron gas layer) 8 is generated in the surface layer of the AjLGaAs layer 6, as shown by the dotted line. The In mixed crystal ratio of the undoped InGaAs layer 5 (
molar ratio) y is 0.15 to 1.0.

Then, the undoped GaAs layer 3 and the undoped In
The graded layer 4 provided between the GaAs layer 5 is
This is a layer in which the In mixed crystal ratio continuously changes from zero to y. That is, undoped I no-+y Ga
141-, the mixed crystal ratio is zero in the part of the As layer 4 that contacts the undoped GaAs layer 3, and the undoped InG
The mixed crystal ratio in the portion in contact with the aAs layer 5 is y. Therefore, the graded layer 4 will be referred to as an undoped In6-*y Ga 141-7As layer 4, although this has already been indicated. Note that the change in the mixed crystal ratio in the thickness direction occurs when forming the graded layer 4 by the MBE method.
By controlling the supply amount of In to increase over time, it can be formed with good reproducibility. Since the mixed crystal ratio of In in this graded layer 4 changes continuously, the difference in lattice constant between each layer is extremely small, so no strain occurs in the crystal. Even if the undoped InGaAsN3 is formed as thick as 500 μm and as large as the mixed crystal ratio y-Q of 5, no distortion occurs. Furthermore, the AA of the n-type A1GaAs layer 6 is
The mixed crystal ratio is 0.3.

On the other hand, on the n-type AjLGaAs layer 6, a gate electrode 9 of 3,000 thickness made of A-layer is provided, and an n◆decade-aAs layer extending on both sides of the gate electrode 9 is provided.
On layer 7 is AuGe/Ni.

A source electrode 10 and a drain electrode 11 each having a thickness of 1500 mm and made of /Au are provided separately.

Further, CVD is selectively applied to the main surface of the GaAs substrate l.
An insulating film 12 and a passivation film 13 made of SiO are provided.

The electrode pattern in such a semiconductor element 15 is as shown in FIG. This semiconductor element 15
As shown in the figure, it has a single gate structure in which one gate electrode 9 is provided between a source electrode IO and one layer of drain electrodes. Each of these electrodes is drawn out to a predetermined location on the semiconductor element 15, and a portion of each electrode is provided with a source wire bonding pad 16. Wire bonding pad for drain 17. A gate wire bonding band 18 is formed. Two source wire bonding pads 16 are provided. Wires 19 are connected to these wire bonding pads 16, 17, and 18 during semiconductor device manufacturing. The wire 1
9 is the source wire bonding pad 1 at the 21M location.
Two wires are connected to each of 6.

Next, a semiconductor element 15 (20EG-
The manufacturing method of FET) will be explained.

In manufacturing the 20EG-FET, first, as shown in FIG. 3, a compound semiconductor thin plate (wafer) 20 is prepared. This wafer 20 is a semi-insulating GaAs substrate 1
is used as the base material. Further, this wafer 20 has already been provided with epitaxial growth layers successively formed on the GaAs-based itO main surface by the MBE method, and a multilayer growth layer 2 is provided. Further, the thickness of the GaAs substrate I is 4
It is approximately 00 μm.

In addition, in the above explanation, a thin plate-shaped GaAs1Fi
Although 1 is referred to as a wafer, not only this GaAs substrate 1 itself but also each layer formed on the surface of this GaAs substrate 1 will be hereinafter referred to as a thin plate before being cut into semiconductor elements 15. will be referred to as a wafer hereinafter.

The multilayer growth N2 provided on the main surface of the GaAs-based Fi1, that is, the (100) crystal plane, is an undoped Ga As Jii3 with a thickness of 5000 people and an undoped I n 114y Ga I-11 with a thickness of 500 people. -y
AS layer (graded layer)4. An undoped InGaAs layer with a thickness of 500 nm (undoped InGa+-y
Ask) 5, 400mm thick n-type AJLGaAs layer 6
．． It consists of a pair of n◆-type GaAs layers 7 with a thickness of 1600 nm. As a result, the n-type A u G a A s
Two-dimensional electron gas (two-dimensional electron gas 11) 8 is generated in the surface layer of li 6, as shown by the dotted line. The In mixed crystal ratio (molar ratio) of the undoped InGaAsJi5 is 0.15 to 1.0. The graded layer 4 provided between the undoped GaAs layer 3 and the undoped InGaAs layer 5 is a layer in which the In mixed crystal ratio continuously changes from zero to y. That is, undoped T nQ4yGal-*+-y AsJi
In the part of F4 in contact with the undoped GaAs layer 3, the mixed crystal ratio is zero, and the undoped I n Ga As l
The mixed crystal ratio in the part that contacts 1I5 is y. Note that the change in the mixed crystal ratio in the thickness direction can be formed with good reproducibility by increasing and controlling the amount of In supplied over time when forming the graded layer 4 by the MBE method. Since the mixed crystal ratio of In in this graded N4 changes continuously, the difference in lattice constant in each layer is extremely small, so no distortion occurs in the crystal. Therefore, in this graded N4, Undoped InGaAs layer 5 formed in
This means that no distortion occurs even if the thickness is 500. Further, the /l mixed crystal ratio of the n-type AlGaAs layer 6 is 0.3.

In such a wafer 20, as shown in FIG.
An insulating film 12 made of D S S O is provided, and an A u G e
A source bridge 10 and a drain electrode 11 having a thickness of 3000 and made of /Ni/Au are connected to the n+ type G
It is formed on the aAs layer 7.

Next, as shown in FIG. 5, the central portion of the insulating film 12 provided on the main surface of the wafer 20 is removed by a commonly used etching technique, and the remaining insulating film 1
2 and n3 using a photoresist film (not shown) as a mask.
The exposed parts of the G a As layer 7 are etched away. A gate bridge 9 having a thickness of 3,000 mm and having a thickness of /l is then formed on the exposed n-type GaAs layer 6 by a commonly used lift-off method (recessed structure). after that,
A banishment film (not shown in the figure) is provided on the wafer 20 in a desired pattern, and the GaAs substrate 1
The lower surface of is polished to the desired thickness. Wafer 20 is approximately 1
After being made to a thickness of about 60 μm, it is divided vertically and horizontally, and the first
A large number of 2DEC-FETs as shown in the figure are manufactured.

The semiconductor device 15 manufactured by such a method is
It is packaged into a semiconductor device as shown in FIGS. 6 and 7.

As shown in FIG. 7, the semiconductor device 1 includes a package 25 made of ceramic having an octagonal column shape, and this package 2.
5, each of which has one end attached to the lower surface thereof. The lead 2G is the package 2
Located on the XY plane with the origin at the center of 5,
It extends in a cross shape along the axial direction. The thick leads extending in the ±Y force direction become source leads 27, and the leads extending in the +X direction become drain leads 28.
The lead extending in the -X direction is the gate lead 29.
It becomes.

As shown in FIG. 6, the package 25 includes a base 30,
The base 30 is composed of three layers of caps that cover the main surface, that is, the top surface. The base 30 includes a base body 32 which is a hexagonal plate made of ceramic, and this base body 3.
The outer periphery of the ceramic frame 33 is provided at the periphery of the main surface of 2 and has an octagonal frame shape. The cap 31 is airtightly fixed to the upper surface of the frame 33 via a bonding material 34. In the base body 32, a conductor N35 is partially provided extending from the main surface of the base body 32 to its peripheral surface and back surface.

These conductor layers 35 include source conductors N36. Drain conductor layer 37. This serves as a gate conductor layer 38. The base 30 is formed by a laminated printing method or the like, and is integrally formed by firing.

The source lead 27, the drain lead 28, and the gate lead 29 are connected to a source conductor layer 36 extending on the lower surface of the base 30. Drain conductor layer 37. They are connected to each other via a bonding material 39 corresponding to the gate conductor layer 38 . Note that each lead 3 is provided with a plating film 40 on its surface.

On the other hand, on the main surface of the base body 32, the source conductor layer 36 forms a chip mounting portion 41 of a drum-shaped cane, as shown in FIG. And this chip mounting part 41
The semiconductor element 15 is mounted in the center with a bonding material 42 made of silver paste or the like interposed therebetween. Further, since a drain conductor layer 37 and a gate conductor layer 38 extend on the main surface of the base body 32, these and the electrodes of the semiconductor element 15 are shown in FIGS. 6 and 7. It is electrically connected by a wire 19 so that it can be connected.

According to such an embodiment, the following effects can be obtained.

(1) In the two-dimensional electron field effect transistor of the present invention, a two-dimensional electron gas serving as a channel is formed between an undoped Ino-*yGa+ AsJi formed in the surface layer and an undoped GaAs layer on the substrate side. −
Since the As layer is provided, it is possible to form an undoped InyGa or □As layer without lattice distortion.

(2) According to (1) above, the two-dimensional electron field effect transistor of the present invention has the undoped I n 04 yGa
By the action of I-1-yAsJi, undoped Iny
Since no lattice strain occurs in the Ga+□As layer, the thickness of the undoped InyGa+-y As layer can be increased by 500 mm, which increases the sheet concentration of the two-dimensional electron gas and reduces carrier mobility and saturation velocity. (3) According to (2) above, the two-dimensional electron field effect transistor of the present invention has the effect of becoming an original high electron mobility transistor by improving carrier mobility. It will be done.

(4) According to (2) above, the two-dimensional electron field effect transistor of the present invention improves the mobility and saturation speed of the carrier concentration of the two-dimensional electron gas serving as the channel, so that the drain electrode and the mutual conductance (g, The effect is that the noise figure (NF) and power gain (pc) are improved.

(5) The two-dimensional electronic field effect transistor of the present invention has two
Undoped In, C where dimensional electron gas is formed on the surface layer
Undoped I n 04 y Gal-1 between the ya+-y As layer and the undoped GaAs layer on the substrate side
Since the structure forms a 1-yAs layer, undoped InGaAs 1J can be formed without causing lattice strain.
can be manufactured, resulting in better reproducibility and improved yield.

(6) According to the above (1) to (5), according to the present invention, a synergistic effect can be obtained in that a two-dimensional electron field effect transistor with excellent characteristics that operates at high speed can be provided at a low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. No, for example, undoped I
The thickness of the nyGal-yAs layer is not limited to 500, but may be formed thicker or thinner.

In the above description, the invention made by the present inventor is mainly applied to the manufacturing technology of two-dimensional electron field effect transistors, which is the background field of application, but the invention is not limited thereto.

The present invention is applicable to at least semiconductor devices or optical devices using InGaAs.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

According to the present invention, GaAs
There is an I
In6-+ where the mixed crystal ratio y of n changes continuously from zero to y
, Ga, □-yAs layer, the thickness of the In, Gal-yAs layer can be increased while suppressing lattice strain, and the mixed crystal ratio of In can be increased, so two-dimensional electron gas The carrier concentration can be increased, and the carrier mobility and saturation speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor element in which a 2DEC-FET according to an embodiment of the present invention is formed, FIG. 2 is a schematic plan view similarly showing an electrode pattern, and FIG. 4 is a cross-sectional view showing a wafer used for manufacturing; FIG. 4 is a cross-sectional view of a wafer on which source and drain electrodes are formed; FIG. 5 is a cross-sectional view of a wafer on which gate electrodes are formed; FIG. 7 is a schematic cross-sectional view of a semiconductor device incorporating a semiconductor element according to the present invention, and FIG. 7 is a partially cutaway plan view. l... Semi-insulating GaAs substrate, 2... Multilayer growth layer,
3... Undoped GaAs layer, 4... Undoped I
n0-ay Ga 141-y AS layer (grapunt layer), 5... undoped InGaAs layer,
6-=n-type AuGaAS layer, 7...n◆-type GaAs
layer, 8... two-dimensional electron gas, 9... gate electrode, 1
0... Source electrode, 11... Drain electrode, 12.
...Insulating film, 13... Passivation film, 15...
- Semiconductor element, 16... wire bonding pad for source, 17... wire bonding pad for drain, 18... wire bonding pad for gate, 1
9... wire, 20... wafer, 25... package, 26... lead, 27 source lead, 28...
...Drain lead, 29...Gately)', 30
... Base, 31 ... Cap, 32 ... Base body, 33 ... Frame, 34 ... Bonding material, 35 ...
Conductor layer, 36... Conductor layer for source, 37... Conductor layer for drain, 38... Conductor layer for gate, 39... Bonding material, 40... Plating film, 41... Chip mounting Department,
42...Joining material.

Claims (1)

[Claims] 1. GaAs layer and In_y bonded to this GaAs layer
A semiconductor element having a Ga_1_-_yAs layer, and between the GaAs layer and the In_yGa_1_-_yAs layer, an In_0_→_yGa_1_→_1_-_yAs layer in which the In mixed crystal ratio y continuously changes from zero to y. A semiconductor device characterized by being provided with. 2. Undoped GaAs layer and this undoped GaAs
Undoped In_yGa_1_-_y provided on the layer
As layer and this undoped In_yGa_1_-_yA
A semiconductor device in which a two-dimensional electron field effect transistor is formed by an n-type AlGaAs layer provided on the s-layer and a two-dimensional electron gas provided in the surface layer of the undoped In, Ga_1_-_yAs layer, The undoped GaAs layer and the undoped In_yGa_1_-_yA
Between the s layer and the undoped In_0_→_yGa_1_→_1_, the In mixed crystal ratio y changes continuously from zero to y.
-_yAs layer is provided, The semiconductor element of Claim 1 characterized by the above-mentioned.