JPS61187363A - Optical integrated circuit device - Google Patents

Abstract

PURPOSE:To settle the crystal growth by once and to improve productivity and yield, by a method wherein a optical semiconductor element which is a PIN photo-diode and an electron element which is a J-FET are formed in a multi-layer semiconductor crystal having a hetero junction using this hetero junction. CONSTITUTION:A P<+> type area 22 is formed on a PIN diode forming area on a semi-insulating GaAs substrate 21 by diffusion of Zn and the like, and a P<-> type GaAs layer 23, an N-type Al0.3Ga0.7As layer 24 and an N-type GaAs layer 25 are stacked by laminating on the whole surface containing said P<+> type area 22 by molecular beam epitaxial growth method or the like. Next, mesas are formed to each area of a diode which is light receiving element and a J-FET adjoining to this, and the inter-element separation is performed, and the layer 25 of a diode light receiving part is removed, and an Au/Au/Zn/Au layer 26 which becomes a P-type area of the diode is cladded. After that, patterning is performed by cladding an Au/AuGe layer 27 on the whole surface, and an N-type area is formed on the diode, and a source area 27S and a drain area 27D are formed on the FET respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an 0EIC (optical integrated circuit), and particularly to the structure of an 0EIC including a light receiving element and a field effect transistor (FET).

Since the effects of stray capacitance and the like can be reduced by integrating optical semiconductor elements and electronic elements on the same semiconductor substrate, research on the structure of monolithic 0EICs is becoming more active.

[Conventional technology]

Figure 2 shows the PIN diode and MES-F according to the conventional example.
FIG. 2 is a cross-sectional view of 0EIC including ET.

The photodetector on the left is a PIN (p-type-insulating layer-n-type structure) diode, and the right side is a MES-FET (Metal Se
m1conductor-Field Effect
Transist.

r).

In the figure, semi-insulating gallium arsenide (S4-GaAs)
The region of the substrate l where the PIN diode is to be formed is etched to form a step, and the n is etched over the entire surface of the substrate, covering the step.
” -GaAs layer 2, n--GaAs layer 3, high resistance aluminum gallium arsenide (IIR-A
layer 4 (le, tGao, Js) are epitaxially grown in sequence.

Next, the PIN diode formation region is covered with a corrosion-resistant mask, and the substrate is etched to remove the n''-GaAs layer 2, the n--GaAs layer 3, and the HR region other than the PIN diode formation region.
- When Alo, 5Gao, and 7AS layers 4 are removed, P
A groove 16 for element isolation is formed between the IN diode and the FET.

The FET includes an undoped GaAs layer 25 and an n-GaAs layer 25 in the FET formation region of the substrate 1 exposed by etching.
Layer 6 is epitaxially grown in sequence, 5iJ4 layer 7 is deposited on the portion other than the FET tl region, and then n-Ga
A gate electrode 8 made of AI, a source electrode 9 and a drain electrode 10 made of gold/gold germanium (Au/AuGe) are formed on the As layer 6.

The PIN diode opens at Si:+LL12 of the light receiving part,
HR-Alo, 3Gao, 7AS layer 4 contains zinc (Zn
) to obtain p-wall region 1). A u/Zn/Au layer 12 and a gold/titanium (Au/Tf) layer 13 are formed as p-type side electrodes on the p-wall region 1), and an n''-GaAs layer 2 is formed on the n''-GaAs layer 2.
An Au/AuGe layer 14 is formed as a mold side electrode.

Next, connect the FET and PIN diode! 15, 5
A gate electrode 8 and an Au/Ti layer 13 are formed on the iJ4 layer 7.
Interlayer type 3. This wiring is formed along the valley of the groove 16.

[Problem that the invention seeks to solve]

In the conventional EIC, the layer structure constituting the FET and the PIN diode was formed by separate epitaxial growth, so the number of manufacturing steps was large and the structure was complicated.

[Means for solving problems]

The above problem can be solved by an optical integrated circuit device in which an optical semiconductor element and an electronic element are formed by using the same heterojunction in a multilayer semiconductor crystal having a heterojunction.

the optical semiconductor element is a heterojunction PIN photodiode;
This is particularly effective for OBIC, which consists of the electronic device or a heterojunction field effect transistor.

[Effect]

The PIN diode as a light receiving element has an advantageous structure having a heterojunction in which the uppermost layer is a window layer with a large forbidden band width in which no light is absorbed.

Even when using such a PIN diode, the conventional 0
Although the BIC has a heterojunction within the substrate, it simply uses the structure of an ordinary FET.

In the present invention, an HBMT (high electron mobility transistor) is formed using a heterojunction that is present in an 0EIC. In this way, the light-receiving element and the electronic element can be formed using the same layer structure, so epitaxial growth only needs to be performed once, and therefore manufacturing is easy, the structure is simple, and high-speed response is possible.

〔Example〕

FIG. 1 is a perspective view of a portion of an OBIC including a PIN diode and a HEMT according to the present invention.

As with the conventional example, the left side is a photodetector with a PIN diode,
The right side constitutes the HEMT.

An overview of the process for obtaining the diagram structure is as follows.

(1) Formation of p” type region 5I-Diffusion of Zn or beryllium (B) into the region where the PIN or diode is to be formed on the GaAs substrate 21.
e) is ion-implanted to form a p-type region 22.

(2) Undoped p-
GaAs layer 23. n-A10. mGao, 715
A layer 24 and an n-GaAs layer 25 are sequentially grown.

Carrier concentration (cm-') and thickness (μm) of each layer
is (cm-”) (μm) p-GaAs Ji23 ・3.50n-A10
．． :+Gao,? 8S To layer 2: 2xlO18
0-,06n-GaAs layer 25
: 2xlO" 0.05.

(3) Element Isolation A mesa is formed in each region of the PIN diode and HEMT to perform element isolation.

(4) Ohmic contact formation The n-GaAs layer 25 of the PIN diode light receiving part is removed, and Au/Zn/A is used as the p-type side electrode of the PIN diode.
A u layer 26 is formed.

Next, an Au/AuGe layer 27 is deposited on the substrate surface and patterned to form a 27A1HE layer on the n-type side of the PIN diode.
273.27D is formed on the source and drain of MT, and 2
Au/Ti layer 28A covering 7A, 27S, 27D
, 2BS, and 28D to form each electrode.

f5) Al Schottky gate formation and wiring ^1529
is used to form a wiring 29- connecting the gate electrode 29G, the n-type electrode of the PIN diode, and the gate of the HEMT.

In the HEMT, electrons are supplied to the p''-GaAs layer 23 from the electron supply layer n-AlGaAs layer 24 to form a two-dimensional electron gas (2DEC, )jiJ.

This p-GaAs layer 23 may be thinner, about <0.5 μm, in the case of only HEMT, but in the case of 0BIC, it is made thick enough to absorb light with a wavelength of 0.8 μm in the light receiving section.

In the embodiment, a GaAs-based semiconductor has been described, but the present invention is also applicable to other semiconductors such as indium phosphide (rnP)-based semiconductors.

〔Effect of the invention〕

As explained in detail above, in the 0BIC according to the present invention,
Since the FET and the PIN diode can be formed at the same time by one crystal growth, the process is extremely easy and the structure is simple, improving productivity including yield.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing a part of an 0EIC including a PIN diode and a HEMT according to the present invention, and FIG. 2 is a perspective view of an 0B including a PIN diode and a MES-FET according to a conventional example.
It is a sectional view of an IC. In the figure, 21 is a 5l-GaAs substrate, 22 is a p-type region 23 is a p--GaAs layer, and 24 is an n-A10. :+Gao, Js layer, 25 is n
-GaAs layer, 26 is Au/Zn/AU layer, 27 is Au/AuGe Hl, 28 is Au/Ti layer, 29 is ^1 layer

Claims (3)

[Claims] (1) An optical integrated circuit device in which an optical semiconductor element and an electronic element are formed using the same heterojunction in a multilayer semiconductor crystal having a heterojunction. (2) The optical integrated circuit device according to claim 1, wherein the optical semiconductor element is a heterojunction PIN photodiode. (3) The optical integrated circuit device according to claim 1, wherein the electronic element is a heterojunction field effect transistor.