JPH10242166A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid short-circuiting electrodes of a semiconductor device. SOLUTION: On an ohmic electrode 15 at the drain a laminate of a metal layer and Au plated layer is provided. On an ohmic electrode 14 at the source no such laminate is provided but it is directly covered with an insulation layer 16. Vias 19 are formed through a substrate 11 beneath the electrode 14. A laminate structure 20 of a grounding metal layer and Au plated layer on the back side of the substrate 11 is electrically connected to the electrode 14 at the source to reduce the source inductance. No electrode short-circuit is caused between the source and drain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, it relates to the structure of a field effect transistor.

[0002]

2. Description of the Related Art A Schottky barrier junction gate type field effect transistor (hereinafter, referred to as MESFET), particularly a GaAs MESFET using an n-type gallium arsenide (hereinafter, referred to as GaAs) crystal layer as an operation layer is excellent as a high frequency device. It has characteristics and is commercialized.

As this type of MESFET, for example,
John L., published in 1993. B. Walker
Written by High-Power GaAs FET Am
pliers "p. 126, FIG. There is one disclosed in 2.44.

In such a GaAs MESFET,
In order to obtain excellent characteristics as a high-frequency device, a via hole (through hole) is provided in GaAs below the source electrode,
There is a structure in which the source inductance is reduced by being electrically connected to the metal layer on the back surface of the semiconductor via the metal layer formed in the via hole, and FIG. 2 shows a cross-sectional view thereof.

In FIG. 2, reference numeral 11 denotes a semi-insulating GaAs substrate; 12, an n-type GaAs crystal layer; 13, a gate electrode;
4 is a source side ohmic electrode, 15 is a drain side ohmic electrode, 16 is an insulating film, 17 is a laminated structure of a metal layer and a gold plating layer provided on the source side ohmic electrode, 1
Reference numeral 8 denotes a laminated structure of a metal layer and a gold plating layer provided on the drain-side ohmic electrode. The distance between the laminated structure 17 of the metal layer and the gold plating layer provided on the ohmic electrode 14 on the source side and the laminated structure 18 provided on the ohmic electrode 15 on the drain side is 2 μm.

Reference numeral 19 denotes a via hole provided in the GaAs layer 11, and the inside of the via hole 19 and the semi-insulating G
The laminated structure 20 of the metal layer and the gold plating layer formed on the back surface of the aAs substrate 11 has a structure in which the ohmic electrode 14 on the source side is electrically connected. , The source inductor is small, and the structure has excellent high-frequency characteristics.

[0007]

However, in the GaAs MESFET having the above-described structure, the distance between the source electrode and the drain electrode is small, and the GaAs MESFET is not covered with an insulating film. There was a short circuit between both electrodes.

An object of the present invention is to provide a semiconductor device which improves productivity by eliminating a short circuit between electrodes.

[0009]

According to the present invention, there is provided a semiconductor device comprising: a gate electrode forming a Schottky barrier with a semiconductor crystal layer; a pair of first and second ohmic electrodes; A via hole provided directly below the electrode; a metal laminated structure provided on the second ohmic electrode; and an insulating film provided directly on the first ohmic electrode.

The operation of the present invention will be described. By covering the source-side ohmic electrode with the insulating film, a short circuit between the source electrode and the drain electrode does not occur even if metal dust is on the source ohmic electrode.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a view showing an embodiment of the present invention, and is a cross-sectional view of a GaAs MESFET similar to FIG. 2, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

Referring to FIG. 1, a portion different from FIG. 2 is described. No metal layer and gold plating layer (see 17 in FIG. 2) are provided on the ohmic electrode 14 on the source side. Is directly adhered on the ohmic electrode 14. The other configuration is the same as that of FIG. 2, and the description is omitted.

Also in this embodiment, the GaAs substrate 11 immediately below the ohmic electrode 14 on the source side has a via hole 1
9 are provided. This source-side ohmic electrode 1
4 is connected to the laminated structure 20 of the metal layer and the gold plated layer formed on the back surface of the substrate 11 by the laminated structure of the metal layer and the gold plated layer filled in the via hole 19, Since the distance between the source electrode, the metal layer serving as the ground electrode, and the laminated structure 20 of the gold plating layer is short, the source inductance is small and the high frequency characteristics are excellent as in the conventional example.

Here, referring to FIG. 3, FIG. 3 is a diagram showing an example of a planar structure of a conventional GaAs MESFET. Also in FIG. 3, the same parts as those in FIGS.

In FIG. 3, reference numeral 37 denotes a gate pad;
Denotes a source pad, and 39 denotes a drain pad, and other symbols are the same as those in FIG.

In the conventional example of FIG. 3, no via hole is provided below the source ohmic electrode. In such a structure, a metal layer and a gold plating layer are formed on the source ohmic electrode in order to reduce the source resistance. Is required. However, in the structure in which the via hole is provided below the source ohmic electrode as in the present invention, the ground is a laminated structure of a metal layer and a gold plating layer formed in the via hole 19 and on the back surface of the semi-insulating GaAs substrate 11. Since the process is performed through the substrate 20, a stacked structure of a metal layer and a gold plating layer is not required on the source ohmic electrode.

In the conventional structure, since a laminated structure of a metal layer and a gold plated layer is provided on both the drain ohmic electrode and the source ohmic electrode, the interval between the electrodes is small and the electrodes are not covered with an insulating film. In some cases, metal scraps straddled between the electrodes, and both electrodes were electrically short-circuited.

On the other hand, in the present embodiment, a laminated structure of a metal layer and a gold plated layer is provided on the drain ohmic electrode, but a laminated structure of a metal layer and a gold plated layer is provided on the source ohmic electrode 14. Since both electrodes were covered with the insulating film 16, there was no electrical short-circuit between the two electrodes due to metal chips.

Although this embodiment is a MESFET using a GaAs crystal layer as an operation layer, it is effective for a semiconductor device having a structure in which a via hole is provided below a source electrode in order to reduce source inductance. Yes, for example, A
It goes without saying that the same effect can be obtained even with a heterojunction type field effect transistor using a two-dimensional electron gas layer generated at the interface between the lGaAs crystal layer and the GaAs crystal layer.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a GaAsM according to an embodiment of the present invention.
It is an ESFET sectional pattern. In FIG. 1, reference numeral 11 denotes a semi-insulating GaAs substrate, and reference numeral 12 denotes, for example, a carrier concentration of 2 ×.
10 ¹⁷ cm ^-3 , 1500 angstrom thick n-type G
An aAs crystal layer 13 is a gate electrode and a metal layer (for example, Ti / Pt) forming a Schottky barrier with the n-type GaAs crystal layer.
/ Au).

Reference numeral 14 denotes a source-side ohmic electrode (for example, an alloy of Au, Ge, and Ni); and 15, a drain-side ohmic electrode (for example, an alloy of Au, Ge, and Ni).
Reference numeral 6 denotes an insulating film (for example, an SiO2 film having a thickness of 2000 Å), reference numeral 18 denotes a laminated structure of a metal layer (for example, Ti / Au) provided on the drain-side ohmic electrode and a gold plating layer, and reference numeral 19 denotes a GaAs layer. It was a via hole.

The inside of the via hole 19 and the semi-insulating Ga
A metal layer formed on the back surface of the As substrate 11 (for example, Ti
/ Au), a laminated structure 20 of a gold plating layer and the ohmic electrode 14 on the source side are electrically connected to each other. Since the distance is short, the source inductance is small and the structure has excellent high-frequency characteristics as in the conventional example.

The present embodiment is different from the conventional example in that a laminated structure of a metal layer and a gold plating layer is not provided on the source ohmic electrode.

As described in the embodiment, in the conventional structure, since the laminated structure of the metal layer and the gold plating layer is provided on both the drain ohmic electrode and the source ohmic electrode, the distance between the electrodes is narrow, and In addition, since the metal dust is not covered with the insulating film, the metal dust may straddle between the electrodes, and both the electrodes may be electrically short-circuited.

On the other hand, in the present invention, a laminated structure of a metal layer and a gold plated layer is provided on the drain ohmic electrode, but a laminated structure of the metal layer and the gold plated layer is not provided on the source ohmic electrode. Because it is covered with a membrane,
Both the electrodes were not electrically short-circuited by the metal dust.

[0027]

As described above, according to the present invention, the laminated structure of the metal layer and the gold plating layer is provided on the drain ohmic electrode, but the laminated structure of the metal layer and the gold plating layer is provided on the source ohmic electrode. Since the structure is directly covered with the insulating film without providing a structure, there is an effect that both electrodes are not electrically short-circuited by metal dust.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for describing an embodiment and an example of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view for explaining an example of the related art.

FIG. 3 is a plan view for explaining another example of the related art.

[Explanation of symbols]

 Reference Signs List 11 semi-insulating GaAs substrate 12 n-type GaAs crystal layer 13 gate electrode 14 ohmic electrode on source side 15 ohmic electrode on drain side 16 insulating film 18, 20 metal layer and gold plated layer 19 via hole

Claims (3)

[Claims] A gate electrode forming a Schottky barrier with the semiconductor crystal layer; a pair of first and second ohmic electrodes; a via hole provided immediately below the first ohmic electrode; A semiconductor device comprising: a metal laminated structure provided on a second ohmic electrode; and an insulating film provided directly on the first ohmic electrode. 2. The semiconductor device according to claim 1, wherein said via hole is filled with a grounding metal. 3. The semiconductor device according to claim 1, wherein the metal laminated structure includes a predetermined metal layer and a gold plating layer.