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WO2000007248A1 - High electron mobility transistor - Google Patents

High electron mobility transistor

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Publication number
WO2000007248A1
WO2000007248A1 PCT/US1999/014805 US9914805W WO2000007248A1 WO 2000007248 A1 WO2000007248 A1 WO 2000007248A1 US 9914805 W US9914805 W US 9914805W WO 2000007248 A1 WO2000007248 A1 WO 2000007248A1
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WO
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Patent type
Prior art keywords
layer
buffer
concentration
lattice
indium
Prior art date
Application number
PCT/US1999/014805
Other languages
French (fr)
Inventor
William E. Hoke
Peter J. Lemonias
Original Assignee
Raytheon Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7785Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer

Abstract

A high electron mobility transistor structure (10) is provided having an insulating substrate (12) having a substrate lattice constant. A buffer layer (14) is disposed over the substrate and has a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constants. A channel layer (22) is disposed above the buffer layer and has a concentration of indium to provide a lattice constant of the channel layer that is larger than the substrate lattice constant.

Description

HIGH ELECTRON MOBILITY TRANSISTOR Background of the Invention This invention relates generally to field-effect transistors and more particularly to high electron mobility transistors (HEMTs) .

As is known in the art, there are several types of active devices that can amplify radio frequency (RF) signals. One such device is a HEMT. With HEMTs, a heterojunction is formed between a donor-spacer layer, including a doped pulse layer and an undoped spacer layer, and an undoped channel that has a smaller bandgap than the donor-spacer layer. The heterojunction provides spatial separation of electrons injected from the pulse layer into the channel layer from the donor atoms in the pulse layer. Electrons move parallel to the heterojunction confined within the channel layer. Limiting conduction to the channel layer provides low impurity scattering and good electron mobility.

Two types of HEMTs are gallium arsenide (GaAs) based HEMTs and Indium phosphide (InP) based HEMTs. GaAs HEMTs use GaAs wafers (i.e., substrates) and InP based HEMTs use InP wafers . The GaAs substrates are inexpensive and durable compared to the InP substrates. For example, a 4 in. diameter GaAs wafer costs about $200 while a 2 in. InP wafer costs about $250, a 3 in. InP wafer costs about $800-1,000, and 4 in. InP wafers are currently unavailable, preventing 4 in. manufacturing lines from using InP substrates. Channel layers in GaAs HEMTs typically are made of In^a^^s with 0.15≤x≤0.25. InP HEMTs, on the other hand, provide low noise figures and high gains, but the InP wafers are expensive and fragile compared to the GaAs wafers. InP HEMTs typically use a channel layer of In^a^^s, where 0.5≤x≤0.6. The increased indium in the channel of the InP HEMTs provides improved conductivity in the channel layer. The indium concentration in the InGaAs channel is limited due to the lattice constant of the InP substrate. The channel is lattice matched to the InP substrate if the indium concentration is about 53% (i.e., x=0.53). Indium concentrations above or below about 53% tend to cause dislocations in the material from strain if the channel layer is grown sufficiently thick, e.g., 400A, to provide other desirable features such as a flat transconductance response for improved linearity.

Summary of the Invention In accordance with a feature of the invention, a high electron mobility transistor structure is provided having an insulating substrate having a substrate lattice constant. A buffer layer is disposed over the substrate and has a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constant . A channel layer is disposed above the buffer layer and has a concentration of indium to provide a lattice constant of the channel layer that is larger than the substrate lattice constant. With such a structure, a channel layer with a high indium concentration can be used to provide good noise figure, high mobility, and good gain using a substrate with a smaller lattice constant than the channel. Also, strain produced by different lattice constants is relieved in the buffer layer, protecting against material dislocations in the channel layer affecting performance of the transistor.

In a preferred embodiment of the invention, a barrier/buffer layer is disposed over the buffer layer and has a lattice constant smaller than the second lattice constant.

In another preferred embodiment of the invention, the lattice constant of a portion of the buffer layer varies with distance from the substrate.

In accordance with another feature of the invention, a method of forming a high electron mobility transistor structure is provided. The method includes providing an insulating substrate having a substrate lattice constant. A buffer layer is formed over the substrate, the buffer layer having a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constant. A channel layer is formed above the buffer layer, the channel layer having a concentration of indium to provide a lattice constant of the channel layer larger than the substrate lattice constant.

In a preferred embodiment of the invention, forming the buffer layer includes growing a Group III-V buffer layer material at a first temperature in a first temperature range while increasing an indium concentration from a first indium concentration to an intermediate indium concentration, and growing the Group III-V buffer layer material at a temperature in a second temperature range while increasing the indium concentration from the intermediate indium concentration to a second indium concentration. A barrier/buffer layer is formed over the buffer layer by growing a Group III-V barrier/buffer layer material at a third temperature in a third temperature range. The second temperature range is lower than the first and the third temperature ranges. With such an arrangement, the buffer layer can be grown with a planar top surface .

In accordance with another feature of the invention, a field-effect transistor structure is provided having a gallium arsenide substrate. A buffer layer of a Group III-V material is disposed over the substrate and includes a Group III material having a graded indium concentration substantially equal to a first concentration near a bottom of the buffer layer and substantially equal to a second concentration near a top of the buffer layer larger than the first concentration. A barrier/buffer layer of a Group III-V material is disposed over the buffer layer and includes a Group III material having a third indium concentration lower than the second indium concentration. A channel layer of a Group III-V material is disposed above the buffer layer and includes a Group III material having an indium concentration substantially equal to the third concentration. In accordance with another feature of the invention, a field-effect transistor structure is provided having a gallium arsenide substrate having a substrate lattice constant. A buffer layer is disposed over the substrate and has a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constant. A channel layer is disposed above the buffer layer and has a concentration of indium to provide a lattice constant of the channel layer larger than the first substrate constant. A donor-spacer layer has a doped region and an undoped region and forms a heterojunction with the channel layer. A contact layer is disposed above the channel layer. With such an arrangement, a low-cost substrate can be used with a channel layer having enough indium to provide good noise figure, mobility, and gain, and a lattice constant for the channel layer that is larger than the lattice constant of the substrate.

In accordance with another feature of the invention, a high electron mobility transistor structure is provided having a gallium arsenide substrate. A buffer layer of Inx (AlyGa-^y) 1-xAs is disposed over the substrate, with O≤x≤l. The buffer layer has a graded concentration of indium such that x is about 0.05 near the substrate and is equal to m at a position remote from the substrate. A barrier/buffer layer of Inn(G3)1.nAs is disposed over the buffer layer, G3 being a Group III material and m being greater than n. A channel layer of InπGa-L.nAs is disposed above the first buffer layer. A donor-spacer layer has a doped region and an undoped region and forms a heterojunction with the channel layer. A contact layer is disposed above the channel layer. Embodiments of the invention may provide one or more of the following advantages. For example, an indium concentration in a channel layer is adjustable, allowing indium concentrations that produce a channel layer with a much different lattice constant than an associated substrate. A GaAs substrate can be used with a channel layer having a lattice constant that is larger than the substrate lattice constant without dislocations affecting device performance. High linearity, high gain, and low noise HEMT performance is possible at a much lower cost than InP based HEMTs.

Other advantages will become apparent from the following description and from the claims. Brief Description of the Drawings FIG. 1 is a cross-sectional diagrammatical view of a HEMT according to the invention;

FIG. 2 is a plot of indium concentration versus thickness and growth time of a buffer layer and of a barrier/buffer layer of the HEMT shown in FIG. 1;

FIG. 3 is a plot of temperature versus growth time of the buffer layer and the barrier/buffer layer shown in FIG. 1; FIG. 4 is a flow diagram of a method of making the HEMT shown in FIG. 1; and

FIG. 5 is a cross-sectional diagrammatical view of another HEMT according to the invention.

Description of Preferred Embodiments Referring to FIG. 1, a metamorphic high electron mobility transistor (MHEMT) 10 is shown. MHEMT 10 includes an insulating GaAs substrate 12, an undoped InAlGaAs buffer layer 14, an undoped In^-Al^^s barrier/buffer layer 16 500-1, 500A, and preferably 1,000A, thick, a doped pulse layer 18 with a silicon sheet concentration of about lxl012crrf2, an undoped In^l^ xAs spacer layer 20 about 50A thick, an undoped InGaAs, here In05Ga05As, channel layer 22 about 100-400A thick, an undoped In^Al^^- s spacer layer 24 about 30A thick, a doped pulse layer 26 with a silicon sheet concentration of about 2xl012cm~2 - 3xl012cιrf2, an undoped Inx_0 , 1A11.1-xAs Schottky layer 28 about 200A thick, an undoped InGaAs layer 30 about 100A thick, an n+ doped InGaAs contact layer 32 about 100A thick, a source electrode 34 and a drain electrode 36 in ohmic contact with contact layer 32, and a gate electrode 38 in Schottky contact with Schottky layer 28.

Pulse layer 18 and spacer layer 20 form a first donor-spacer layer 40 and spacer layer 24 and pulse layer 26 form a second donor-spacer layer 42. Donor-spacer layers 40 and 42 form heterojunctions with channel layer 22.

Although many values of x are possible, e.g., 0.2≤x≤1.0, for MHEMT 10 x equals 0.5. Thus, barrier/buffer layer 16, spacer layer 20, and spacer layer 24 have equal indium concentrations. The indium concentration refers to the ratio (e.g., percentage) of indium atoms of the total atoms of Group III material (i.e., a material containing Group III elements, e.g., InAlGa) , in a given material, here the Group III-V materials that make up barrier/buffer layer 16, spacer layer 20, and spacer layer 24. AlAs, GaAs, and AlGaAs have almost identical lattice constants. However, because indium to arsenic bonds are longer than gallium to arsenic and aluminum to arsenic bonds, alloying indium into AlAs, GaAs, or AlGaAs expands the lattice constant. Using different lattice constant materials in the same device introduces strain to the device . To reduce strain, channel layer 22 has an indium concentration substantially equal to that of layers 16, 20, and 24. For thick (e.g., 300-400A) channel layers, the channel layer indium concentration is preferably substantially equal to (e.g., within ±2 percentage points of) the indium concentrations of layers 16, 20 and 24. For thin channel layers (e.g., 100A) , the channel layer indium concentration can differ up to about ±20 percentage points from that of layers 16, 20, and 24. The indium concentration of Schottky layer 28 is slightly less than for layers 16, 20, and 24 in order to increase the bandgap of Schottky layer 28 and help the breakdown voltage of MHEMT 10.

Buffer layer 14 is a Group III-V material having a graded, metamorphic indium concentration and a thickness depending on the indium concentration. As shown in FIG. 2, at the bottom of buffer layer 14 (a0=0) , the indium concentration is about 5%. The indium concentration linearly increases with the thickness of buffer layer 14 until a maximum concentration cmax is reached at thickness a2 corresponding to the top of buffer layer 14 and corresponding to a maximum lattice constant. At a2, the indium concentration is about 3-8 percentage points higher than a desired relaxed indium concentration crel (i.e., the indium concentration associated with a desired relaxed lattice constant) . As shown, preferably the maximum indium concentration, here 55%, is about 5 percentage points more than the desired relaxed indium concentration, here 50%. The thickness of buffer layer 14 from a0 to a2 is about 0.5μm - 3.0μm. This thickness depends upon the desired relaxed indium concentration and the rate of increase of indium concentration in buffer layer 14.

The top of buffer layer 14 coincides with the bottom of barrier/buffer layer 16 at a2. Between a2 and the top a3 of barrier/buffer layer 16, a thickness of about 1,000A, the indium concentration is constant and equal to the desired relaxed indium concentration of 50%.

In MHEMT 10, the channel layer indium concentration substantially matches the desired relaxed indium concentration of about 50%. Thus, channel layer 22 can be made thick, e.g., 300-400A, to improve linearity (i.e., to flatten the transconductance response) . The 50% indium concentration in channel layer 22 provides MHEMT 10 with a low noise figure, high gain, good conductivity, and a conduction band discontinuity for the heterojunction between layers 40 and 42 and channel layer 22 of about 0.47 eV. This indium concentration also means that the lattice constant of channel layer 22 is larger than the lattice constant of substrate 12. The graded indium concentration of buffer layer 14 provides a graded lattice constant from substantially equal to the lattice constant of substrate 12 to a larger lattice constant than that of barrier/buffer layer 16. The lattice constant of buffer layer 14 changes with distance (a) from the upper surface of substrate 12 in accordance with the indium concentration in buffer layer 14. With an indium concentration of less than about 15%, here 5%, the lattice constant at the bottom a0 of buffer layer 14 is larger, but substantially equal to the lattice constant of substrate 12. The buffer layer lattice constant increases with buffer layer thickness (a) so that at the top a2 of buffer layer 14 the lattice constant is larger than the lattice constant of barrier/buffer layer 16.

Increased lattice constants in buffer layer 14 cause strain that results in dislocations in buffer layer 14 that relieve or relax the strain. Most of the dislocations in buffer layer 14 occur near substrate 12. This helps ensure that the dislocations do not effect device performance by guarding against dislocations in channel layer 22. Exceeding (i.e., "overshooting") the desired relaxed indium concentration in buffer layer 14 produces dislocations that relieve or relax most, if not all, of the strain associated with the desired relaxed lattice constant, which is lower than the maximum lattice constant .

Barrier/buffer layer 16 has the desired relaxed lattice constant. Barrier/buffer layer 16 is therefore substantially free of strain, i.e., is relaxed. Thus, most, if not all, of the strain associated with using the high indium concentration, high lattice constant channel layer 22 with the low lattice constant substrate 12 is relieved. Channel layer 22 has a lattice constant substantially equal to the desired relaxed lattice constant. With an indium concentration within ±2 percentage points, here 0 percentage points, of the barrier/buffer layer indium concentration, channel layer 22 has a lattice constant substantially equal to the desired relaxed lattice constant.

Referring to FIG. 4, a method 50 of making MHEMT 10 is shown. Method 50 uses molecular beam epitaxy (MBE) to deposit/grow materials on top of existing materials in a single wafer deposition chamber, e.g., a VG-80H made by VG Semicon, a division of Thermo Electron, Corp. Thus, a substrate 12 is provided and prepared (Step 54) , graded, metamorphic buffer layer 14 is grown (Steps 56, 58, 60, 62) , barrier/buffer layer 16 is grown (Steps 64 and 66) , device layers, including channel layer 22, are grown (Step 68) and etched (Step 70) , and ohmic contacts and Schottky contact are formed (Step 70) .

More particularly, GaAs substrate 12 is prepared (Step 54) by desorbing oxide from substrate 12 and growing layers to smooth the surface of substrate 12. Oxide is desorbed from substrate 12 at about 640 °C in an arsenic overpressure using conventional techniques. More GaAs is deposited at a temperature of about 560-600°C to a thickness of about 100-400A, preferably about 100A, to help provide a smooth top surface of GaAs. A 5-10 period superlattice is formed at about 560-600°C over the deposited GaAs. Each period includes about 20-40A of GaAs and 20-40A of AlyGa^yAs, where 0.2≤y≤1.0. This superlattice helps prevent propagation of substrate defects (e.g., dislocations) into buffer layer 14. More GaAs is grown over the superlattice at about 560-600°C to a thickness of less than about 1,000A, and preferably about 500A. Referring also to FIGS. 1-3, the temperature of the wafer is reduced (Step 56) and a portion of buffer layer 14 is grown (Step 58) from times t0 to t . The wafer temperature is reduced to between about 480°C and about 520°C. Buffer layer 14 is grown (Step 58) starting with either Al.95In.05As or In.05(AlwGa1_w) 95As. The indium concentration is initially less than about 15% to guard against 3 -dimensional (nonplanar) growth. As buffer layer 14 begins growing, more indium is introduced into the material being deposited so that the indium concentration linearly increases with time, t, and, correspondingly, with the thickness, a, of buffer layer 14. For In.05 (A^Ga^ .95As, as the indium concentration is increased, the aluminum and gallium concentrations are adjusted (aluminum being ramped up and gallium being ramped down) to help ensure that buffer layer 14 remains insulating and that the bandgap of buffer layer 14 remains greater than the bandgap of GaAs substrate 12. The indium concentration is linearly increased to an intermediate concentration cint between 10-20%, and preferably about 15%, at time t corresponding to thickness ax.

When the indium concentration in buffer layer 14 reaches the intermediate concentration cint, the temperature is reduced (Step 60) for more buffer layer growth (Step 62) . The temperature is reduced (Step 60) to between about 380 and about 420°C. Buffer layer 14 may be grown during the time needed to reduce (Step 60) the temperature or, as indicated in FIGS. 2 and 3, a growth interrupt may occur during temperature reduction.

With the temperature reduced (Step 60) , buffer layer 14 is continued to be grown (Step 62) . The reduced temperature helps reduce 3-dimensional growth, yielding substantially planar growth of buffer layer 14. The indium concentration is linearly increased between times tx and t2 while growing (Step 62) buffer layer 14 from thickness a-L to a2 until the indium concentration in buffer layer 14 reaches the predetermined maximum concentration craax at the top a2 of buffer layer 14. When the maximum desired indium concentration craax is reached, the temperature is increased (Step 64) for growing barrier/buffer layer 16 (Step 66) . The temperature is increased (Step 64) to between about 470 and about 520°C. Barrier/buffer layer 16 may be grown during the time needed to increase (Step 64) the temperature or, as indicated in FIGS. 2 and 3, a growth interrupt may occur during temperature increase (Step 64) . With the temperature raised (Step 64) , barrier/buffer layer 16 is grown (Step 66) with the indium concentration adjusted to the desired relaxed indium concentration crel .

Device layers 18, 20, 22, 24, 26, 28, 30, and 32 are grown (Step 68) and etched (Step 70) , and electrodes 34, 36, and 38 are formed (Step 70) . The device layers are grown (Step 68) at temperatures between about 480 and about 520°C using conventional techniques. A recess is formed (Step 70) through undoped layer 30 and contact layer 32 for gate electrode 38 using a selective succinic acid based etch based wet etch. Source and drain electrodes 34 and 36 are formed (Step 70) using an AuGe- Au metallurgy alloyed in a tube furnace in an H2 ambient . Gate electrode 38 is formed from Ti-Pt-Au as a 0.15μm - 0.25μm T-gate using conventional techniques to complete the device 10. MHEMTs similar to MHEMT 10 were built with an In065Ga0.35As channel layer and an In0.53Ga047As channel layer, respectively. The 65% In MHEMT exhibited room temperature mobility of greater than 10,000 cm2/Vs with a sheet density of 4xl012cm~2, and better transconductance and gain than pseudomorphic HEMTs (PHEMTs) . The 53% MHEMT exhibited better transconductance than PHEMTs, at least 3 dB better gain, and better noise figure above 11 GHz than PHEMTs.

Referring to FIG. 5, a metamorphic high electron mobility transistor (MHEMT) 80 is shown. FIG. 5 illustrates that the invention is applicable to other compositions than that of MHEMT 10 shown in FIG. 1. MHEMT 80 is similar to MHEMT 10 except that x=0.35 in MHEMT 80 and barrier/buffer layer 16 and Schottky layer 28 are replaced by barrier/buffer layer 82 and Schottky layer 84. Barrier layer 82 is made of Inx(GazAl1_z) j.χAs and Schottky layer 84 is made of (Ga-.A1-._J 1.1_xAs . Layers 82 and 84 are made using MBE with the appropriate ratios of elements. Other embodiments are within the spirit and scope of the appended claims. For example, the indium concentration in channel layer 22 can be different than specifically mentioned above. The channel layer indium concentration is adjustable, and can be as low as 0% or as high as 100%. Thus, the relaxed lattice constant of buffer layer 14 can be, e.g., as low as about 5.653A (GaAs) or as high as about 6.058A (InAs) . Also, undoped layer 30 and contact layer 32 may be formed as a single layer, either doped or undoped. What is claimed is:

Claims

1. A high electron mobility transistor structure comprising: an insulating substrate having a substrate lattice constant; a buffer layer disposed over the substrate and having a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constant; and a channel layer disposed above the buffer layer and having a concentration of indium to provide a lattice constant of the channel layer larger than the substrate lattice constant .
2. The structure recited in claim 1 further comprising a barrier/buffer layer disposed over the buffer layer.
3. The structure recited in claim 2 wherein the lattice constant near a top of the barrier/buffer layer is substantially equal to the lattice constant of the channe1 1ayer .
4. The structure recited in claim 2 wherein the lattice constant of the barrier/buffer layer is different from the lattice constant of the channel layer.
5. The structure of claim 2 wherein the lattice constant of the barrier/buffer layer is smaller than the second lattice constant.
6. The structure recited in claim 2 wherein the lattice constant of a portion of the buffer layer varies with distance from the substrate.
7. The structure recited in claim 2 wherein the buffer layer is a Group III-V material including a Group III material having a first concentration of indium at the bottom of the buffer layer lower than a second indium concentration at the top of the buffer layer.
8. The structure recited in claim 7 wherein the first indium concentration is about 5%.
9. The structure recited in claim 7 wherein the barrier/buffer layer is a Group III-V material including a Group III material having a lower indium concentration than the second indium concentration of the buffer layer.
10. The structure recited in claim 9 wherein a difference between the second indium concentration and the indium concentration of the barrier/buffer layer is between about 3 percentage points and about 8 percentage points .
11. The structure recited in claim 9 wherein the channel layer is a Group III-V material including a Group III material having an indium concentration substantially equal to an indium concentration of the barrier/buffer layer.
12. The structure recited in claim 7 wherein the channel layer is a Group III-V material including a Group III material having an indium concentration between about 25% and about 75%.
13. The structure recited in claim 7 wherein the indium concentration in the buffer layer varies with thickness of the buffer layer from the first indium concentration to the second indium concentration.
14. The structure of claim 13 wherein the indium concentration in the buffer layer varies linearly with thickness from the first concentration to the third concentration.
15. The structure recited in claim 1 wherein the substrate comprises gallium arsenide.
16. A method of forming a high electron mobility transistor structure, the method comprising: providing an insulating substrate having a substrate lattice constant; forming a buffer layer over the substrate, the buffer layer having a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constant; and forming a channel layer above the buffer layer, the channel layer having a concentration of indium to provide a lattice constant of the channel layer larger than the substrate lattice constant .
17. The method recited in claim 16 further comprising forming a barrier/buffer layer over the buffer layer.
18. The method recited in claim 17 wherein the barrier/buffer layer has a lattice constant substantially equal to the lattice constant of the channel layer.
19. The method recited in claim 17 wherein the barrier/buffer layer has a lattice constant different than the lattice constant of the channel layer.
20. The method recited in claim 17 wherein the lattice constant of the barrier/buffer layer is smaller than the second lattice constant.
21. The method recited in claim 17 wherein the buffer layer is a Group III-V buffer layer material including a Group III material having a first indium concentration near the bottom of the buffer layer and a second indium concentration, higher than the first indium concentration, disposed near the top of the buffer layer, and wherein the barrier/buffer layer is a Group III-V barrier/buffer layer material including a Group III material having an indium concentration lower than the second indium concentration.
22. The method recited in claim 21 wherein forming the buffer layer includes growing the Group III-V buffer layer material at a first temperature in a first temperature range while increasing the buffer layer indium concentration from the first indium concentration to an intermediate indium concentration, and growing the Group III-V buffer layer material at a second temperature in a second temperature range while increasing the buffer layer indium concentration from the intermediate indium concentration to the second indium concentration, and wherein forming the barrier/buffer layer includes growing the Group III-V barrier/buffer layer material at a third temperature in a third temperature range, and wherein the second temperature range is lower than the first and third temperature ranges .
23. The method recited in claim 22 wherein the first temperature range is about 480┬░C to about 520┬░C, the second temperature range is about 380┬░C to about 420┬░C, and the third temperature range is about 470┬░C to about 520┬░C.
24. A field-effect transistor structure comprising: a gallium arsenide substrate; a buffer layer of a Group III-V material disposed over the substrate and including a Group III material having a graded indium concentration substantially equal to a first concentration near a bottom of the buffer layer and substantially equal to a second concentration near a top of the buffer layer larger than the first concentration; a barrier/buffer layer of a Group III-V material disposed over the buffer layer and including a Group III material having a third indium concentration lower than the second indium concentration; and a channel layer of a Group III-V material disposed above the buffer layer and including a Group III material having an indium concentration substantially equal to the third indium concentration.
25. A field-effect transistor structure comprising: a gallium arsenide substrate having a substrate lattice constant; a buffer layer disposed over the substrate and having a graded lattice constant substantially equal to a first lattice constant near a bottom of the buffer layer and substantially equal to a second lattice constant near a top of the buffer layer larger than the substrate lattice constant and the first lattice constant; a channel layer disposed above the buffer layer and having a concentration of indium to provide a lattice constant of the channel layer larger than the substrate lattice constant; a donor-spacer layer having a doped region and an undoped region forming a heterojunction with the channel layer; and a contact layer disposed above the channel layer.
26. A high electron mobility transistor structure comprising: a gallium arsenide substrate; a buffer layer of Inx (AlyGa_..y) 1-xAs disposed over the substrate, where OΓëñxΓëñl, the buffer layer having a concentration of indium such that x is about 0.05 near the substrate and is equal to m at a position remote from the substrate; a barrier/buffer layer of In., (G3) __nAs disposed over the buffer layer, G3 being a Group III material and m being greater than n; a channel layer of InnGa1.ΓÇ₧As disposed above the first buffer layer; a donor-spacer layer having a doped region and an undoped region forming a heterojunction with the channel layer; and a contact layer disposed above the channel layer.
27. The structure recited in claim 26 wherein m is about 0.05 greater than n.
28. The structure recited in claim 26 wherein the indium concentration in the buffer layer increases substantially linearly with buffer layer thickness from the substrate to the position remote from the substrate.
29. The structure recited in claim 26 wherein the donor-spacer layer is a first donor-spacer layer disposed between the buffer layer and the channel layer, the structure further comprising a second donor-spacer layer disposed over the channel layer and having a doped region and an undoped region forming a heterojunction with the channel layer.
30. The structure recited in claim 29 wherein G3 is GazAl1-z/ wherein the first donor-spacer layer comprises : a first pulse layer disposed over the barrier/buffer layer and including a high concentration of carriers; and a first spacer layer of Inn(GazAl1_J 1-nAs disposed over the first pulse layer; wherein the second donor-spacer layer comprises: a second spacer layer of Ir^ (Ga-Al^J 1-riAs disposed over the channel layer; a second pulse layer disposed over the second spacer layer and including a high concentration of carriers ; and wherein the structure further comprises a Schottky layer of Inn.01 CGa-Al^-As) 1#-,._-, disposed over the second pulse layer.
31. The structure recited in claim 29 wherein G3 is Al, wherein the first donor-spacer layer comprises: a first pulse layer disposed over the barrier/buffer layer and including a high concentration of carriers; and a first spacer layer disposed over the first pulse layer; wherein the second donor-spacer layer comprises: a second spacer layer disposed over the channel layer; a second pulse layer disposed over the second spacer layer and including a high concentration of carriers ; and wherein the structure further comprises a Schottky layer of Ir_n_0.1Al1.__nAs disposed over the second pulse layer.
PCT/US1999/014805 1998-07-31 1999-06-29 High electron mobility transistor WO2000007248A1 (en)

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US6888179B2 (en) 2003-04-17 2005-05-03 Bae Systems Information And Electronic Systems Integration Inc GaAs substrate with Sb buffering for high in devices
WO2008041249A1 (en) * 2006-10-04 2008-04-10 Selex Sistemi Integrati S.P.A. Single voltage supply pseudomorphic high electron mobility transistor (phemt) power device and process for manufacturing the same

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US5319223A (en) * 1991-07-26 1994-06-07 Kabushiki Kaisha Toshiba High electron mobility transistor
US5633516A (en) * 1994-07-25 1997-05-27 Hitachi, Ltd. Lattice-mismatched crystal structures and semiconductor device using the same

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US5319223A (en) * 1991-07-26 1994-06-07 Kabushiki Kaisha Toshiba High electron mobility transistor
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US6888179B2 (en) 2003-04-17 2005-05-03 Bae Systems Information And Electronic Systems Integration Inc GaAs substrate with Sb buffering for high in devices
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WO2008041249A1 (en) * 2006-10-04 2008-04-10 Selex Sistemi Integrati S.P.A. Single voltage supply pseudomorphic high electron mobility transistor (phemt) power device and process for manufacturing the same
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