CN100350577C - Gallium-indium-nitride-arsenide based epitaxial wafer and hetero-field effect transistor using the same, and its manufacturing method - Google Patents
Gallium-indium-nitride-arsenide based epitaxial wafer and hetero-field effect transistor using the same, and its manufacturing method Download PDFInfo
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Abstract
A hetero-field-effect transistor comprises an InP substrate (21), a channel layer (23) formed on a buffer layer (22) on the InP substrate, a spacer layer (25a) made of a semiconductor having a bandgap larger than that of the channel layer and having a heterojunction with the channel layer, and a carrier supply layer (26) adjacent to the spacer layer. The channel layer includes a predetermined semiconductor layer made of a compound semiconductor the composition of which is expressed by chemical formula GaxIn1-xNyA1-y, where A is As or Sb, the number x is 0<=x<=0.2, the number y is 0.03<=y<=0.10.
Description
Technical field
The present invention relates to the nitrogenize Gallium indium arsenide is the hetero-field effect transistor of epitaxial wafer, its manufacture method and with its transceiver.
Background technology
The hetero-field effect transistor of High Electron Mobility Transistor (HEMT) etc. is the compound semiconductor element that utilizes 2 dimensional electron gas that is formed with heterogeneous structure.
The first existing example as this HEMT has the HEMT that forms InAlAs charge carrier supplying layer/InGaAs channel layer/InAlAs resilient coating on the InP substrate as shown in figure 13.In Figure 13, label 1 expression electrode metal, label 2 expression n+-InGaAs cap rocks, label 3 expression n-InAlAs charge carrier supplying layers, label 4 expression i-InAlAs walls, label 5 expression i-InGaAs channel layers, label 6 expression i-InAlAs resilient coatings, label 7 expression half insulation InP substrates (S.I.-InP substrate).This HEMT because with InGaAs channel layer 5, so with GaAs relatively as the HEMT of channel layer because its high electron transport property is expressed the high frequency characteristics of excellence.Particularly, feature of this existing example is that the InAs layer 8 that will have 1～7nm thickness in InGaAs channel layer 5 is inserted into from InAlAs wall 4 and leaves on the position of 0～6nm (for example, please refer to Japanese kokai publication hei 5-36726 patent gazette (patent documentation 1)).
Again, as the second existing example, the HEMT with the GaInNAs channel layer that forms on the GaAs substrate as shown in figure 14.At this HEMT, the not Doped GaAs resilient coating 12 of 0.5 μ m is set on semiconductive GaAs substrate 11, on this resilient coating 12, form the not doping GaInNAs channel layer 13 of thickness 15nm.Further, the not doped with Al GaAs wall 16 formation thickness through thickness 2nm on it are the n type AlGaAs charge carrier supplying layer 14 of 50nm, form electrode 18 by evaporation on this AlGaAs charge carrier supplying layer 14.It all is 0.28 (for example, please refer to TOHKEMY 2002-164852 patent gazette (patent documentation 2)) that the Al of wall 16 and charge carrier supplying layer 14 forms.
But, in the first existing example, in the situation of inserting InAs layer 8, produce lattice and do not match as mentioned above, defective takes place more than critical film thickness.Thereby because the thickness that can not make channel layer more than critical film thickness, can not be realized enough carrier densities, the improvement of characteristic is inadequate.
On the other hand, the second existing example forms on GaAs substrate 11 in the situation of InGaAs layer, in order to solve the problem on the characteristic that is caused by the lattice match that is difficult to realize InGaAs layer and GaAs substrate, imports N in the InGaAs of formation channel layer.In this second existing example, realize lattice match by the channel layer 13 and the GaAs substrate 11 that constitute by GaInNAs, compare with the situation that on GaAs substrate 11, forms the InGaAs channel layer, can positively improve characteristic.But, can not realize characteristic above the first existing example of the InGaAs channel layer that on the InP substrate, forms.
Summary of the invention
The purpose of this invention is to provide the raising electron mobility, hetero-field effect transistor that therefore can high speed motion, its manufacture method and with its transceiver.
And, in order to reach these purposes, the channel layer that the hetero-field effect transistor relevant with the present invention have substrate, form on aforesaid substrate through resilient coating, constitute and engage wall that forms and the charge carrier supplying layer that forms in abutting connection with ground with above-mentioned wall with this channel layer is heterogeneous by semiconductor with band gap bigger (bandgap) than above-mentioned channel layer; Aforesaid substrate is made of InP; Above-mentioned channel layer has by chemical formula Ga
xIn
1-xN
yA
1-yExpression, above-mentioned A is As or Sb, above-mentioned composition x is in the scope of 0＜x＜0.2, and the compound semiconductor layer of above-mentioned composition y in the scope of 0.03≤y≤0.10.
Above-mentioned composition y also can be in the scope of 0.03≤y≤0.07.
Above-mentioned A also can be As.
Above-mentioned A also can be Sb.
Above-mentioned channel layer also can only be made of the above-claimed cpd semiconductor layer.
Above-mentioned channel layer also can have first channel layer and with this first channel layer in abutting connection with and with heterozygous second channel layer of above-mentioned wall, above-mentioned first channel layer is made of the above-claimed cpd semiconductor layer, above-mentioned second channel layer is made of the InAs layer.
Also can x=0.
The N concentration of above-mentioned first channel layer also can be along with the related reduction near above-mentioned second channel layer.
Also can form a pair of above-mentioned second channel layer in mode with the top and following adjacency of above-mentioned first channel layer, to form a pair of above-mentioned wall, form a pair of above-mentioned charge carrier supplying layer in mode with above-mentioned a pair of wall adjacency with the heterozygous mode of above-mentioned a pair of second channel layer.
Also can 0＜x.
Also can further satisfy 3y≤x≤0.2.
Also can satisfy 0.1≤x≤0.2.
Above-mentioned first channel layer also can be made of the GaInNAs/InAsMQW layer of the multiple quantum trap structure that forms as the semi-conductive GaInNAs layer of the above-claimed cpd of 0＜x and the mutual lamination of InAs layer.
Above-mentioned first channel layer also can be by constituting as the InNAs layer of the compound semiconductor of x=0 and the InNAs/InAsMQW layer of the multiple quantum trap structure that the mutual lamination of InAs layer forms.
Also can above-mentioned resilient coating and above-mentioned wall constitute by the InAlAs layer, above-mentioned charge carrier supplying layer is made of the n-InAlAs layer.
Again, the manufacture method of the hetero-field effect transistor relevant with the present invention has: the channel layer that forms channel layer through resilient coating on aforesaid substrate forms operation; Form operation with the wall that forms the wall that constitutes by semiconductor with the heterozygous mode of this channel layer with band gap bigger than above-mentioned channel layer; Form operation with the current-carrying sublayer that forms the charge carrier supplying layer in abutting connection with ground with above-mentioned wall, aforesaid substrate is made of InP, and above-mentioned channel layer has by chemical formula Ga
xIn
1-xN
yA
1-yExpression, above-mentioned A is As or Sb, above-mentioned composition x is in the scope of 0≤x≤0.2, and the compound semiconductor layer of above-mentioned composition y in the scope of 0.03≤y≤0.10.
In the operation that forms above-mentioned channel layer, also can import Ionized N atom.
Also can have the resilient coating that on above-mentioned InP substrate, forms the above-mentioned resilient coating that constitutes by InAlAs and form operation, above-mentioned channel layer forms operation to have: second channel layer that forms operation and form second channel layer that is made of InAs on above-mentioned first channel layer at first channel layer that forms first channel layer that is made of InNAs on the above-mentioned resilient coating forms operation, form in the operation at above-mentioned wall, can on above-mentioned second channel layer, form the above-mentioned wall that constitutes by InAlAs.As form this formation, when forming the interface of channel layer and wall, because N atom and Al atom do not exist simultaneously, so can form good interface.
Again, the transceiver relevant with the present invention is in order to handle and to have hetero-field effect transistor according to claim 1 sending signal or received signal.
Above-mentioned purpose of the present invention, other purpose, feature and advantage will see too clearly from the detailed description of with reference to the accompanying drawings suitable execution mode being carried out.
Description of drawings
Fig. 1 is the sectional view of the formation of the expression hetero-field effect transistor relevant with embodiments of the present invention 1.
Fig. 2 is the figure that expression can be with structure, and Fig. 2 (a) is the figure that can be with structure of expression InGaAs, and Fig. 2 (b) is the figure that can be with structure of expression GaInNAs.
Fig. 3 is the figure of energy state in the structure of being with of presentation graphs 2, and Fig. 3 (a) is the figure that amplifies the energy state that the Γ of presentation graphs 2 (a) order, and Fig. 3 (b) is the figure of the Γ of amplification presentation graphs 2 (b) energy state of ordering.
Fig. 4 is the table of physics value in the crystal of expression various kinds of compound semiconductors.
Fig. 5 is the velocity of electrons in the crystal of expression various kinds of compound semiconductors and the figure of the relation of electric field.
Fig. 6 is the figure of the preferable range of the expression ratio of components that constitutes Ga in the GaInNAs4 unit based compound of channel layer of the present invention and N.
Fig. 7 is the sectional view of the formation of the expression hetero-field effect transistor relevant with embodiments of the present invention 2.
Fig. 8 (a) and (b) are figure of channel layer energy state nearby of the hetero-field effect transistor of presentation graphs 7.
Fig. 9 is the sectional view of the formation of the expression hetero-field effect transistor relevant with the variation of embodiments of the present invention 2.
Figure 10 is the figure of the formation of the expression hetero-field effect transistor relevant with embodiments of the present invention 3, and Figure 10 (a) is a sectional view, and Figure 10 (b) is the figure of the energy state near the channel layer of expression Figure 10 (a).
Figure 11 is the sectional view of the formation of the expression hetero-field effect transistor relevant with second variation of embodiments of the present invention 2.
Figure 12 is the block diagram of the formation of the expression transceiver relevant with embodiments of the present invention 4.
Figure 13 is the sectional view that expression first has the formation of routine hetero-field effect transistor.
Figure 14 is the sectional view that expression second has the formation of routine hetero-field effect transistor.
Embodiment
Below, we simultaneously illustrate embodiments of the present invention with reference to accompanying drawing at one side.
{ notion of the present invention }
We illustrate notion of the present invention at first.
The feature of hetero-field effect transistor of the present invention is to form Ga and N to have the GaInNAs of ratio of components of prescribed limit as channel layer on the InP substrate.In the present invention, in this GaInNAs, be 0 o'clock sample attitude as the ratio of components of Ga, comprise InNAs.In other words, in the first existing example, has the formation that the ratio of components with the Ga of InGaAs channel layer is set in setting and adds nitrogen (N) in the mode that becomes the regulation ratio of components in the InGaAs channel layer.
At first, we illustrate by add the effect that nitrogen-atoms produces in the InGaAs crystal simply with Fig. 2 (a) and (b), Fig. 3 (a) and (b).
Fig. 2 (a) is the figure that can be with structure of expression InGaAs, and Fig. 2 (b) is the figure that can be with structure of expression GaInNAs.Again, Fig. 3 (a) is the figure that amplifies the energy state that the Γ of presentation graphs 2 (a) order, and Fig. 3 (b) is the figure of the Γ of amplification presentation graphs 2 (b) energy state of ordering.In Fig. 2 (a) and (b), transverse axis is represented the position on the K space, and the longitudinal axis is represented energy.In Fig. 3 (a) and (b), transverse axis is represented momentum, and the longitudinal axis is represented energy.
Again, Fig. 2 (a) and (b) are tried to achieve by simulation, suppose in existing example, form In on the InP substrate
0.5Ga
0.5The As crystal layer in the present invention, forms Ga on the InP substrate
0.5In
0.5N
0.125As
0.875Crystal layer.
In Fig. 2 (a), at In
0.5Ga
0.5Being with in the structure of the conduction band 34 of As crystal, the energy level that Γ is ordered is minimum, and electronics is advanced through this Γ point.In Fig. 3 (a), the situation of whole InGaAs has the energy shown in dotted line 41 and the proportional relation of 2 powers of momentum.In with the situation of InGaAs layer as the quantum well of potential well layer structure, shown in heavy line 42 quantization of energy form stepped can the band structure, obtain electron density shown in fine line 43 by weighted integral with the fermi-distribution 46 of electronics.
On the other hand, shown in Fig. 2 (b), at Ga
0.5In
0.5N
0.125As
0.875In the situation of crystal, near the energy state the W point becomes smooth, shows the effect of adding nitrogen.This is that the energy that Γ is ordered reduces owing to there is the energy level of nitrogen, but the energy that L is ordered reduces hardly.Thereby we see by adding the energy difference Δ that nitrogen is ordered Γ point and L
Γ LIncrease.We will be described hereinafter, but we see this Δ
Γ LThe maximum of big more Electron drift speed increases more, adds nitrogen and exists advantage.But shown in Fig. 3 (b), when representing near amplifying the Γ point, the Energy distribution 48 of whole GaInNAs departs from the 2 powers relation to momentum, and the recruitment of energy reduces.This is because form by what nitrogen-atoms produced and can be with 47 by adding nitrogen-atoms, the result, take place with InGaAs intrinsic can be with the cause of mixing of 41 (please refer to Fig. 3 (a)).In producing the situation that to be with mixing, when shown in Fig. 3 (b), because by nitrogen-atoms produce can with 47 and InGaAs intrinsic can be with 41 to repel, so along with intrinsic be with of InGaAs near being with 47, the energy minimizing in same momentum by the nitrogen-atoms generation.Again, even if in momentum is 0 situation because exist by nitrogen-atoms produce can with 47 and InGaAs intrinsic can be with 41 mixing, so even if the curvature of the Energy distribution of GaInNAs 48 is 0 also to become big at momentum.
As other viewpoint, the effect that we add nitrogen-atoms from the effective mass explanation of electronics.Because the curvature that can be with is big, mean that the effective mass of electronics is big, what produced by nitrogen-atoms can be straight line with the momentum dependence of 47 energy, so curvature is big, effective mass increases.On the other hand, what InGaAs was intrinsic can be with, because curvature is little, so effective mass is also little.Thereby, when adding nitrogen-atoms because in InGaAs effective mass big being with of nitrogen-atoms cause mixing, so the effective mass of GaInNAs is bigger than InGaAs certainly, the big equivalence of curvature of the Energy distribution 48 of this and GaInNAs.
Below, our explanation by add nitrogen-atoms enable with curvature become greatly influence to electronic device.When using, because usually electronics is confined on the heterogeneous interface of wall and channel layer, so, have stepped Energy distribution by making energy quantity of state as electronic device with heterogeneous structure.As a result, because become the stage shape, energy takes place sharply to change, so the state (state density) that can exist at this portions of electronics increases.The energy difference of wall and channel layer is big more, and effective mass is more little, and the hop count in stage is just few more.On the other hand, when room temperature, can there be the high-energy of which kind of degree in fermi-distribution 46 expression electronics.When the product of the fermi-distribution of state density that obtains the state that can exist and electronics, can try to achieve the electron density in the particular energy as electronics.In order to increase electron density, exist (1) little by the band gap that makes channel layer, near Fermi level, thereby make with product increase, (2) of fermi-distribution little by the energy difference that makes stage portion, the quantum level that makes high-order is near Fermi level, thereby make with the product of fermi-distribution increase, (3) increase by making effective mass, makes state density self increase such 3 kinds of methods.Reduce band gap (because in order after adding nitrogen-atoms, to make lattice match increase the addition of In from (1) that produces by interpolation nitrogen-atoms channel layer, so further reduce band gap), (2) because effective mass increases, so the section difference reduces, (3) increase because of effective mass, so state density increases such 3 effects, we see by adding nitrogen-atoms increases electron density, have the box lunch of being when adding big electric field, electronics also is difficult to overflow such advantage from the Γ point to the L point.This responsiveness under the situation that shortens channel length is not easy saturated, does not produce the gunn vibration, is extremely effective.
As mentioned above,, have the increase effective mass, reduce mobility, but increase Δ by adding nitrogen-atoms
Γ L, the advantage of increase state density.Therefore, we estimate quantitatively and can expect which kind of degree these have influence on.The result is shown in the table of Fig. 4.In this table, represented the physics value that obtains under study for action.By these physics values are made clear, can realize and estimate hetero-field effect transistor of the present invention.Fig. 5 represents from mobility (hall mobility) μ l and the Δ of electronics weak electric field
Γ L, the result of the velocity of electrons when calculating adds electric field.From Fig. 5 as seen, velocity of electrons increases along with the increase of applied field, even if but add that velocity of electrons becomes maximum some v
dAbove electric field, velocity of electrons descends on the contrary.This, shown in Fig. 5 left part because electronics is present in the big Γ point of the little mobility of its effective mass when electric field is low, thus velocity of electrons increase along with the increase of applied field, but electronics spills into the L point when the electric field that adds more than this.Because at L point effective mass m
*Greatly, mobility is little, so total mobility reduces, velocity of electrons also reduces.Make that this velocity of electrons maximum is v
d, be illustrated among Fig. 4.As seen from Figure 4, velocity of electrons maximum v
dOrder with GaInNAs＜GaAs＜InP＜InGaAs＜InNAs＜InAs increases, but this is because the Δ of InP
Γ LBigger than GaAs, the also big cause of μ l of further InGaAs and InAs.Here, in the situation of GaInNAs, because Δ
Γ LBig and μ l is terrifically little, so velocity of electrons maximum v
dBe reduced to below the GaAs.On the other hand, in the situation of InNAs, although reduce Δ because compare μ l with InGaAs
Γ LGreatly, so the result can access (the v than InGaAs
d=3.96 * 10
5M/s) big v
d(=4.47 * 10
5M/s).As a result, we distinguish by replace the InGaAs layer with the InNAs layer as channel layer, velocity of electrons increases, responsiveness improves about 20%.
That is, when replacing the InGaAs layer with the GaInNAs layer during as channel layer, velocity of electrons reduces, and responsiveness reduces, but when replace the InGaAs layer with the InNAs layer as channel layer, velocity of electrons increases, responsiveness improves about 20%.Therefore, we distinguish that velocity of electrons increases by replacing the GaInNAs layer of Ga ratio of components that the InGaAs layer will have certain scope as channel layer, and responsiveness improves.
Below, the preferred range of the ratio of components of our Ga of explanation in this GaInNAs layer and N.
Fig. 6 is the figure of the so-called preferable range of the expression ratio of components that constitutes Ga in the GaInNAs4 unit based compound of channel layer of the present invention and N (below be also referred to as concentration (correct is atomic concentration)).
As shown in Figure 6, result of study according to this patent inventor, distinguished that Ga concentration in the scope below 20% more than 0% and in the zone (hereinafter referred to as zone of the present invention) 63 of N concentration in the scope below 10% more than 3%, can grow the GaInNAs layer that does not produce defective on the InP substrate.In Fig. 6, label 61 is the Ga composition of expression and InP lattice match and the straight line of the relation that N forms.When the composition with GaInNAs is expressed as Ga
xIn
1-xN
yAs
1-yThe time, this straight line becomes x=0.47-6.7y.So far say about x=0.47-3y.N concentration needs about 15%, but by selecting the ion that does not form gathering (cluster) from the nitrogen ion with the magnetic filtering device according to the mass spectral analysis principle, can be with they supplying substrate surfaces equably, and making crystal growth temperature is as optimum temperature 550 ℃, the N atom is evenly dispersed among the GaInAs, we see in lower N atomic concentration, also can carry out lattice match with InP.As a result, do not have N concentration to increase the phenomenon that band gap is diminished partly,, can realize lattice match and the stable change that can be with yet with N concentration still less.Particularly, when N concentration more than 3% 7% when following, in channel layer, produce the compression distortion, can stably obtain 15000cm
2Hall mobility before and after the/Vs.This is to consider because sharply reduce the cause of hall mobility increase in the effective mass of 20% electronics when following when Ga concentration.In execution mode 1 described later, by the InN that forms that has with InP substrate lattice match
0.07As
0.93(composition 1. of Fig. 6) constitutes channel layer, but if the composition in 63 scopes of the zone of the invention described above then can stably obtain 15000cm
2The high hall mobility that/Vs is above.Of the present invention regional 63, so because make the thickness of channel layer set distortion of lattice more than the 10nm in ± 1.5%.
Gather above explanation, constitute the Ga of GaInNAs of channel layer of the present invention and the ratio of components of N, preferred Ga concentration in the scope below 20% more than 0% and N concentration in the scope below 10% more than 3%.This is because sharply reduce the cause of hall mobility increase when the effective mass of Ga concentration at 20% electronics when following.Again, this be because when N concentration less than 3% the time, it is inadequate increasing by velocity of electrons that the responsiveness of bringing improves, when N concentration surpassed 10%, generation was to the unmatched cause of the lattice of InP substrate.Be more preferably N concentration in the scope below 7% more than 3% again.This is because when in this scope, produces compression and distort in channel layer, can stably obtain high (15000cm here
2The cause of hall mobility/Vs front and back).
Below, we illustrate the execution mode that makes reification of the present invention in turn.
(execution mode 1)
Fig. 1 is the sectional view of the formation of the expression hetero-field effect transistor relevant with embodiments of the present invention 1.
As shown in Figure 1, this hetero-field effect transistor has InP substrate 21.Lamination InAlAs resilient coating 22, InNAs channel layer 23, the InAlAs first wall 25a, n-InAlAs charge carrier supplying layer 26, the InAlAs second wall 25b in turn on InP substrate 21.On the InAlAs second wall 25b, form the electrode 29a that constitutes grid, be provided with in electrode 29a both sides at interval, form the pair of electrodes 29b, the 29c that constitute source electrode and drain electrode.On the InAlAs second wall 25b, form electrode 29b, 29c through n-InGaAs contact layer 28.
Below, we illustrate the manufacture method of the hetero-field effect transistor of such formation.
In this manufacture method, with gas source MBE (Molecular Beam Epitaxy (molecular beam epitaxy) method.Unstrpped gas is PH
3, AsH
3, N
2, In, Ga, Si.N
2Supply with by in plasma source, resolving into the N atom.PH
3And AsH
3Supply with by thermal decomposition.One side is supplied with PH
3One side is warmed up to 550 ℃, on half insulation InP substrate 21, and growth i-InAlAs resilient coating (thickness 500nm) 22, InNAs channel layer (20nm) 23, i-InAlAs wall (5nm) 25a, n
+-InAlAs charge carrier supplying layer (10nm, n type impurity concentration n=10
19Cm
-3) 26, i-InAlAs wall (20nm) 25b, n
+-InGaAs contact layer (100nm) 28.After this, remove the contact layer 28 of area of grid, in the regulation zone, form respectively and constitute grid, source electrode, electrode metal 29a, the 29b of drain electrode, 29c by evaporation by etching.Make that grid length is 0.2 μ m, grid width is 200 μ m.Hall mobility during as a result, with formation InGaAs layer on the InP substrate is 10000cm
2/ Vs is relative, and is relative therewith, and in the present embodiment, hall mobility becomes from 12000cm
2/ Vs is to 15000cm
2Value in the scope of/Vs, and the responsiveness f of hetero-field effect transistor
T, the 200GHz during with formation InGaAs layer on the InP substrate is relative, in the present embodiment, is increased to the value in the scope from 250GHz to 300GHz.
(execution mode 2)
Fig. 7 is the sectional view of the formation of the expression hetero-field effect transistor relevant with embodiments of the present invention 2.The label identical with Fig. 1 represented identical or suitable part in Fig. 7.
As shown in Figure 7, in the present embodiment, channel layer is made of the such 2 class layers of InAs layer 24 (thickness 4nm) as the InNAs layer 23 (thickness 10nm) of first channel layer and conduct second channel layer that forms on InNAs layer 23.Others are identical with execution mode 1.
The reason of Gou Chenging is as beginning illustrates with Fig. 4 and Fig. 5, because the velocity of electrons maximum v of InAs layer like this
dBigger than InNAs layer, so in order to apply flexibly the advantage of this InAs layer.When being elaborated, because having about 3% lattice for InP substrate 21, InAs channel layer 24 do not match, so can not the above thickness of lamination 4nm.So as the first existing example like that when in the InGaAs layer, forming thin InAs layer, exist the migration that generation is ordered to L from the Γ point before charge carrier spills into the InGaAs layer, the problem that the responsiveness reduction is such., as present embodiment, confirmed when forming the energy InN lower slightly in abutting connection with ground than InAs channel layer 24 with InAs channel layer 24
0.03As
0.97During channel layer 23 (Fig. 6 composition 2.), because before the charge carrier in being confined to InAs channel layer 24 moved from the Γ point to the L point, charge carrier spilt into InNAs channel layer 23 from InAs channel layer 24, so responsiveness does not reduce.Here, because InNAs channel layer 23 hangs down 0.1eV approximately than InAs channel layer 24 on energy, so can consider charge carrier preferentially advances by InNAs channel layer 23, so but because in fact the InAlAs wall 25 that InAs channel layer 24 and band gap are big engages can be with shown in Fig. 8 (a) on the interface of InAs channel layer 24 and InAlAs wall 25 and bends, so electronics is closed in the interface of InAs channel layer 24 and InAlAs wall 25.
Further again, can between InAlAs wall 25 and InNAs channel layer 23, sandwich InAs channel layer 24, when crystal growth, stop to supply with and begin to supply with the Al atom again behind the N atom a little while and get final product, as implement mode 1, so can not form good interface because when forming the interface of InAlAs wall 25 and InNAs channel layer 23, supply with the situation of Al atom and N atom simultaneously.Its reason is because form AlN as the high resistance insulator when Al and N exist simultaneously, thus on the interface, form many impurity energy levels, but in the situation of present embodiment, because existence simultaneously of Al and N, so do not form AlN.
; in execution mode 1 and 2; make the N concentration of InNAs certain; but in whichever execution mode; by in the InNAs channel layer, reducing N concentration (along with reducing near surperficial N concentration) at thickness direction from substrate-side towards face side; form and shown in Fig. 8 (b), can be with structure, particularly in execution mode 2, can suppress the unwanted outflow of charge carrier from InAs channel layer 24 to InNAs channel layers 23.
In the present embodiment, utilize Si to be equivalent to 1 atomic layer 5 * 10 again,
12Cm
-2The δ doped region 26 that adds InAlAs to and obtain forms the charge carrier supplying layer.As a result, we see that hall mobility is increased to 20000cm
2/ Vs, and the responsiveness f of hetero-field effect transistor
TBe increased to 400～450GHz.
In addition, as modified embodiment of the present embodiment, as shown in Figure 9, also can adopt first, second wall 25a, the 25b through constituting respectively by InAlAs, form first, second charge carrier supplying layer 26a, the 26b that constitutes by the δ doped region in the channel layer both sides that constitute by InNAs channel layer 23 and first, second InAs channel layer 24a, 24b, further form the double channel structure of first, second InAs channel layer 24a, 24b in the both sides of InNAs channel layer 23.In addition, form InAlAs the 3rd wall 25c between the first charge carrier supplying layer 26a and the InAlAs resilient coating 22, on the second charge carrier supplying layer 26b, form InAlAs the 4th wall 25d.In the situation of this structure, because count the magnitude of current that increase is flow through, so can realize high speed motion up to about the about 500GHz of the current range of about 500mA with single grid by increasing raceway groove.Again, we see by form a pair of first, second InAs channel layer 24a, 24b in the mode that clips InNAs channel layer 23 like this, the charge carrier that overflows from first, second InAs channel layer 24a, 24b flows into InNAs layer 23, also form raceway groove in fact in InNAs layer 23, consequent electric current is also made contributions to the increase of this magnitude of current.
(execution mode 3)
Figure 10 (a) is the sectional view of the formation of the expression hetero-field effect transistor relevant with embodiments of the present invention 3, and Figure 10 (b) is the figure of the energy state near the channel layer of expression Figure 10 (a).The label identical with Fig. 7 represented identical or suitable part in Figure 10 (a).
Shown in Figure 10 (a), in the present embodiment,, replace the InNAs channel layer 23 of execution mode 2 as first channel layer, form GaInNAs channel layer 23.Others are identical with execution mode 2.
In execution mode 2 because for easy grown crystal with InNAs layer 23 as first channel layer, so exist the worry that charge carrier overflows from InAs layer 24 shown in Fig. 8 (a).Therefore, in the present embodiment, we try to replace InNAs channel layer 23, are formed on the GaInNAs channel layer 23 that adds Ga among the InNAs, and band gap is increased.
In Fig. 6, drawn equally and become the energy contour 64 of energy level spacing (energy gap) with InAs, but we see in of the present invention regional 63 and are in the zone of energy contour more than 64 at energy, be that (in the zone of x 〉=3y), the energy of GaInNAs layer is bigger than the energy of InAs layer for N concentration more than 3 times promptly in Ga concentration.As a result, the energy state shown in Figure 10 (b) is such, and we see can suppress charge carrier from InAs channel layer 24 (following be called simply " InAs layer ") overflowing to GaInNAs layer 23.Again, we see that the composition by making GaInNAs layer 23 for example is Ga
0.1In
0.9N
0.03As
0.97(composition 3. of Fig. 6) makes Ga concentration more than 0.1, can realize high speed motion up to the about 500GHz of big current range of about 600mA with single grid.In addition, make the GaInNAs layer form the thickness of 10nm respectively, the InAs layer forms the thickness of 4nm.
Below, we illustrate the variation of this example.As first variation, replace GaInNAs channel layer 23, alternatively the GaInNAs layer of the InAs layer of each 3 layers ground laminated thickness 2nm and thickness 3nm forms GaInNAs/InAsMQW channel layer 23.Can obtain the result better slightly by this formation than above-mentioned formation.Thereby InAs layer that can the lamination multilayer has enlarged the scope of design condition.
At this moment, when making GaInNAs form Ga
0.1In
0.9N
0.03As
0.97Composition (composition 3. of Fig. 6) time import 1% compression distortion, but when forming Ga
0.16In
0.84N
0.05As
0.95Composition (composition 4. of Fig. 6) time with the condition of InP lattice match under, can form the band gap identical with InAs.
Here, we see GaInNAs and InAs relatively, the conduction band can be with variable quantity big.The band gap of the conduction band of GaInNAs and InAs should be identical, forms Ga
0.2In
0.8N
0.045As
0.955Composition (composition 5. of Fig. 6).As a result, we see that can suppress charge carrier penetrates into the GaInNAs layer, and responsiveness can improve about 10%.
Again, in this MQW channel layer 23, also can replace the GaInNAs layer, form the InNAs layer of following composition.That is, because in the InAs layer, import the compression distortion, so by in the InNAs layer, importing expansion distortion, the stably a plurality of InAs channel layers of lamination.We see the layer as InNAs, up to the InN that imports 1% compression distortion
0.1As
0.9Composition (composition 6. of Fig. 6) can both grow stable stromatolithic structure.
As mentioned above, even if we see in the situation that lamination InAs layer and GaInNAs layer are used, if Ga concentration in from 0 to 20% scope, N concentration then also can reach the purpose that improves responsiveness in from 3% to 10% scope.
At above execution mode, that is, in the composition of channel layer shown in Figure 6,, form InAs but pass through in InAsN, to add P by in InAsN, adding the purpose that Ga can realize increasing band gap
1-y-xN
yP
zAlso can increase band gap.We see in the situation of P, make P consist of about 3 times (z=3y) of N concentration in order to hold with the same dependency need of Ga.Even if because the upper limit of N concentration is at InAs
1-y-zN
yP
zIn also below 10%, so obtain 0.03＜y＜0.1,0＜z＜0.3.At this moment, in the situation of carrying out crystal growth, because need behind growth first channel layer, remove P fully, so exist the such problem of growth time lengthening, but because the variation of conduction band side is big in the variation of band gap, so operating current is increased a little.
In the composition of GaInNAs channel layer shown in Figure 6, also As can be replaced as Sb again.Because the mobility ratio InAs of InSb is big, can realize the high speed of HEMT.We think that the GaInNSb channel layer more produces effect than GaInNAs channel layer.
Again, second variation as present embodiment, can adopt first, second wall 25a, the 25b through constituting respectively as shown in figure 11 by InAlAs, both sides at GaInAs channel layer 23 and first, second InAs channel layer 24a, 24b form first, second charge carrier supplying layer 26a, the 26b that is made of the δ doped region, the double channel that forms first, second InAs channel layer 24a, 24b in the both sides of GaInNAs channel layer 23 is constructed (promptly, in the double channel structure of Fig. 9, with the structure of GaInNAs channel layer 23 displacement InNAs channel layers 23).
In this case, we see that can count increase by the increase raceway groove flows through the magnitude of current.
(execution mode 4)
Figure 12 is the block diagram of the formation of the expression transceiver relevant with embodiments of the present invention 4.
The present embodiment illustration transceiver of the hetero-field effect transistor of execution mode 1 to 3.
In Figure 12, transceiver 302 is wireless terminals.This transceiver 302 has antenna 321, amplification is sent to it the transmission enlarging section 313 of antenna 321 and at carrier wave generation transmission electric wave signal it is sent to the control part 325 of transmission enlarging section 313 from taking out received signal from the reception electric wave signal that receives enlarging section 312 and will sending signal overlap from reception enlarging section 312, the amplification transmission electric wave signal of the reception electric wave signal of antenna 321.
And, receive enlarging section 312 and sending the hetero-field effect transistor of use execution mode 1 to 3 in the amplifier etc. of enlarging section 313.Because this hetero-field effect transistor is as mentioned above, with existing example relatively can high speed motion, so the transceiver 302 of present embodiment also can compatibly be used for than the high frequency (for example frequency band of terahertz) of existing example.
As those of ordinary skill in the art,, can know many improvement of the present invention and other execution mode from above-mentioned explanation.Thereby above-mentioned explanation just is used to explain as illustration, provides in order to demonstrate enforcement best sample attitude of the present invention to those of ordinary skill in the art.In the scope that does not break away from spirit of the present invention, can change the detailed content of structure of the present invention and/or function in fact.
Industrial application possibility
The hetero-field effect transistor conduct relevant with the present invention is used for the high frequency transceiver Semiconductor elements etc. are useful.
Again, the manufacture method of the hetero-field effect transistor relevant with the present invention is as being used for high frequency The manufacture method of the semiconductor element of transceiver etc. is useful.
Again, the transceiver relevant with the present invention is useful as wireless terminal etc.
Claims (19)
1. hetero-field effect transistor is characterized in that having:
Substrate, the channel layer that on described substrate, forms through resilient coating, by the semiconductor with band gap bigger than described channel layer constitute and with heterogeneous wall that forms of this channel layer and the charge carrier supplying layer that forms in abutting connection with ground with described wall with engaging,
Described substrate is made of InP,
Described channel layer has by chemical formula Ga
xIn
1-xN
yA
1-yExpression, described A is As or Sb, described composition x is in the scope of 0≤x≤0.2, and described composition y is at the compound semiconductor layer of 0.03≤y≤0.10.
2. hetero-field effect transistor according to claim 1 is characterized in that:
Described composition y is in the scope of 0.03≤y≤0.07.
3. hetero-field effect transistor according to claim 1 is characterized in that:
Described A is As.
4. hetero-field effect transistor according to claim 1 is characterized in that:
Described A is Sb.
5. hetero-field effect transistor according to claim 1 is characterized in that:
Described channel layer only is made of described compound semiconductor layer.
6. hetero-field effect transistor according to claim 3 is characterized in that:
Described channel layer have first channel layer and with this first channel layer in abutting connection with and with heterozygous second channel layer of described wall, described first channel layer is made of described compound semiconductor layer, described second channel layer is made of the InAs layer.
7. hetero-field effect transistor according to claim 6 is characterized in that:
x＝0。
8. hetero-field effect transistor according to claim 6 is characterized in that:
The N concentration of described first channel layer is along with reducing near described second channel layer.
9. hetero-field effect transistor according to claim 6 is characterized in that:
Form a pair of described second channel layer in mode with the top and following adjacency of described first channel layer, to form a pair of described wall, form a pair of described charge carrier supplying layer in mode with described a pair of wall adjacency with the heterozygous mode of described a pair of second channel layer.
10. hetero-field effect transistor according to claim 6 is characterized in that:
0＜x≤0.2。
11. hetero-field effect transistor according to claim 10 is characterized in that:
Further satisfy 3y≤x≤0.2.
12. hetero-field effect transistor according to claim 10 is characterized in that:
Satisfy 0.1≤x≤0.2.
13. hetero-field effect transistor according to claim 6 is characterized in that:
Described first channel layer is by constituting as the GaInNAs layer of the described compound semiconductor layer of 0＜x≤0.2 and the GaInNAs/InAs layer of the multiple quantum trap structure that the mutual lamination of InAs layer forms.
14. hetero-field effect transistor according to claim 6 is characterized in that:
Described first channel layer is by constituting as the InNAs layer of the described compound semiconductor layer of x=0 and the InNAs/InAs layer of the multiple quantum trap structure that the mutual lamination of InAs layer forms.
15. hetero-field effect transistor according to claim 1 is characterized in that:
Described resilient coating and described wall are made of the InAlAs layer, and described charge carrier supplying layer is made of the n-InAlAs layer.
16. the manufacture method of a hetero-field effect transistor is characterized in that, has,
The channel layer that forms channel layer through resilient coating on described substrate forms operation;
Form operation with the wall that forms the wall that constitutes by semiconductor with the heterozygous mode of described channel layer with band gap bigger than described channel layer; With
The current-carrying sublayer that forms the charge carrier supplying layer with described wall in abutting connection with ground forms operation,
Described substrate is made of InP,
Described channel layer has by chemical formula Ga
xIn
1-xN
yA
1-yExpression, described A is As or Sb, described composition x is in the scope of 0≤x≤0.2, and the compound semiconductor layer of described composition y in the scope of 0.03≤y≤0.10.
17. the manufacture method of hetero-field effect transistor according to claim 16 is characterized in that:
In the operation that forms described channel layer, import Ionized N atom.
18. the manufacture method of hetero-field effect transistor according to claim 16 is characterized in that,
Have the resilient coating that on described InP substrate, forms the described resilient coating that constitutes by InAlAs and form operation,
Described channel layer forms operation to have second channel layer that forms operation and form second channel layer that is made of InAs on described first channel layer at first channel layer that forms first channel layer that is made of InNAs on the described resilient coating and forms operation,
Form in the operation at described wall, on described second channel layer, form the described wall that constitutes by InAlAs.
19. a transceiver is characterized in that:
In order to handle and to have the described hetero-field effect transistor of claim 1 to sending signal or received signal.
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| CN103117222B (en) * | 2013-01-18 | 2016-01-13 | 中国科学院半导体研究所 | The method of growth GaAs material HEMT device in ART structured channel |
| CN104637941B (en) * | 2015-02-04 | 2017-05-10 | 桂林电子科技大学 | Composite channel MHEMT (Metamorphic High Electron Mobility Transistor) microwave oscillator and preparation method thereof |
| US9536962B1 (en) * | 2015-07-20 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain regions for high electron mobility transistors (HEMT) and methods of forming same |
| CN111524996A (en) * | 2020-04-29 | 2020-08-11 | 中山德华芯片技术有限公司 | Infrared detector epitaxial wafer containing rare nitrogen compound |
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| JP2000091559A (en) * | 1998-09-14 | 2000-03-31 | Fujitsu Ltd | Compound semiconductor device and manufacture thereof |
| JP2000164852A (en) * | 1998-11-25 | 2000-06-16 | Hitachi Cable Ltd | Gallium-indium-nitride-arsenide based epitaxial wafer and high electron mobility transistor using the same |
| JP2000216101A (en) * | 1999-01-25 | 2000-08-04 | Sharp Corp | Crystal growth method of compound semiconductor mixed crystal and compound semiconductor device |
| JP2002094187A (en) * | 2000-09-18 | 2002-03-29 | Hitachi Ltd | Semiconductor laser and optical communication system using it |
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| JP2000091559A (en) * | 1998-09-14 | 2000-03-31 | Fujitsu Ltd | Compound semiconductor device and manufacture thereof |
| JP2000164852A (en) * | 1998-11-25 | 2000-06-16 | Hitachi Cable Ltd | Gallium-indium-nitride-arsenide based epitaxial wafer and high electron mobility transistor using the same |
| JP2000216101A (en) * | 1999-01-25 | 2000-08-04 | Sharp Corp | Crystal growth method of compound semiconductor mixed crystal and compound semiconductor device |
| JP2002094187A (en) * | 2000-09-18 | 2002-03-29 | Hitachi Ltd | Semiconductor laser and optical communication system using it |
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