JPH02266569A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPH02266569A JPH02266569A JP1087691A JP8769189A JPH02266569A JP H02266569 A JPH02266569 A JP H02266569A JP 1087691 A JP1087691 A JP 1087691A JP 8769189 A JP8769189 A JP 8769189A JP H02266569 A JPH02266569 A JP H02266569A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gaas
- substrate
- type
- type gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 abstract description 5
- 229910001634 calcium fluoride Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 13
- 239000010408 film Substances 0.000 description 11
- 238000001259 photo etching Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002222 fluorine compounds Chemical class 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000157282 Aesculus Species 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 235000010181 horse chestnut Nutrition 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電界効果トランジスタに関し、さらに詳しく
は、ＧａＡｓ絶縁ゲート電界効果トランジスタ（以下、
ＭＩＳＦＥＴと称す）の素子構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to field effect transistors, and more particularly to GaAs insulated gate field effect transistors (hereinafter referred to as
(referred to as MISFET).
現在、電力用スイッチング素子として、２重拡散技術を
用いたＳ１パワ−ＭＯ５ＦＥＴが使われている。しかし
、この素子は、高耐圧構造ではＯＮ抵抗が高くなってし
まい大電流を流すのが難しい。Currently, an S1 power MO5FET using double diffusion technology is used as a power switching element. However, this element has a high withstand voltage structure and has a high ON resistance, making it difficult to flow a large current.
これに対して、導電変調型ＭＯ３ＦＥＴが提案されてい
るが、素子構造１作製プロセス等の問題がある。In response to this, a conductivity modulation type MO3FET has been proposed, but there are problems such as the manufacturing process of the element structure 1.
そこでＳｉに代わって、高移動度を有するＧａＡｓを用
いればＳ１パワ−ＭＯ３ＦＥＴに比べて大電流。Therefore, if GaAs, which has high mobility, is used instead of Si, the current will be larger than that of the S1 power MO3FET.
高耐圧の素子が実現できる可能性がある。There is a possibility that devices with high breakdown voltage can be realized.
ＧａＡｓを用いた場合のチャネル構造としては、ＧａＡ
ｓ ／＾１ＧａＡｓ等の半導体ヘテロ界面の２次元電子
を利用するもの、ＣａＦ２／ＧａＡｓ等の弗化物とＧａ
Ａｓ界面の反転層を利用するものが考えられる。The channel structure when using GaAs is GaAs.
s/^1 Those that utilize two-dimensional electrons at the hetero interface of semiconductors such as GaAs, fluorides such as CaF2/GaAs, and Ga
One possibility is to use an inversion layer at the As interface.
しかし、ウェハーコスト、ウェハーサイズ、強度、熱伝
導１重さ等で、ＳｉｌまＧａＡｓよりも優れてふリ、）
−９ルコ：２．トチＧａＡｓ −Ｍ Ｉ Ｓ Ｆ Ｅ
ＴはＳｒ・ＭＯＳＦＥＴに対し充分な優位性を持たない
と考えられる。However, it is superior to Sil or GaAs in terms of wafer cost, wafer size, strength, heat conduction, weight, etc.)
-9 Luko: 2. Horse chestnut GaAs-M I S F E
It is considered that T does not have sufficient superiority over Sr MOSFET.
エピタキシャル成長させたＣａＦ２膜をゲート絶縁膜と
して用いて製作されたＧａＡｓ−ＭＩＳＦＥＴを第３ｒ
ｉ！Ｊに示す。A GaAs-MISFET fabricated using an epitaxially grown CaF2 film as a gate insulating film was
i! Shown in J.
他方、ＳＩ基板上へのＧａＡｓのヘテロエピタキシー技
術が最近注目されている。すなわち、Ｓｉ基板とＧａＡ
ｓ成長層間の格子不整合（格子定数差４．１％）を緩和
するだめのバッファ層形成技術として、２段階成長法や
、歪超格子を用いる方法等が提案されている。前者は成
長層と同じ材料のｎｍ程度のごく薄い膜（バッファ層）
を低温でまず成長させ、次に通常の成長温度でエピタキ
シャル成長を行うもの、後者は超格子をバッファ層とす
るものであり、ともにバッファ層でミスフィツト転移を
吸収し、良質の成長層を得ようとするものである。On the other hand, GaAs heteroepitaxy technology on SI substrates has recently attracted attention. That is, Si substrate and GaA
A two-step growth method, a method using a strained superlattice, and the like have been proposed as techniques for forming a buffer layer to alleviate the lattice mismatch (difference in lattice constant of 4.1%) between the s-grown layers. The former is a very thin film (buffer layer) on the order of nanometers made of the same material as the growth layer.
The latter method uses a superlattice as a buffer layer to absorb misfit transitions and obtain a high-quality growth layer. It is something to do.
従来、第３図に示す如き構造のＧａＡｓ−Ｍ Ｔ Ｓ
ＦＥＴが製作されているが、充分な高耐圧性、大型に特
性を得られない問題点があった。Conventionally, GaAs-MTS with a structure as shown in FIG.
Although FETs have been manufactured, they have had the problem of not being able to achieve sufficiently high voltage resistance and characteristics in large sizes.
また、ウェハーコスト、ウェハーサイズ、強度熱伝導１
重さ等では、むしろＧａＡｓを用いるとＳｉよりも劣る
問題点があった。In addition, wafer cost, wafer size, strength thermal conductivity 1
In terms of weight, etc., the use of GaAs actually had the problem of being inferior to Si.
従って、本発明の目的とするところはＧａＡｓを用いて
充分な高耐圧性と大電流特性とを得ることができると共
に、Ｓｌの利点をも取り入れた構造のＭＩＳＦＥＴを提
供することにある。Therefore, an object of the present invention is to provide a MISFET having a structure that can obtain sufficient high voltage resistance and large current characteristics using GaAs, and also incorporates the advantages of Sl.
本発明の電界効果トランジスタは、第１導電型のＳｉ基
板上に形成された第１導電型ＧａＡｓの第１領域と、そ
の第１領域の表面に選択的に形成された第２導電型Ｇａ
ＡＳの第２領域と、この第２領域の表面に選択的に形成
された高不純物濃度で第１導電型ＧａＡｓの第３領域と
、前記第１領域と第３領域の一部とそれらの間に挟まれ
た第２領域の一部の上に形成されたゲート絶縁膜と、そ
のゲート絶縁膜の上に形成さたゲート電極と、前記第２
領域の他の一部と前記第３領域の他の一部の表面に同時
にコンタクトするよう形成されたソース電極と、前記Ｇ
ａＡｓ基板の表面に形成されたドレイン電極とを具備し
てなり、前記ゲート絶縁膜とのヘテロ界面での反転層を
チャネルとすることを構成上の特徴とするものである。The field effect transistor of the present invention includes a first region of first conductivity type GaAs formed on a first conductivity type Si substrate, and a second conductivity type GaAs selectively formed on the surface of the first region.
a second region of AS, a third region of first conductivity type GaAs with a high impurity concentration selectively formed on the surface of the second region, and a portion of the first region and the third region and between them. a gate insulating film formed on a part of the second region sandwiched by the second region; a gate electrode formed on the gate insulating film;
a source electrode formed to simultaneously contact the surface of another part of the third region and the other part of the third region;
A drain electrode is formed on the surface of an aAs substrate, and the structure is characterized in that an inversion layer at the hetero interface with the gate insulating film serves as a channel.
Ｓｉ基板を用いることで、コスト等を低減できる。 By using a Si substrate, costs etc. can be reduced.
また、ＦＥＴ特性はＳ１上のＧａＡＳ部で決まり、以下
のように高耐圧、大電流化が可能となる。すなわち、ゲ
ート電圧によりゲート絶縁膜とＧａＡｓの界面にポテン
シャルの井戸すなわち反転層が形成され、チャネルとな
る。電流は、ドレイン電極からＧａＡｓ基板および第１
領域内を流れ、前記チャネルを通ってソース電極に流れ
る。この縦型構造のためＯＮ抵抗が低くなり大電流特性
が得られる。また、ドレイン電圧が上昇すると、空乏層
が第１領域に広がって電圧を保持するので、高耐圧特性
が得られる。Further, the FET characteristics are determined by the GaAS portion on S1, and as described below, high breakdown voltage and large current are possible. That is, a potential well or inversion layer is formed at the interface between the gate insulating film and GaAs by the gate voltage, and becomes a channel. The current flows from the drain electrode to the GaAs substrate and the first
flow within the region and through the channel to the source electrode. This vertical structure reduces ON resistance and provides large current characteristics. Further, when the drain voltage increases, the depletion layer spreads to the first region and maintains the voltage, resulting in high breakdown voltage characteristics.
以下、図に示す実施例により本発明をさらに詳しく説明
する。なお、これにより本発明が限定されるものではな
い。Hereinafter, the present invention will be explained in more detail with reference to embodiments shown in the drawings. Note that the present invention is not limited thereby.
第１図は本発明の一実施例のＭＩＳＦＥＴＩを示すもの
であって、ｎ＋型Ｓｉ基板２上にｎ型ＧａＡｓの第１領
域３が形成され、その第１領域３の表面に選択的にｐ＋
型ＧａＡｓとｐ−型ＧａＡｓの第２領域４゜５が形成さ
れ、その第２領域４，５０表面に選択的に ｎ゛型Ｇａ
Ａｓの第３領域６が形成されている。FIG. 1 shows a MISFET I according to an embodiment of the present invention, in which a first region 3 of n-type GaAs is formed on an n+-type Si substrate 2, and p+
A second region 4.5 of type GaAs and p-type GaAs is formed, and n-type Ga is selectively formed on the surfaces of the second regions 4 and 50.
A third region 6 of As is formed.
第１領域３と第３領域６の一部とそれらの間に挟まれた
第２領域の一部５の上にはＣａＦ２のゲート絶縁膜７が
形成され、その上にＡ１のゲート電極８が形成されてい
る。また、第２領域４の他の一部４と第３領域６の他の
一部の表面に同時にコンタクトするように＾ｕＺｎ ／
＾Ｕと＾ｕＧｅのソース電極１０ｂ。A gate insulating film 7 of CaF2 is formed on a part of the first region 3 and a part of the third region 6 and a part 5 of the second region sandwiched between them, and a gate electrode 8 of A1 is formed thereon. It is formed. Further, ^uZn/
＾U and ＾uGe source electrodes 10b.
１０ａが形成され、また、ＧａＡｓ基板２の裏面には＾
ｌのドレイン電極が形成されている。さらに、ＳｉＯ□
のアイソレーション層１１が形成されている。10a is formed, and on the back surface of the GaAs substrate 2,
1 drain electrodes are formed. Furthermore, SiO□
An isolation layer 11 is formed.
第３図（ａ）〜（ｉ）は、上記ＭＩＳＦＥＴの製造工程
を各々示したものである。以下、順に説明する。FIGS. 3(a) to 3(i) each show the manufacturing process of the above-mentioned MISFET. Below, they will be explained in order.
（ａ） ｎ”型Ｓｉ （Ｉ ＸＩＯ”ｃ＋ａ−’、
３００μｍ）を基板２上にｎ型ＧａＡｓ（〜ｌ ＸＩＯ
”ｃｌｌ−’、 ４０ μｍ）をＭＯＣＶＤ法を用いた
２段階成長法でエピタキシャル成長させて第１領域３を
形成する。すなわち、まず第１段階として、Ｓｉ基板を
高温（９００℃）で処理し、その後４５０℃ないしそれ
以下でバッファ層（２０ｎｍ程度）の低温成長を行い、
次に第２段階として、成長温度７５０℃でｎ−ＧａＡｓ
を成長させた。(a) n" type Si (I XIO"c+a-',
300 μm) on the substrate 2 and n-type GaAs (~1XIO
"cll-', 40 μm)" is epitaxially grown using a two-step growth method using MOCVD to form the first region 3. That is, in the first step, the Si substrate is treated at high temperature (900° C.), After that, low-temperature growth of a buffer layer (about 20 nm) is performed at 450°C or lower,
Next, in the second step, n-GaAs was grown at a growth temperature of 750°C.
grew.
（ｂ） 第１領域３０表面にＳｌＯ□をスパッタまた
は蒸着し、フォトエツチングでマスクを形成し、口また
はＺｎのインプラ （ドーズＩ Ｉ ＸＩＯ”ｃｍ−’
、深さ３μｍ程度）を行い、ｐ＋型ＧａＡｓの第２領域
４を選択的に形成する。(b) SlO□ is sputtered or vapor-deposited on the surface of the first region 30, a mask is formed by photoetching, and a hole or Zn implant (dose I
, to a depth of about 3 μm) to selectively form the second region 4 of p+ type GaAs.
（ｃ） Ｓｉｎ、のマスクの一部を除去し、更にＭｇま
たは７口のインプラ （ドーズＩ Ｉ Ｘ １０” ｃ
ｍ−’ 、 深さ１μｍ）を行い、ｐ−型ＧａＡｓの
第２領域５を形成する。(c) Remove a part of the Sin mask and add Mg or 7 implants (dose I
m-', depth 1 μm) to form a second region 5 of p-type GaAs.
（ｄ） アニールにより、第２領域４，５を活性化す
る。(d) Activate the second regions 4 and 5 by annealing.
（ｅ） ５ｉｎ２のマスクを除去し、再び全面にＳｉｎ
、を被着し、フォトエツチングでマスク形成後、Ｓｌの
インプラ （ドーズ量Ｉ ＸＩＯ”ｃｍ−２，深さ０．
５ μｍ） を行い、ｎ＋型ＧａＡｓの第３領域６を
形成する。(e) Remove the 5in2 mask and apply Sin to the entire surface again.
, and after forming a mask by photo-etching, implantation of Sl (dose: I XIO" cm-2, depth 0.
5 μm) to form the third region 6 of n+ type GaAs.
（ｆ） アニールにより活性化し、５ｉｎ２のマスク
を除去し、全面に［：ａＦ、をエピタキシャル成長する
。具体的には、ＭＢＥ法を用い、表面を化学処理後、基
板温度４５０℃でＣａＦｚを成長した。 そして、フォ
トエツチングにより、図に示す如き部分以外のＣａＦ２
を除去する。これによりゲート絶縁膜７が形成される。(f) Activate by annealing, remove the 5in2 mask, and epitaxially grow [:aF] on the entire surface. Specifically, after chemically treating the surface using the MBE method, CaFz was grown at a substrate temperature of 450°C. Then, by photo-etching, CaF2 was removed in areas other than those shown in the figure.
remove. As a result, gate insulating film 7 is formed.
（ｇ） 表面および裏面にＡＩを被着し、表面側は図に
示す部分のみを残すようにエツチングする。ゲート絶縁
膜７上のＡ１層がゲート電極８となり、裏面のＡ１層が
ドレイン電極９となる。(g) Apply AI to the front and back sides, and etch the front side so that only the portion shown in the figure remains. The A1 layer on the gate insulating film 7 becomes the gate electrode 8, and the A1 layer on the back surface becomes the drain electrode 9.
（ｈ） 次にフォトエツチング工程を経て、第２領域
４上のみにＡｕＺｎ／＾Ｕを被着する。前記第３領域６
上のＡ１層と共にソース電極１０ａ、１０ｂとなる。(h) Next, AuZn/^U is deposited only on the second region 4 through a photo-etching process. Said third area 6
Together with the upper A1 layer, these become source electrodes 10a and 10b.
（ｉ） フォトエツチング工程を経て、Ｓ＋Ｏａのア
イソレーション層１１を図に示すように形成する。(i) Through a photoetching process, an isolation layer 11 of S+Oa is formed as shown in the figure.
以上によりＭＩＳＦＥＴＩが製造される。なお、ゲート
絶縁膜７として、ＣａＦ、の代わりに他の弗化物または
ＡＩＮのような窒化物を用いる場合でも同様なプロセス
で実現できる。MISFETI is manufactured through the above steps. It should be noted that the same process can be used to form the gate insulating film 7 using other fluorides or nitrides such as AIN instead of CaF.
また、＾’ＸＧａ＋−ｘＡＳまたはＺｎ５ｅを用いる場
合にも、電極との間にｎ＋型ＧａＡｓ層を形成する以外
は、上記と同様なプロセスで実現できる。また、エピタ
キシャル成長法は、ＭＢＥ法、ＶＰＥ法でも可能である
。Further, when using ^'XGa+-xAS or Zn5e, it can be realized by the same process as above except that an n+ type GaAs layer is formed between the electrodes. Further, the epitaxial growth method can also be an MBE method or a VPE method.
本発明の電界効果トランジスタは３１基板を用いること
で安価である。The field effect transistor of the present invention is inexpensive because it uses a 31 substrate.
また、基本的にはＧａＡｓ縦型ＦＥＴであるためドレイ
ン電流が大きく、半導体表面の利用効率が良い。また、
第１領域３が高耐圧化のための低濃度領域として働く。Furthermore, since it is basically a GaAs vertical FET, the drain current is large and the semiconductor surface is used efficiently. Also,
The first region 3 functions as a low concentration region for increasing the breakdown voltage.
さらに、Ｓｌより高移動度でバンドギャップの大きいＧ
ａＡｓを用いているから、高周波特性が良好となり、Ｏ
Ｎ抵抗も低くなり、高温動作も可能となる。Furthermore, G has a higher mobility and a larger bandgap than Sl.
Since aAs is used, high frequency characteristics are good and O
N resistance is also lowered, and high temperature operation is also possible.
第１表に上記ＭＩＳＦＥＴＩの特性を示す。また、比較
のためにＳｉ・ＭＯＳＦＥＴ（耐圧５００ Ｖ ／電流
容量１０Ａ、同１０００Ｖ１５Ａ）の特性を例示する。Table 1 shows the characteristics of the above MISFETI. Further, for comparison, the characteristics of a Si MOSFET (withstand voltage 500 V/current capacity 10 A, 1000 V 15 A) are illustrated.
第１表から理解されるように、チップ当たりの電流容攪
が３倍になると共に、アンペア当たりのコストも１／３
に低減し得る。As can be seen from Table 1, the current capacity per chip is tripled and the cost per ampere is reduced to 1/3.
can be reduced to
また、同−Ｓｉ基板上でのＳｉ素子との複合化も可能で
ある。Further, it is also possible to combine it with a Si element on the same -Si substrate.
第 １ 表
〔発明の効果〕
本発明の電界効果トランジスタは、Ｓｉ基板を用いるこ
とで安価である。また、基本的にはＧａＡｓを用いた縦
型のＭＩＳ構造であるため、高速、低電力制御性、高耐
圧、大電流化に優れており、電力用スイッチング素子と
して極めて有用である。Table 1 [Effects of the Invention] The field effect transistor of the present invention is inexpensive because it uses a Si substrate. Moreover, since it basically has a vertical MIS structure using GaAs, it is excellent in high speed, low power controllability, high withstand voltage, and large current, and is extremely useful as a power switching element.
第１図は本発明の一実施例のＭＩＳＦＥＴの断面図、第
２図（ａ）〜（１）は第１図に示すＭＩＳＦＥＴの製造
工程を示す断面図、第３図は従来公知のＧａＡｓ −Ｍ
Ｉ Ｓ Ｆ Ｅ Ｔの断面図である。
１−Ｍ Ｔ Ｓ Ｆ Ｅ Ｔ、 ２−３＋基板、３ 第
１領域、４．５ 第２領域、６ 第３領域、７ ゲート
絶縁膜、８ ゲート電極、９ ドレイン電極、ｌ０ａ１
０ｂ ソース電極、１１ アイソレーション層。
第
図
（その１）
（その２）FIG. 1 is a cross-sectional view of a MISFET according to an embodiment of the present invention, FIGS. 2(a) to (1) are cross-sectional views showing the manufacturing process of the MISFET shown in FIG. 1, and FIG. 3 is a conventionally known GaAs- M
It is a sectional view of ISFET. 1-MTSFET, 2-3+ substrate, 3 first region, 4.5 second region, 6 third region, 7 gate insulating film, 8 gate electrode, 9 drain electrode, l0a1
0b source electrode, 11 isolation layer. Figure (Part 1) (Part 2)
Claims (1)
ａＡｓの第１領域と、その第１領域の表面に選択的に形
成された第２導電型ＧａＡｓの第２領域と、この第２領
域の表面に選択的に形成された高不純物濃度で第１導電
型ＧａＡｓの第３領域と、前記第１領域と第３領域の一
部とそれらの間に挟まれた第２領域の一部の上に形成さ
れたゲート絶縁膜と、そのゲート絶縁膜の上に形成され
たゲート電極と、前記第２領域の他の一部と前記第３領
域の他の一部の表面に同時にコンタクトするよう形成さ
れたソース電極と、前記ＧａＡｓ基板の裏面に形成され
たドレイン電極とを具備してなり、前記ゲート絶縁膜と
のヘテロ界面での反転層をチャネルとすることを特徴と
する電界効果トランジスタ。1) First conductivity type G formed on a first conductivity type Si substrate
A first region of aAs, a second region of second conductivity type GaAs selectively formed on the surface of the first region, and a first region of high impurity concentration selectively formed on the surface of the second region. a third region of conductive type GaAs; a gate insulating film formed on a portion of the first region and the third region; and a portion of the second region sandwiched therebetween; a gate electrode formed on the top, a source electrode formed so as to simultaneously contact the surfaces of another part of the second region and another part of the third region, and a source electrode formed on the back surface of the GaAs substrate. 1. A field-effect transistor, comprising a drain electrode, and an inversion layer at a hetero-interface with the gate insulating film serves as a channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087691A JPH02266569A (en) | 1989-04-06 | 1989-04-06 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087691A JPH02266569A (en) | 1989-04-06 | 1989-04-06 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02266569A true JPH02266569A (en) | 1990-10-31 |
Family
ID=13921952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1087691A Pending JPH02266569A (en) | 1989-04-06 | 1989-04-06 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02266569A (en) |
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| WO1995032525A1 (en) * | 1994-05-19 | 1995-11-30 | The Government Of The United States Of America, Represented By The Secretary Of The Navy | BaF2/GaAs ELECTRONIC COMPONENTS |
| US6077775A (en) * | 1998-08-20 | 2000-06-20 | The United States Of America As Represented By The Secretary Of The Navy | Process for making a semiconductor device with barrier film formation using a metal halide and products thereof |
| US6083818A (en) * | 1998-08-20 | 2000-07-04 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with strontium barrier film and process for making same |
| US6171953B1 (en) | 1998-08-20 | 2001-01-09 | The United States Of America As Represented By The Secretary Of The Navy | Processes for making electronic devices with rubidum barrier film |
| US6208001B1 (en) | 1994-05-19 | 2001-03-27 | The United States Of America As Represented By The Secretary Of The Navy | Gallium arsenide semiconductor devices fabricated with insulator layer |
| US6291876B1 (en) | 1998-08-20 | 2001-09-18 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with composite atomic barrier film and process for making same |
| US6351036B1 (en) | 1998-08-20 | 2002-02-26 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with a barrier film and process for making same |
| US6465887B1 (en) | 2000-05-03 | 2002-10-15 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with diffusion barrier and process for making same |
| US6720654B2 (en) | 1998-08-20 | 2004-04-13 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with cesium barrier film and process for making same |
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-
1989
- 1989-04-06 JP JP1087691A patent/JPH02266569A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208001B1 (en) | 1994-05-19 | 2001-03-27 | The United States Of America As Represented By The Secretary Of The Navy | Gallium arsenide semiconductor devices fabricated with insulator layer |
| US5932006A (en) * | 1994-05-19 | 1999-08-03 | The United States Of America As Represented By The Secretary Of The Navy | BaF2 /GaAs electronic components |
| US6306212B1 (en) | 1994-05-19 | 2001-10-23 | The United States Of America As Represented By The Secretary Of The Navy | Gallium arsenide semiconductor devices fabricated with insulator layer |
| WO1995032525A1 (en) * | 1994-05-19 | 1995-11-30 | The Government Of The United States Of America, Represented By The Secretary Of The Navy | BaF2/GaAs ELECTRONIC COMPONENTS |
| US6291876B1 (en) | 1998-08-20 | 2001-09-18 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with composite atomic barrier film and process for making same |
| US6171953B1 (en) | 1998-08-20 | 2001-01-09 | The United States Of America As Represented By The Secretary Of The Navy | Processes for making electronic devices with rubidum barrier film |
| US6188134B1 (en) | 1998-08-20 | 2001-02-13 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with rubidium barrier film and process for making same |
| US6144050A (en) * | 1998-08-20 | 2000-11-07 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with strontium barrier film and process for making same |
| US6083818A (en) * | 1998-08-20 | 2000-07-04 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with strontium barrier film and process for making same |
| US6077775A (en) * | 1998-08-20 | 2000-06-20 | The United States Of America As Represented By The Secretary Of The Navy | Process for making a semiconductor device with barrier film formation using a metal halide and products thereof |
| US6351036B1 (en) | 1998-08-20 | 2002-02-26 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with a barrier film and process for making same |
| US6566247B2 (en) | 1998-08-20 | 2003-05-20 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with composite atomic barrier film and process for making same |
| US6720654B2 (en) | 1998-08-20 | 2004-04-13 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with cesium barrier film and process for making same |
| US6734558B2 (en) | 1998-08-20 | 2004-05-11 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with barium barrier film and process for making same |
| US6465887B1 (en) | 2000-05-03 | 2002-10-15 | The United States Of America As Represented By The Secretary Of The Navy | Electronic devices with diffusion barrier and process for making same |
| US6881669B2 (en) | 2000-05-03 | 2005-04-19 | The United States Of America As Represented By The Secretary Of The Navy | Process for making electronic devices having a monolayer diffusion barrier |
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